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authorKeith Whitwell <keith@tungstengraphics.com>2002-07-03 10:35:45 +0000
committerKeith Whitwell <keith@tungstengraphics.com>2002-07-03 10:35:45 +0000
commitf53833d1ac4885e211db04cef86857cb4fbf463e (patch)
tree95ea071e12c1e099c71815bdb1443e218e566075 /linux
parent89b1bc3ee4e976d5cbd4bc1874ebcaf228aabb0c (diff)
new packet
Diffstat (limited to 'linux')
-rw-r--r--linux/radeon_drm.h3
-rw-r--r--linux/radeon_drv.h3
-rw-r--r--linux/radeon_state.c23
3 files changed, 21 insertions, 8 deletions
diff --git a/linux/radeon_drm.h b/linux/radeon_drm.h
index 69603480..bb6e5a6a 100644
--- a/linux/radeon_drm.h
+++ b/linux/radeon_drm.h
@@ -118,7 +118,8 @@
#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
-#define RADEON_MAX_STATE_PACKETS 50
+#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
+#define RADEON_MAX_STATE_PACKETS 51
/* Commands understood by cmd_buffer ioctl. More can be added but
diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h
index a052eabd..6e605e6f 100644
--- a/linux/radeon_drv.h
+++ b/linux/radeon_drv.h
@@ -481,6 +481,7 @@ extern int radeon_cp_flip( struct inode *inode, struct file *filp,
# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
# define RADEON_CNTL_PAINT_MULTI 0x00009A00
# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
+# define RADEON_CCE_SET_SCISSORS 0xC0001E00
#define RADEON_CP_PACKET_MASK 0xC0000000
#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
@@ -560,6 +561,8 @@ extern int radeon_cp_flip( struct inode *inode, struct file *filp,
#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
#define R200_SE_VTE_CNTL 0x20b0
#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
+#define R200_PP_TAM_DEBUG3 0x2d9c
+
#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
diff --git a/linux/radeon_state.c b/linux/radeon_state.c
index 03898df1..7c4757af 100644
--- a/linux/radeon_state.c
+++ b/linux/radeon_state.c
@@ -48,13 +48,21 @@ static inline void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n",
box->x1, box->y1, box->x2, box->y2 );
- BEGIN_RING( 4 );
- OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
- OUT_RING( (box->y1 << 16) | box->x1 );
- OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
-/* OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );*/
- OUT_RING( (box->y2 << 16) | box->x2 );
- ADVANCE_RING();
+#if 1
+ BEGIN_RING( 4 );
+ OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
+ OUT_RING( (box->y1 << 16) | box->x1 );
+ OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
+/* OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );*/
+ OUT_RING( (box->y2 << 16) | box->x2 );
+ ADVANCE_RING();
+#else
+ BEGIN_RING( 3 );
+ OUT_RING( CP_PACKET3( RADEON_CCE_SET_SCISSORS, 1 ));
+ OUT_RING( (box->y1 << 16) | box->x1 );
+ OUT_RING( (box->y2 << 16) | box->x2 );
+ ADVANCE_RING();
+#endif
}
/* Emit 1.1 state
@@ -271,6 +279,7 @@ static struct {
{ R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
{ R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
{ R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
+ { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
};