i915.o drm driver

13 files changed, 3469 insertions, 0 deletions

diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index 128932bb..6eb05693 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -186,3 +186,10 @@
 
 [ffb]
 
+[i915]
+0x8086 0x3577 "Intel i830M GMCH"
+0x8086 0x2562 "Intel i845G GMCH"
+0x8086 0x3582 "Intel i852GM/i855GM GMCH"
+0x8086 0x2572 "Intel i865G GMCH"
+0x8086 0x2582 "Intel i915G"
+
diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
new file mode 100644
index 00000000..80f643cd
--- /dev/null
+++ b/shared-core/i915_dma.c
@@ -0,0 +1,756 @@
+/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
+ */
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ **************************************************************************/
+
+#define __NO_VERSION__
+#include "i915.h"
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+
+static void i915_print_status_page(drm_device_t *dev)
+{
+      	drm_i915_private_t *dev_priv = dev->dev_private;
+	u32 *temp = dev_priv->hw_status_page;
+
+	if (!temp) {
+		DRM_DEBUG("no status page\n");
+		return;
+	}
+
+   	DRM_DEBUG(  "hw_status: Interrupt Status : %x\n", temp[0]);
+   	DRM_DEBUG(  "hw_status: LpRing Head ptr : %x\n", temp[1]);
+   	DRM_DEBUG(  "hw_status: IRing Head ptr : %x\n", temp[2]);
+      	DRM_DEBUG(  "hw_status: Reserved : %x\n", temp[3]);
+   	DRM_DEBUG(  "hw_status: Driver Counter : %d\n", temp[5]);
+
+}
+
+
+
+
+/* Really want an OS-independent resettable timer.  Would like to have
+ * this loop run for (eg) 3 sec, but have the timer reset every time
+ * the head pointer changes, so that EBUSY only happens if the ring
+ * actually stalls for (eg) 3 seconds.
+ */
+int i915_wait_ring( drm_device_t *dev, int n, const char *caller )
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+   	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
+	u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+	int i;
+
+	for ( i = 0 ; i < 10000 ; i++ ) {
+		ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+	   	ring->space = ring->head - (ring->tail+8);
+		if (ring->space < 0) ring->space += ring->Size;
+		if ( ring->space >= n )
+			return 0;
+		
+		dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
+
+		if (ring->head != last_head) 
+			i = 0;
+
+		last_head = ring->head;
+	}
+
+	return DRM_ERR(EBUSY);
+}
+
+void i915_kernel_lost_context(drm_device_t *dev)
+{
+      	drm_i915_private_t *dev_priv = dev->dev_private;
+   	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
+      
+   	ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+     	ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
+     	ring->space = ring->head - (ring->tail+8);
+     	if (ring->space < 0) ring->space += ring->Size;
+
+	if (ring->head == ring->tail)
+		dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
+}
+
+
+int i915_cleanup(drm_device_t *dev)
+{
+	/* Make sure interrupts are disabled here because the uninstall ioctl
+	 * may not have been called from userspace and after dev_private
+	 * is freed, it's too late.
+	 */
+	if (dev->irq) DRM(irq_uninstall)(dev);
+
+	if (dev->dev_private) {
+	   	drm_i915_private_t *dev_priv = 
+	     		(drm_i915_private_t *) dev->dev_private;
+	   
+	   	if (dev_priv->ring.virtual_start) {
+		   	DRM_IOREMAPFREE( &dev_priv->ring.map, dev);
+		}
+
+	   	if (dev_priv->hw_status_page) {
+			pci_free_consistent(dev->pdev, PAGE_SIZE,
+				      dev_priv->hw_status_page,
+				      dev_priv->dma_status_page);
+		   	/* Need to rewrite hardware status page */
+		   	I915_WRITE(0x02080, 0x1ffff000);
+		}
+
+	   	DRM(free)(dev->dev_private, sizeof(drm_i915_private_t), 
+			 DRM_MEM_DRIVER);
+
+	   	dev->dev_private = NULL;
+	}
+
+   	return 0;
+}
+
+
+
+static int i915_initialize(drm_device_t *dev, 
+			       drm_i915_private_t *dev_priv,
+			       drm_i915_init_t *init)
+{
+   	memset(dev_priv, 0, sizeof(drm_i915_private_t));
+
+	DRM_GETSAREA();
+	if(!dev_priv->sarea) {
+		DRM_ERROR("can not find sarea!\n");
+		dev->dev_private = (void *)dev_priv;
+		i915_cleanup(dev);
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_FIND_MAP( dev_priv->mmio_map, init->mmio_offset );
+	if(!dev_priv->mmio_map) {
+		dev->dev_private = (void *)dev_priv;
+		i915_cleanup(dev);
+		DRM_ERROR("can not find mmio map!\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	dev_priv->sarea_priv = (drm_i915_sarea_t *)
+		((u8 *)dev_priv->sarea->handle +
+		 init->sarea_priv_offset);
+
+   	dev_priv->ring.Start = init->ring_start;
+   	dev_priv->ring.End = init->ring_end;
+   	dev_priv->ring.Size = init->ring_size;
+   	dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
+		
+	dev_priv->ring.map.offset = init->ring_start;
+	dev_priv->ring.map.size = init->ring_size;
+	dev_priv->ring.map.type = 0;
+	dev_priv->ring.map.flags = 0;
+	dev_priv->ring.map.mtrr = 0;
+
+	DRM_IOREMAP( &dev_priv->ring.map, dev );
+
+   	if (dev_priv->ring.map.handle == NULL) {
+		dev->dev_private = (void *) dev_priv;
+	   	i915_cleanup(dev);
+	   	DRM_ERROR("can not ioremap virtual address for"
+			  " ring buffer\n");
+	   	return DRM_ERR(ENOMEM);
+	}
+
+   	dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
+   
+	dev_priv->back_offset = init->back_offset;
+	dev_priv->front_offset = init->front_offset;
+	dev_priv->current_page = 0;
+	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
+
+	/* We are using separate values as placeholders for mechanisms for
+	 * private backbuffer/depthbuffer usage.
+	 */
+	dev_priv->use_mi_batchbuffer_start = 0;
+
+	/* Allow hardware batchbuffers unless told otherwise.
+	 */
+	dev_priv->allow_batchbuffer = 1;
+
+   	/* Program Hardware Status Page */
+   	dev_priv->hw_status_page =
+		pci_alloc_consistent( dev->pdev, PAGE_SIZE, 
+						&dev_priv->dma_status_page );
+
+   	if (!dev_priv->hw_status_page) {
+		dev->dev_private = (void *)dev_priv;
+		i915_cleanup(dev);
+		DRM_ERROR("Can not allocate hardware status page\n");
+		return DRM_ERR(ENOMEM);
+	}
+   	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
+   
+   	I915_WRITE(0x02080, dev_priv->dma_status_page);
+	DRM_DEBUG("Enabled hardware status page\n");
+   
+	dev->dev_private = (void *)dev_priv;
+
+   	return 0;
+}
+
+
+static int i915_resume(drm_device_t *dev)
+{
+	drm_i915_private_t *dev_priv = 
+		(drm_i915_private_t *) dev->dev_private;
+
+	DRM_DEBUG( "%s\n", __FUNCTION__);
+		   
+	if(!dev_priv->sarea) {
+		DRM_ERROR("can not find sarea!\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	if(!dev_priv->mmio_map) {
+		DRM_ERROR("can not find mmio map!\n");
+		return DRM_ERR(EINVAL);
+	}
+
+   	if (dev_priv->ring.map.handle == NULL) {
+	   	DRM_ERROR("can not ioremap virtual address for"
+			  " ring buffer\n");
+	   	return DRM_ERR(ENOMEM);
+	}
+
+   	/* Program Hardware Status Page */
+   	if (!dev_priv->hw_status_page) {
+		DRM_ERROR("Can not find hardware status page\n");
+		return DRM_ERR(EINVAL);
+	}
+	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
+   
+   	I915_WRITE(0x02080, dev_priv->dma_status_page);
+	DRM_DEBUG("Enabled hardware status page\n");
+
+   	return 0;
+}
+
+
+int i915_dma_init( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+   	drm_i915_private_t *dev_priv;
+   	drm_i915_init_t init;
+   	int retcode = 0;
+	
+  	DRM_COPY_FROM_USER_IOCTL( init, (drm_i915_init_t *)data, sizeof(init));
+	
+   	switch(init.func) {
+	 	case I915_INIT_DMA:
+			dev_priv = DRM(alloc)(sizeof(drm_i915_private_t), 
+					      DRM_MEM_DRIVER);
+	   		if(dev_priv == NULL) 
+				return DRM_ERR(ENOMEM);
+	   		retcode = i915_initialize(dev, dev_priv, &init);
+	   	break;
+	 	case I915_CLEANUP_DMA:
+	   		retcode = i915_cleanup(dev);
+	   	break;
+		case I915_RESUME_DMA:
+			retcode = i915_resume(dev);
+	   	break;
+	 	default:
+	   		retcode = -EINVAL;
+	   	break;
+	}
+   
+   	return retcode;
+}
+
+
+
+/* Implement basically the same security restrictions as hardware does
+ * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
+ *
+ * Most of the calculations below involve calculating the size of a
+ * particular instruction.  It's important to get the size right as
+ * that tells us where the next instruction to check is.  Any illegal
+ * instruction detected will be given a size of zero, which is a
+ * signal to abort the rest of the buffer.
+ */
+static int do_validate_cmd( int cmd )
+{
+	switch (((cmd>>29) & 0x7)) {
+	case 0x0:
+		switch ((cmd>>23) & 0x3f) {
+		case 0x0: 
+			return 1; /* MI_NOOP */
+		case 0x4: 
+			return 1; /* MI_FLUSH */
+		default: 
+			return 0; /* disallow everything else */
+		}
+		break;
+	case 0x1: 
+		return 0;	/* reserved */
+	case 0x2: 
+		return (cmd & 0xff) + 2; /* 2d commands */
+	case 0x3:
+		if (((cmd>>24) & 0x1f) <= 0x18)
+			return 1;
+
+		switch ((cmd>>24) & 0x1f) {
+		case 0x1c: 
+			return 1;
+		case 0x1d:
+			return (cmd & 0xffff) + 2;
+		case 0x1e: 
+			if (cmd & (1<<23)) 
+				return (cmd & 0xffff) + 1;
+			else
+				return 1;
+		case 0x1f:
+			if ((cmd & (1<<23)) == 0) /* inline vertices */
+				return (cmd & 0x1ffff) + 2;
+			else if (cmd & (1<<17)) /* indirect random */
+				if ((cmd & 0xffff) == 0)
+					return 0; /* unknown length, too hard */
+				else
+					return (((cmd & 0xffff) + 1) / 2) + 1;
+			else
+				return 2; /* indirect sequential */
+		default: 
+			return 0;
+		}
+	default:
+		return 0;
+	}
+
+	return 0;
+}
+
+static int validate_cmd( int cmd )
+{
+	int ret = do_validate_cmd( cmd );
+	
+/* 	printk("validate_cmd( %x ): %d\n", cmd, ret); */
+
+	return ret;
+}
+	
+	
+
+static int i915_emit_cmds( drm_device_t *dev,
+			   int *buffer,
+			   int dwords )
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+	int i;
+	RING_LOCALS;
+
+	for (i = 0 ; i < dwords ; ) {
+		int cmd, sz;
+
+		if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
+			return DRM_ERR( EINVAL );
+
+/* 		printk("%d/%d ", i, dwords); */
+
+		if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) 
+			return DRM_ERR( EINVAL );
+
+		BEGIN_LP_RING( sz );
+		OUT_RING(cmd);
+
+		while (++i, --sz) {
+			if (DRM_COPY_FROM_USER_UNCHECKED( &cmd, &buffer[i], 
+							  sizeof(cmd))) {
+				return DRM_ERR( EINVAL );
+			}
+			OUT_RING(cmd);
+		}
+		ADVANCE_LP_RING();
+	}
+
+	return 0;
+}
+
+static int i915_emit_box( drm_device_t *dev,
+			  drm_clip_rect_t *boxes,
+			  int i,
+			  int DR1,
+			  int DR4)
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+   	drm_clip_rect_t box;
+   	RING_LOCALS;
+
+	if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) {
+		return EFAULT;
+	}
+
+	if (box.y2 <= box.y1 ||
+	    box.x2 <= box.x1 ||
+	    box.y2 <= 0 ||
+	    box.x2 <= 0) {
+		DRM_ERROR("Bad box %d,%d..%d,%d\n",
+			  box.x1, box.y1, box.x2, box.y2);
+		return DRM_ERR(EINVAL);
+	}
+				
+
+	BEGIN_LP_RING(6);
+	OUT_RING( GFX_OP_DRAWRECT_INFO );
+	OUT_RING( DR1 );
+	OUT_RING( (box.x1 & 0xffff) | (box.y1<<16) );
+	OUT_RING( ((box.x2-1) & 0xffff) | ((box.y2-1)<<16) );
+	OUT_RING( DR4 );
+	OUT_RING( 0 );
+	ADVANCE_LP_RING();
+	
+	return 0;
+}
+
+
+static int i915_dispatch_cmdbuffer(drm_device_t *dev, 
+				   drm_i915_cmdbuffer_t *cmd )
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+   	int nbox = cmd->num_cliprects;
+	int i = 0, count, ret;
+   	RING_LOCALS;
+
+	if (cmd->sz & 0x3) {
+		DRM_ERROR("alignment");
+		return DRM_ERR(EINVAL);
+	}
+		
+   	i915_kernel_lost_context(dev);
+
+	count = nbox ? nbox : 1;
+
+	for (i = 0 ; i < count ; i++) {
+		if (i < nbox) {
+			ret = i915_emit_box( dev, cmd->cliprects, i, 
+					     cmd->DR1, cmd->DR4);
+			if (ret) 
+				return ret;
+		}
+
+		ret = i915_emit_cmds( dev, (int *)cmd->buf, cmd->sz / 4 );
+		if (ret) 
+			return ret;
+	}
+
+	return 0;
+}
+
+
+
+
+static int i915_dispatch_batchbuffer(drm_device_t *dev, 
+				    drm_i915_batchbuffer_t *batch )
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+   	drm_clip_rect_t box, *boxes = batch->cliprects;
+   	int nbox = batch->num_cliprects;
+	int i = 0, count;
+   	RING_LOCALS;
+
+	if ((batch->start | batch->used) & 0x7) {
+		DRM_ERROR("alignment");
+		return DRM_ERR(EINVAL);
+	}
+		
+   	i915_kernel_lost_context(dev);
+
+	count = nbox ? nbox : 1;
+
+	for (i = 0 ; i < count ; i++) {
+		if (i < nbox) {
+			int ret = i915_emit_box( dev, boxes, i,
+						 batch->DR1, batch->DR4);
+			if (ret) 
+				return ret;
+		}
+
+		if (dev_priv->use_mi_batchbuffer_start) {
+			BEGIN_LP_RING(2);
+			OUT_RING( MI_BATCH_BUFFER_START | (2<<6) );
+			OUT_RING( batch->start | MI_BATCH_NON_SECURE );
+			ADVANCE_LP_RING();
+		} 
+		else {
+			BEGIN_LP_RING(4);
+			OUT_RING( MI_BATCH_BUFFER );
+			OUT_RING( batch->start | MI_BATCH_NON_SECURE );
+			OUT_RING( batch->start + batch->used - 4 );
+			OUT_RING( 0 );
+			ADVANCE_LP_RING();
+		}
+	}
+
+	
+	dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
+
+	BEGIN_LP_RING(4);
+	OUT_RING( CMD_STORE_DWORD_IDX );
+	OUT_RING( 20 );
+	OUT_RING( dev_priv->counter );
+	OUT_RING( 0 );
+	ADVANCE_LP_RING();
+
+	return 0;
+}
+
+static int i915_dispatch_flip( drm_device_t *dev )
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+	RING_LOCALS;
+
+	DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", 
+		   __FUNCTION__, 
+		   dev_priv->current_page,
+		   dev_priv->sarea_priv->pf_current_page);
+
+  	i915_kernel_lost_context(dev);
+
+
+	BEGIN_LP_RING( 2 );
+    	OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); 
+	OUT_RING( 0 );
+	ADVANCE_LP_RING();
+
+	BEGIN_LP_RING( 6 );
+	OUT_RING( CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP );	
+	OUT_RING( 0 );
+	if ( dev_priv->current_page == 0 ) {
+		OUT_RING( dev_priv->back_offset );
+		dev_priv->current_page = 1;
+	} else {
+		OUT_RING( dev_priv->front_offset );
+		dev_priv->current_page = 0;
+	}
+	OUT_RING(0);
+	ADVANCE_LP_RING();
+
+
+	BEGIN_LP_RING( 2 );
+	OUT_RING( MI_WAIT_FOR_EVENT |
+		  MI_WAIT_FOR_PLANE_A_FLIP );
+	OUT_RING( 0 );
+	ADVANCE_LP_RING();
+	
+
+	dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
+
+	BEGIN_LP_RING(4);
+	OUT_RING( CMD_STORE_DWORD_IDX );
+	OUT_RING( 20 );
+	OUT_RING( dev_priv->counter );
+	OUT_RING( 0 );
+	ADVANCE_LP_RING();
+
+	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
+	return 0;
+}
+
+
+static int i915_quiescent(drm_device_t *dev)
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+
+  	i915_kernel_lost_context(dev);
+	return i915_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ );
+}
+
+
+int i915_flush_ioctl( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i915_flush_ioctl called without lock held\n");
+		return DRM_ERR(EINVAL);
+	}
+
+    	return i915_quiescent(dev); 
+}
+
+int i915_batchbuffer( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+   	drm_i915_private_t *dev_priv = (drm_i915_private_t *)dev->dev_private;
+      	u32 *hw_status = dev_priv->hw_status_page;
+   	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 
+     					dev_priv->sarea_priv; 
+	drm_i915_batchbuffer_t batch;
+	int ret;
+
+	if (!dev_priv->allow_batchbuffer) {
+		DRM_ERROR("Batchbuffer ioctl disabled\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( batch, (drm_i915_batchbuffer_t *)data, 
+				  sizeof(batch) );
+
+	DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
+		  batch.start, batch.used, batch.num_cliprects);
+
+
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i915_batchbuffer called without lock held\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects, 
+						       batch.num_cliprects *
+						       sizeof(drm_clip_rect_t)))
+		return DRM_ERR(EFAULT);
+
+	ret = i915_dispatch_batchbuffer( dev, &batch );
+
+   	sarea_priv->last_dispatch = (int) hw_status[5];   
+	return ret;
+}
+
+int i915_cmdbuffer( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+   	drm_i915_private_t *dev_priv = (drm_i915_private_t *)dev->dev_private;
+      	u32 *hw_status = dev_priv->hw_status_page;
+   	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 
+		dev_priv->sarea_priv; 
+	drm_i915_cmdbuffer_t cmdbuf;
+	int ret;
+
+	DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_i915_cmdbuffer_t *)data, 
+				  sizeof(cmdbuf) );
+
+	DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
+		  cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
+
+
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i915_cmdbuffer called without lock held\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	if (cmdbuf.num_cliprects && 
+	    DRM_VERIFYAREA_READ(cmdbuf.cliprects, 
+				cmdbuf.num_cliprects *
+				sizeof(drm_clip_rect_t))) {
+		DRM_ERROR("Fault accessing cliprects\n");
+		return DRM_ERR(EFAULT);
+	}
+
+	ret = i915_dispatch_cmdbuffer( dev, &cmdbuf );
+	if (ret) {
+		DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
+		return ret;
+	}
+
+   	sarea_priv->last_dispatch = (int) hw_status[5];   
+	return 0;
+}
+
+
+
+int i915_do_cleanup_pageflip( drm_device_t *dev )
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	DRM_DEBUG("%s\n", __FUNCTION__);
+	if (dev_priv->current_page != 0)
+		i915_dispatch_flip( dev );
+
+	return 0;
+}
+
+int i915_flip_bufs( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+
+	DRM_DEBUG("%s\n", __FUNCTION__);
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i915_flip_buf called without lock held\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	return i915_dispatch_flip( dev );
+}
+
+
+
+int i915_getparam( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_getparam_t param;
+	int value;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t *)data, 
+				 sizeof(param));
+
+	switch( param.param ) {
+	case I915_PARAM_IRQ_ACTIVE:
+		value = dev->irq ? 1 : 0;
+		break;
+	case I915_PARAM_ALLOW_BATCHBUFFER:
+		value = dev_priv->allow_batchbuffer ? 1 : 0;
+		break;
+	default:
+		DRM_ERROR("Unkown parameter %d\n", param.param);
+		return DRM_ERR(EINVAL);
+	}
+
+	if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
+		DRM_ERROR("DRM_COPY_TO_USER failed\n");
+		return DRM_ERR(EFAULT);
+	}
+	
+	return 0;
+}
+
+
+int i915_setparam( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_setparam_t param;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( param, (drm_i915_setparam_t *)data, 
+				  sizeof(param) );
+
+	switch( param.param ) {
+	case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
+		dev_priv->use_mi_batchbuffer_start = param.value;
+		break;
+	case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
+		dev_priv->tex_lru_log_granularity = param.value;
+		break;
+	case I915_SETPARAM_ALLOW_BATCHBUFFER:
+		dev_priv->allow_batchbuffer = param.value;
+		break;
+	default:
+		DRM_ERROR("unknown parameter %d\n", param.param);
+		return DRM_ERR(EINVAL);
+	}
+
+
+	return 0;
+}
diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
new file mode 100644
index 00000000..707e553c
--- /dev/null
+++ b/shared-core/i915_drm.h
@@ -0,0 +1,162 @@
+#ifndef _I915_DRM_H_
+#define _I915_DRM_H_
+
+/* Please note that modifications to all structs defined here are
+ * subject to backwards-compatibility constraints.
+ */
+
+#include "drm.h"
+
+/* Each region is a minimum of 16k, and there are at most 255 of them.
+ */
+#define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
+				 * of chars for next/prev indices */
+#define I915_LOG_MIN_TEX_REGION_SIZE 14
+
+
+typedef struct _drm_i915_init {
+	enum {
+		I915_INIT_DMA = 0x01,
+		I915_CLEANUP_DMA = 0x02,
+		I915_RESUME_DMA = 0x03
+	} func;
+	unsigned int mmio_offset;
+	int sarea_priv_offset;
+	unsigned int ring_start;
+	unsigned int ring_end;
+	unsigned int ring_size;
+	unsigned int front_offset;
+	unsigned int back_offset;
+	unsigned int depth_offset;
+	unsigned int w;
+	unsigned int h;
+	unsigned int pitch;
+	unsigned int pitch_bits;
+	unsigned int back_pitch;
+	unsigned int depth_pitch;
+	unsigned int cpp;
+        unsigned int chipset;
+} drm_i915_init_t;
+
+
+typedef struct _drm_i915_sarea {
+	drm_tex_region_t texList[I915_NR_TEX_REGIONS+1];
+        int last_upload;	/* last time texture was uploaded */
+        int last_enqueue;	/* last time a buffer was enqueued */
+	int last_dispatch;	/* age of the most recently dispatched buffer */
+	int ctxOwner;		/* last context to upload state */
+	int texAge;
+        int pf_enabled;		/* is pageflipping allowed? */
+        int pf_active;               
+        int pf_current_page;	/* which buffer is being displayed? */
+        int perf_boxes;	        /* performance boxes to be displayed */   
+} drm_i915_sarea_t;
+
+/* Flags for perf_boxes
+ */
+#define I915_BOX_RING_EMPTY    0x1 
+#define I915_BOX_FLIP          0x2 
+#define I915_BOX_WAIT          0x4 
+#define I915_BOX_TEXTURE_LOAD  0x8 
+#define I915_BOX_LOST_CONTEXT  0x10 
+
+
+/* I915 specific ioctls
+ * The device specific ioctl range is 0x40 to 0x79.
+ */
+#define DRM_IOCTL_I915_INIT		DRM_IOW( 0x40, drm_i915_init_t)
+#define DRM_IOCTL_I915_FLUSH		DRM_IO ( 0x41)
+#define DRM_IOCTL_I915_FLIP		DRM_IO ( 0x42)
+#define DRM_IOCTL_I915_BATCHBUFFER	DRM_IOW( 0x43, drm_i915_batchbuffer_t)
+#define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(0x44, drm_i915_irq_emit_t)
+#define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( 0x45, drm_i915_irq_wait_t)
+#define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(0x46, drm_i915_getparam_t)
+#define DRM_IOCTL_I915_SETPARAM         DRM_IOW( 0x47, drm_i915_setparam_t)
+#define DRM_IOCTL_I915_ALLOC            DRM_IOWR(0x48, drm_i915_mem_alloc_t)
+#define DRM_IOCTL_I915_FREE             DRM_IOW( 0x49, drm_i915_mem_free_t)
+#define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( 0x4a, drm_i915_mem_init_heap_t)
+#define DRM_IOCTL_I915_CMDBUFFER	DRM_IOW( 0x4b, drm_i915_cmdbuffer_t)
+
+
+/* Allow drivers to submit batchbuffers directly to hardware, relying
+ * on the security mechanisms provided by hardware.
+ */
+typedef struct _drm_i915_batchbuffer {
+   	int start;		/* agp offset */
+	int used;		/* nr bytes in use */
+	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
+        int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO*/
+	int num_cliprects;	/* mulitpass with multiple cliprects? */
+        drm_clip_rect_t *cliprects; /* pointer to userspace cliprects */
+} drm_i915_batchbuffer_t;
+
+/* As above, but pass a pointer to userspace buffer which can be
+ * validated by the kernel prior to sending to hardware.
+ */
+typedef struct _drm_i915_cmdbuffer {
+   	char *buf;	        /* pointer to userspace command buffer */
+	int sz;		        /* nr bytes in buf */
+	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
+        int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO*/
+	int num_cliprects;	/* mulitpass with multiple cliprects? */
+        drm_clip_rect_t *cliprects; /* pointer to userspace cliprects */
+} drm_i915_cmdbuffer_t;
+
+
+/* Userspace can request & wait on irq's:
+ */
+typedef struct drm_i915_irq_emit {
+	int *irq_seq;
+} drm_i915_irq_emit_t;
+
+typedef struct drm_i915_irq_wait {
+	int irq_seq;
+} drm_i915_irq_wait_t;
+
+
+/* Ioctl to query kernel params:
+ */
+#define I915_PARAM_IRQ_ACTIVE            1
+#define I915_PARAM_ALLOW_BATCHBUFFER     2
+
+typedef struct drm_i915_getparam {
+	int param;
+	int *value;
+} drm_i915_getparam_t;
+
+
+/* Ioctl to set kernel params:
+ */
+#define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
+#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
+#define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
+
+typedef struct drm_i915_setparam {
+	int param;
+	int value;
+} drm_i915_setparam_t;
+
+/* A memory manager for regions of shared memory:
+ */
+#define I915_MEM_REGION_AGP 1
+
+typedef struct drm_i915_mem_alloc {
+	int region;
+	int alignment;
+	int size;
+	int *region_offset;	/* offset from start of fb or agp */
+} drm_i915_mem_alloc_t;
+
+typedef struct drm_i915_mem_free {
+	int region;
+	int region_offset;
+} drm_i915_mem_free_t;
+
+typedef struct drm_i915_mem_init_heap {
+	int region;
+	int size;
+	int start;	
+} drm_i915_mem_init_heap_t;
+
+
+#endif /* _I915_DRM_H_ */
diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
new file mode 100644
index 00000000..ba306c65
--- /dev/null
+++ b/shared-core/i915_drv.h
@@ -0,0 +1,228 @@
+/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
+ */
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ **************************************************************************/
+
+#ifndef _I915_DRV_H_
+#define _I915_DRV_H_
+
+
+typedef struct _drm_i915_ring_buffer{
+	int tail_mask;
+	unsigned long Start;
+	unsigned long End;
+	unsigned long Size;
+	u8 *virtual_start;
+	int head;
+	int tail;
+	int space;
+	drm_local_map_t map;
+} drm_i915_ring_buffer_t;
+
+struct mem_block {
+	struct mem_block *next;
+	struct mem_block *prev;
+	int start;
+	int size;
+	DRMFILE filp;		/* 0: free, -1: heap, other: real files */
+};
+
+typedef struct drm_i915_private {
+	drm_local_map_t *sarea;
+	drm_local_map_t *mmio_map;
+
+	drm_i915_sarea_t *sarea_priv;
+   	drm_i915_ring_buffer_t ring;
+
+      	void * hw_status_page;
+   	unsigned long counter;
+	dma_addr_t dma_status_page;
+
+	
+	int back_offset;
+	int front_offset;
+	int current_page;
+	int page_flipping;
+	int use_mi_batchbuffer_start;
+	
+
+	wait_queue_head_t irq_queue;
+   	atomic_t irq_received;
+   	atomic_t irq_emitted;
+
+	int tex_lru_log_granularity;
+	int allow_batchbuffer;
+	struct mem_block *agp_heap;
+} drm_i915_private_t;
+
+				/* i915_dma.c */
+extern int i915_dma_init( DRM_IOCTL_ARGS );
+extern int i915_cleanup(drm_device_t *dev);
+extern int i915_flush_ioctl( DRM_IOCTL_ARGS );
+extern int i915_batchbuffer( DRM_IOCTL_ARGS );
+extern int i915_flip_bufs( DRM_IOCTL_ARGS );
+extern int i915_getparam(  DRM_IOCTL_ARGS );
+extern int i915_setparam(  DRM_IOCTL_ARGS );
+extern int i915_cmdbuffer( DRM_IOCTL_ARGS );
+extern void i915_kernel_lost_context(drm_device_t *dev);
+
+/* i915_irq.c */
+extern int i915_irq_emit(  DRM_IOCTL_ARGS );
+extern int i915_irq_wait(  DRM_IOCTL_ARGS );
+extern int i915_wait_irq(drm_device_t *dev, int irq_nr);
+extern int i915_emit_irq(drm_device_t *dev);
+
+
+/* i915_mem.c */
+extern int i915_mem_alloc( DRM_IOCTL_ARGS );
+extern int i915_mem_free( DRM_IOCTL_ARGS );
+extern int i915_mem_init_heap( DRM_IOCTL_ARGS );
+extern void i915_mem_takedown( struct mem_block **heap );
+extern void i915_mem_release( drm_device_t *dev, 
+			      DRMFILE filp, struct mem_block *heap );
+
+#define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, reg)
+#define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, reg, val)
+#define I915_READ16(reg) 	DRM_READ16(dev_priv->mmio_map, reg)
+#define I915_WRITE16(reg,val)	DRM_WRITE16(dev_priv->mmio_map, reg, val)
+
+
+
+#define I915_VERBOSE 0
+
+#define RING_LOCALS	unsigned int outring, ringmask, outcount; \
+                        volatile char *virt;
+
+#define BEGIN_LP_RING(n) do {				\
+	if (I915_VERBOSE)				\
+		DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",	\
+			  n, __FUNCTION__);		\
+	if (dev_priv->ring.space < n*4)			\
+		i915_wait_ring(dev, n*4, __FUNCTION__);		\
+	outcount = 0;					\
+	outring = dev_priv->ring.tail;			\
+	ringmask = dev_priv->ring.tail_mask;		\
+	virt = dev_priv->ring.virtual_start;		\
+} while (0)
+
+
+#define OUT_RING(n) do {					\
+	if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
+	*(volatile unsigned int *)(virt + outring) = n;		\
+        outcount++;						\
+	outring += 4;						\
+	outring &= ringmask;					\
+} while (0)
+
+#define ADVANCE_LP_RING() do {						\
+	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);	\
+	dev_priv->ring.tail = outring;					\
+	dev_priv->ring.space -= outcount * 4;				\
+	I915_WRITE(LP_RING + RING_TAIL, outring);			\
+} while(0)
+
+extern int i915_wait_ring(drm_device_t *dev, int n, const char *caller);
+
+
+#define GFX_OP_USER_INTERRUPT 		((0<<29)|(2<<23))
+#define GFX_OP_BREAKPOINT_INTERRUPT	((0<<29)|(1<<23))
+#define CMD_REPORT_HEAD			(7<<23)
+#define CMD_STORE_DWORD_IDX		((0x21<<23) | 0x1)
+#define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
+
+#define INST_PARSER_CLIENT   0x00000000
+#define INST_OP_FLUSH        0x02000000
+#define INST_FLUSH_MAP_CACHE 0x00000001
+
+
+#define BB1_START_ADDR_MASK   (~0x7)
+#define BB1_PROTECTED         (1<<0)
+#define BB1_UNPROTECTED       (0<<0)
+#define BB2_END_ADDR_MASK     (~0x7)
+
+#define I915REG_HWSTAM		0x02098
+#define I915REG_INT_IDENTITY_R	0x020a4
+#define I915REG_INT_MASK_R 	0x020a8
+#define I915REG_INT_ENABLE_R	0x020a0
+
+#define SRX_INDEX		0x3c4
+#define SRX_DATA		0x3c5
+#define SR01			1
+#define SR01_SCREEN_OFF 	(1<<5)
+
+#define PPCR			0x61204
+#define PPCR_ON			(1<<0)
+
+#define ADPA			0x61100
+#define ADPA_DPMS_MASK		(~(3<<10))
+#define ADPA_DPMS_ON		(0<<10)
+#define ADPA_DPMS_SUSPEND	(1<<10)
+#define ADPA_DPMS_STANDBY	(2<<10)
+#define ADPA_DPMS_OFF		(3<<10)
+
+#define NOPID                   0x2094
+#define LP_RING     		0x2030
+#define HP_RING     		0x2040
+#define RING_TAIL      		0x00
+#define TAIL_ADDR		0x001FFFF8
+#define RING_HEAD      		0x04
+#define HEAD_WRAP_COUNT     	0xFFE00000
+#define HEAD_WRAP_ONE       	0x00200000
+#define HEAD_ADDR           	0x001FFFFC
+#define RING_START     		0x08
+#define START_ADDR          	0x0xFFFFF000
+#define RING_LEN       		0x0C
+#define RING_NR_PAGES       	0x001FF000 
+#define RING_REPORT_MASK    	0x00000006
+#define RING_REPORT_64K     	0x00000002
+#define RING_REPORT_128K    	0x00000004
+#define RING_NO_REPORT      	0x00000000
+#define RING_VALID_MASK     	0x00000001
+#define RING_VALID          	0x00000001
+#define RING_INVALID        	0x00000000
+
+#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define SC_UPDATE_SCISSOR       (0x1<<1)
+#define SC_ENABLE_MASK          (0x1<<0)
+#define SC_ENABLE               (0x1<<0)
+
+#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
+#define SCI_YMIN_MASK      (0xffff<<16)
+#define SCI_XMIN_MASK      (0xffff<<0)
+#define SCI_YMAX_MASK      (0xffff<<16)
+#define SCI_XMAX_MASK      (0xffff<<0)
+
+#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
+#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
+#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
+#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
+#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
+#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
+
+
+#define MI_BATCH_BUFFER 	((0x30<<23)|1)
+#define MI_BATCH_BUFFER_START 	(0x31<<23)
+#define MI_BATCH_BUFFER_END 	(0xA<<23)
+#define MI_BATCH_NON_SECURE	(1)
+
+
+
+#define MI_WAIT_FOR_EVENT       ((0x3<<23))
+#define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2) 
+#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 
+
+
+#define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
+
+#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
+#define ASYNC_FLIP                (1<<22)
+
+#define CMD_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
+
+#endif
+
diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
new file mode 100644
index 00000000..f9d5d4b7
--- /dev/null
+++ b/shared-core/i915_irq.c
@@ -0,0 +1,173 @@
+/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
+ */
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ **************************************************************************/
+
+#define __NO_VERSION__
+#include "i915.h"
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+#define USER_INT_FLAG 0x2
+#define MAX_NOPID ((u32)~0)
+#define READ_BREADCRUMB(dev_priv)  (((u32*)(dev_priv->hw_status_page))[5])
+
+
+irqreturn_t DRM(irq_handler)( DRM_IRQ_ARGS )
+{
+	drm_device_t	 *dev = (drm_device_t *)arg;
+      	drm_i915_private_t *dev_priv = (drm_i915_private_t *)dev->dev_private;
+   	u16 temp;
+
+      	temp = I915_READ16(I915REG_INT_IDENTITY_R);
+	temp &= USER_INT_FLAG;
+	
+	DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
+
+   	if (temp == 0) 
+		return IRQ_NONE;
+
+	I915_WRITE16(I915REG_INT_IDENTITY_R, temp); 
+	DRM_WAKEUP( &dev_priv->irq_queue ); 
+
+	return IRQ_HANDLED;
+}
+
+
+int i915_emit_irq(drm_device_t *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	u32 ret;
+	RING_LOCALS;
+
+   	i915_kernel_lost_context(dev);
+
+	DRM_DEBUG("%s\n", __FUNCTION__);
+
+	ret = dev_priv->counter;
+
+   	BEGIN_LP_RING(2);
+      	OUT_RING( 0 );
+      	OUT_RING( GFX_OP_USER_INTERRUPT );
+      	ADVANCE_LP_RING();
+
+	return ret;
+}
+
+
+int i915_wait_irq(drm_device_t *dev, int irq_nr)
+{
+  	drm_i915_private_t *dev_priv = 
+	   (drm_i915_private_t *)dev->dev_private;
+	int ret = 0;
+
+	DRM_DEBUG("%s irq_nr=%d breadcrumb=%d\n", __FUNCTION__, irq_nr, READ_BREADCRUMB(dev_priv));
+
+ 	if (READ_BREADCRUMB(dev_priv) >= irq_nr)  
+ 		return 0; 
+
+	dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
+
+	DRM_WAIT_ON( ret, dev_priv->irq_queue, 3 * DRM_HZ,
+		     READ_BREADCRUMB(dev_priv) >= irq_nr );
+
+	if (ret == DRM_ERR(EBUSY)) {
+		DRM_ERROR("%s: EBUSY -- rec: %d emitted: %d\n", 
+			  __FUNCTION__,
+			  READ_BREADCRUMB(dev_priv),
+			  (int)dev_priv->counter);
+	}
+
+      	dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
+	return ret;
+}
+
+
+/* Needs the lock as it touches the ring.
+ */
+int i915_irq_emit( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_irq_emit_t emit;
+	int result;
+
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i915_irq_emit called without lock held\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( emit, (drm_i915_irq_emit_t *)data,
+				  sizeof(emit) );
+
+	result = i915_emit_irq( dev );
+
+	if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
+		DRM_ERROR( "copy_to_user\n" );
+		return DRM_ERR(EFAULT);
+	}
+
+	return 0;
+}
+
+
+/* Doesn't need the hardware lock.
+ */
+int i915_irq_wait( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_irq_wait_t irqwait;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_i915_irq_wait_t *)data, 
+				  sizeof(irqwait) );
+
+	return i915_wait_irq( dev, irqwait.irq_seq );
+}
+
+
+/* drm_dma.h hooks
+*/
+void DRM(driver_irq_preinstall)( drm_device_t *dev ) {
+	drm_i915_private_t *dev_priv =
+		(drm_i915_private_t *)dev->dev_private;
+
+	I915_WRITE16( I915REG_HWSTAM, 0xfffe );
+	I915_WRITE16( I915REG_INT_MASK_R, 0x0 );
+	I915_WRITE16( I915REG_INT_ENABLE_R, 0x0 );
+}
+
+void DRM(driver_irq_postinstall)( drm_device_t *dev ) {
+	drm_i915_private_t *dev_priv =
+		(drm_i915_private_t *)dev->dev_private;
+
+	I915_WRITE16( I915REG_INT_ENABLE_R, USER_INT_FLAG );
+	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
+}
+
+void DRM(driver_irq_uninstall)( drm_device_t *dev ) {
+	drm_i915_private_t *dev_priv =
+		(drm_i915_private_t *)dev->dev_private;
+	if (!dev_priv)
+		return;
+
+	I915_WRITE16( I915REG_HWSTAM, 0xffff );
+	I915_WRITE16( I915REG_INT_MASK_R, 0xffff );
+	I915_WRITE16( I915REG_INT_ENABLE_R, 0x0 );
+}
diff --git a/shared-core/i915_mem.c b/shared-core/i915_mem.c
new file mode 100644
index 00000000..58f7b888
--- /dev/null
+++ b/shared-core/i915_mem.c
@@ -0,0 +1,361 @@
+/* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*-
+ */
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ **************************************************************************/
+
+#include "i915.h"
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+/* This memory manager is integrated into the global/local lru
+ * mechanisms used by the clients.  Specifically, it operates by
+ * setting the 'in_use' fields of the global LRU to indicate whether
+ * this region is privately allocated to a client.
+ *
+ * This does require the client to actually respect that field.
+ *
+ * Currently no effort is made to allocate 'private' memory in any
+ * clever way - the LRU information isn't used to determine which
+ * block to allocate, and the ring is drained prior to allocations --
+ * in other words allocation is expensive.
+ */
+static void mark_block( drm_device_t *dev, struct mem_block *p,
+			int in_use )
+{
+   drm_i915_private_t *dev_priv = dev->dev_private;
+   drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
+   drm_tex_region_t *list;
+   unsigned   shift, nr;
+   unsigned   start;
+   unsigned   end;
+   unsigned   i;
+   int age;
+
+   shift = dev_priv->tex_lru_log_granularity;
+   nr = I915_NR_TEX_REGIONS;
+
+   start = p->start >> shift;
+   end = (p->start + p->size - 1) >> shift;
+
+   age = ++sarea_priv->texAge;
+   list = sarea_priv->texList;
+
+   /* Mark the regions with the new flag and update their age.  Move
+    * them to head of list to preserve LRU semantics.
+    */
+   for (i = start ; i <= end ; i++) {
+      list[i].in_use = in_use;
+      list[i].age = age;
+
+      /* remove_from_list(i)
+       */
+      list[(unsigned)list[i].next].prev = list[i].prev;
+      list[(unsigned)list[i].prev].next = list[i].next;
+
+      /* insert_at_head(list, i)
+       */
+      list[i].prev = nr;
+      list[i].next = list[nr].next;
+      list[(unsigned)list[nr].next].prev = i;
+      list[nr].next = i;
+   }
+}
+
+
+/* Very simple allocator for agp memory, working on a static range
+ * already mapped into each client's address space.  
+ */
+
+static struct mem_block *split_block(struct mem_block *p, int start, int size,
+				     DRMFILE filp )
+{
+	/* Maybe cut off the start of an existing block */
+	if (start > p->start) {
+		struct mem_block *newblock = DRM_MALLOC(sizeof(*newblock));
+		if (!newblock) 
+			goto out;
+		newblock->start = start;
+		newblock->size = p->size - (start - p->start);
+		newblock->filp = 0;
+		newblock->next = p->next;
+		newblock->prev = p;
+		p->next->prev = newblock;
+		p->next = newblock;
+		p->size -= newblock->size;
+		p = newblock;
+	}
+   
+	/* Maybe cut off the end of an existing block */
+	if (size < p->size) {
+		struct mem_block *newblock = DRM_MALLOC(sizeof(*newblock));
+		if (!newblock)
+			goto out;
+		newblock->start = start + size;
+		newblock->size = p->size - size;
+		newblock->filp = 0;
+		newblock->next = p->next;
+		newblock->prev = p;
+		p->next->prev = newblock;
+		p->next = newblock;
+		p->size = size;
+	}
+
+ out:
+	/* Our block is in the middle */
+	p->filp = filp;
+	return p;
+}
+
+static struct mem_block *alloc_block( struct mem_block *heap, int size, 
+				      int align2, DRMFILE filp )
+{
+	struct mem_block *p;
+	int mask = (1 << align2)-1;
+
+	for (p = heap->next ; p != heap ; p = p->next) {
+		int start = (p->start + mask) & ~mask;
+		if (p->filp == 0 && start + size <= p->start + p->size)
+			return split_block( p, start, size, filp );
+	}
+
+	return NULL;
+}
+
+static struct mem_block *find_block( struct mem_block *heap, int start )
+{
+	struct mem_block *p;
+
+	for (p = heap->next ; p != heap ; p = p->next) 
+		if (p->start == start)
+			return p;
+
+	return NULL;
+}
+
+
+static void free_block( struct mem_block *p )
+{
+	p->filp = 0;
+
+	/* Assumes a single contiguous range.  Needs a special filp in
+	 * 'heap' to stop it being subsumed.
+	 */
+	if (p->next->filp == 0) {
+		struct mem_block *q = p->next;
+		p->size += q->size;
+		p->next = q->next;
+		p->next->prev = p;
+		DRM_FREE(q, sizeof(*q));
+	}
+
+	if (p->prev->filp == 0) {
+		struct mem_block *q = p->prev;
+		q->size += p->size;
+		q->next = p->next;
+		q->next->prev = q;
+		DRM_FREE(p, sizeof(*q));
+	}
+}
+
+/* Initialize.  How to check for an uninitialized heap?
+ */
+static int init_heap(struct mem_block **heap, int start, int size)
+{
+	struct mem_block *blocks = DRM_MALLOC(sizeof(*blocks));
+
+	if (!blocks) 
+		return -ENOMEM;
+	
+	*heap = DRM_MALLOC(sizeof(**heap));
+	if (!*heap) {
+		DRM_FREE( blocks, sizeof(*blocks) );
+		return -ENOMEM;
+	}
+
+	blocks->start = start;
+	blocks->size = size;
+	blocks->filp = 0;
+	blocks->next = blocks->prev = *heap;
+
+	memset( *heap, 0, sizeof(**heap) );
+	(*heap)->filp = (DRMFILE) -1;
+	(*heap)->next = (*heap)->prev = blocks;
+	return 0;
+}
+
+
+/* Free all blocks associated with the releasing file.
+ */
+void i915_mem_release( drm_device_t *dev, 
+		       DRMFILE filp, struct mem_block *heap )
+{
+	struct mem_block *p;
+
+	if (!heap || !heap->next)
+		return;
+
+	for (p = heap->next ; p != heap ; p = p->next) {
+		if (p->filp == filp) {
+			p->filp = 0;
+			mark_block( dev, p, 0 );
+		}
+	}
+
+	/* Assumes a single contiguous range.  Needs a special filp in
+	 * 'heap' to stop it being subsumed.
+	 */
+	for (p = heap->next ; p != heap ; p = p->next) {
+		while (p->filp == 0 && p->next->filp == 0) {
+			struct mem_block *q = p->next;
+			p->size += q->size;
+			p->next = q->next;
+			p->next->prev = p;
+			DRM_FREE(q, sizeof(*q));
+		}
+	}
+}
+
+/* Shutdown.
+ */
+void i915_mem_takedown( struct mem_block **heap )
+{
+	struct mem_block *p;
+	
+	if (!*heap)
+		return;
+
+	for (p = (*heap)->next ; p != *heap ; ) {
+		struct mem_block *q = p;
+		p = p->next;
+		DRM_FREE(q, sizeof(*q));
+	}
+
+	DRM_FREE( *heap, sizeof(**heap) );
+	*heap = 0;
+}
+
+
+
+static struct mem_block **get_heap( drm_i915_private_t *dev_priv,
+				   int region )
+{
+	switch( region ) {
+	case I915_MEM_REGION_AGP:
+ 		return &dev_priv->agp_heap; 
+	default:
+		return 0;
+	}
+}
+
+
+/* IOCTL HANDLERS */
+
+int i915_mem_alloc( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_mem_alloc_t alloc;
+	struct mem_block *block, **heap;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( alloc, (drm_i915_mem_alloc_t *)data,
+				  sizeof(alloc) );
+
+	heap = get_heap( dev_priv, alloc.region );
+	if (!heap || !*heap)
+		return DRM_ERR(EFAULT);
+	
+	/* Make things easier on ourselves: all allocations at least
+	 * 4k aligned.
+	 */
+	if (alloc.alignment < 12)
+		alloc.alignment = 12;
+
+	block = alloc_block( *heap, alloc.size, alloc.alignment,
+			     filp );
+
+	if (!block) 
+		return DRM_ERR(ENOMEM);
+
+	mark_block( dev, block, 1 );
+
+	if ( DRM_COPY_TO_USER( alloc.region_offset, &block->start, 
+			       sizeof(int) ) ) {
+		DRM_ERROR( "copy_to_user\n" );
+		return DRM_ERR(EFAULT);
+	}
+	
+	return 0;
+}
+
+
+
+int i915_mem_free( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_mem_free_t memfree;
+	struct mem_block *block, **heap;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( memfree, (drm_i915_mem_free_t *)data,
+				  sizeof(memfree) );
+
+	heap = get_heap( dev_priv, memfree.region );
+	if (!heap || !*heap)
+		return DRM_ERR(EFAULT);
+	
+	block = find_block( *heap, memfree.region_offset );
+	if (!block)
+		return DRM_ERR(EFAULT);
+
+	if (block->filp != filp)
+		return DRM_ERR(EPERM);
+
+	mark_block( dev, block, 0 );
+	free_block( block );	
+	return 0;
+}
+
+int i915_mem_init_heap( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_mem_init_heap_t initheap;
+	struct mem_block **heap;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( initheap, (drm_i915_mem_init_heap_t *)data,
+				  sizeof(initheap) );
+
+	heap = get_heap( dev_priv, initheap.region );
+	if (!heap) 
+		return DRM_ERR(EFAULT);
+	
+	if (*heap) {
+		DRM_ERROR("heap already initialized?");
+		return DRM_ERR(EFAULT);
+	}
+		
+	return init_heap( heap, initheap.start, initheap.size );
+}
+
+
diff --git a/shared/drm_pciids.txt b/shared/drm_pciids.txt
index 128932bb..6eb05693 100644
--- a/shared/drm_pciids.txt
+++ b/shared/drm_pciids.txt
@@ -186,3 +186,10 @@
 
 [ffb]
 
+[i915]
+0x8086 0x3577 "Intel i830M GMCH"
+0x8086 0x2562 "Intel i845G GMCH"
+0x8086 0x3582 "Intel i852GM/i855GM GMCH"
+0x8086 0x2572 "Intel i865G GMCH"
+0x8086 0x2582 "Intel i915G"
+
diff --git a/shared/i915.h b/shared/i915.h
new file mode 100644
index 00000000..f7832e21
--- /dev/null
+++ b/shared/i915.h
@@ -0,0 +1,95 @@
+/* i915.h -- Intel I915 DRM template customization -*- linux-c -*-
+ */
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ **************************************************************************/
+
+#ifndef __I915_H__
+#define __I915_H__
+
+/* This remains constant for all DRM template files.
+ */
+#define DRM(x) i915_##x
+
+/* General customization:
+ */
+#define __HAVE_AGP		1
+#define __MUST_HAVE_AGP		1
+#define __HAVE_MTRR		1
+#define __HAVE_CTX_BITMAP	1
+
+#define DRIVER_AUTHOR		"Tungsten Graphics, Inc."
+
+#define DRIVER_NAME		"i915"
+#define DRIVER_DESC		"Intel Graphics"
+#define DRIVER_DATE		"20040405"
+
+/* Interface history:
+ *
+ * 1.1: Original.
+ */
+#define DRIVER_MAJOR		1
+#define DRIVER_MINOR		1
+#define DRIVER_PATCHLEVEL	0
+
+
+#define DRIVER_IOCTLS							    \
+	[DRM_IOCTL_NR(DRM_IOCTL_I915_INIT)]   = { i915_dma_init,    1, 1 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I915_FLUSH)]  = { i915_flush_ioctl, 1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I915_FLIP)]   = { i915_flip_bufs,   1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I915_BATCHBUFFER)] = { i915_batchbuffer, 1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I915_IRQ_EMIT)] = { i915_irq_emit,  1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I915_IRQ_WAIT)] = { i915_irq_wait,  1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I915_GETPARAM)] = { i915_getparam,  1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I915_SETPARAM)] = { i915_setparam,  1, 1 }, \
+        [DRM_IOCTL_NR(DRM_IOCTL_I915_ALLOC)]   = { i915_mem_alloc,  1, 0 }, \
+        [DRM_IOCTL_NR(DRM_IOCTL_I915_FREE)]    = { i915_mem_free,    1, 0 }, \
+        [DRM_IOCTL_NR(DRM_IOCTL_I915_INIT_HEAP)] = { i915_mem_init_heap, 1, 1 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I915_CMDBUFFER)] = { i915_cmdbuffer, 1, 0 }
+
+
+#define __HAVE_COUNTERS         4
+#define __HAVE_COUNTER6         _DRM_STAT_IRQ
+#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
+#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
+#define __HAVE_COUNTER9         _DRM_STAT_DMA
+
+/* Driver customization:
+ */
+#define DRIVER_PRETAKEDOWN(dev) do {					\
+	if ( dev->dev_private ) {					\
+		drm_i915_private_t *dev_priv = dev->dev_private;	\
+	        i915_mem_takedown( &(dev_priv->agp_heap) );             \
+ 	}								\
+	i915_cleanup( dev );					\
+} while (0)
+
+
+/* When a client dies:
+ *    - Free any alloced agp memory.
+ */
+#define DRIVER_PRERELEASE() 						\
+do {									\
+	if ( dev->dev_private ) {					\
+		drm_i915_private_t *dev_priv = dev->dev_private;	\
+                i915_mem_release( dev, filp, dev_priv->agp_heap );	\
+	}								\
+} while (0)
+
+
+
+
+/* We use our own dma mechanisms, not the drm template code.  However,
+ * the shared IRQ code is useful to us:
+ */
+#define __HAVE_DMA		0
+#define __HAVE_IRQ		1
+#define __HAVE_SHARED_IRQ	1
+
+
+#define __HAVE_PM		1
+
+#endif
diff --git a/shared/i915_dma.c b/shared/i915_dma.c
new file mode 100644
index 00000000..80f643cd
--- /dev/null
+++ b/shared/i915_dma.c
@@ -0,0 +1,756 @@
+/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
+ */
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ **************************************************************************/
+
+#define __NO_VERSION__
+#include "i915.h"
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+
+static void i915_print_status_page(drm_device_t *dev)
+{
+      	drm_i915_private_t *dev_priv = dev->dev_private;
+	u32 *temp = dev_priv->hw_status_page;
+
+	if (!temp) {
+		DRM_DEBUG("no status page\n");
+		return;
+	}
+
+   	DRM_DEBUG(  "hw_status: Interrupt Status : %x\n", temp[0]);
+   	DRM_DEBUG(  "hw_status: LpRing Head ptr : %x\n", temp[1]);
+   	DRM_DEBUG(  "hw_status: IRing Head ptr : %x\n", temp[2]);
+      	DRM_DEBUG(  "hw_status: Reserved : %x\n", temp[3]);
+   	DRM_DEBUG(  "hw_status: Driver Counter : %d\n", temp[5]);
+
+}
+
+
+
+
+/* Really want an OS-independent resettable timer.  Would like to have
+ * this loop run for (eg) 3 sec, but have the timer reset every time
+ * the head pointer changes, so that EBUSY only happens if the ring
+ * actually stalls for (eg) 3 seconds.
+ */
+int i915_wait_ring( drm_device_t *dev, int n, const char *caller )
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+   	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
+	u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+	int i;
+
+	for ( i = 0 ; i < 10000 ; i++ ) {
+		ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+	   	ring->space = ring->head - (ring->tail+8);
+		if (ring->space < 0) ring->space += ring->Size;
+		if ( ring->space >= n )
+			return 0;
+		
+		dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
+
+		if (ring->head != last_head) 
+			i = 0;
+
+		last_head = ring->head;
+	}
+
+	return DRM_ERR(EBUSY);
+}
+
+void i915_kernel_lost_context(drm_device_t *dev)
+{
+      	drm_i915_private_t *dev_priv = dev->dev_private;
+   	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
+      
+   	ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+     	ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
+     	ring->space = ring->head - (ring->tail+8);
+     	if (ring->space < 0) ring->space += ring->Size;
+
+	if (ring->head == ring->tail)
+		dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
+}
+
+
+int i915_cleanup(drm_device_t *dev)
+{
+	/* Make sure interrupts are disabled here because the uninstall ioctl
+	 * may not have been called from userspace and after dev_private
+	 * is freed, it's too late.
+	 */
+	if (dev->irq) DRM(irq_uninstall)(dev);
+
+	if (dev->dev_private) {
+	   	drm_i915_private_t *dev_priv = 
+	     		(drm_i915_private_t *) dev->dev_private;
+	   
+	   	if (dev_priv->ring.virtual_start) {
+		   	DRM_IOREMAPFREE( &dev_priv->ring.map, dev);
+		}
+
+	   	if (dev_priv->hw_status_page) {
+			pci_free_consistent(dev->pdev, PAGE_SIZE,
+				      dev_priv->hw_status_page,
+				      dev_priv->dma_status_page);
+		   	/* Need to rewrite hardware status page */
+		   	I915_WRITE(0x02080, 0x1ffff000);
+		}
+
+	   	DRM(free)(dev->dev_private, sizeof(drm_i915_private_t), 
+			 DRM_MEM_DRIVER);
+
+	   	dev->dev_private = NULL;
+	}
+
+   	return 0;
+}
+
+
+
+static int i915_initialize(drm_device_t *dev, 
+			       drm_i915_private_t *dev_priv,
+			       drm_i915_init_t *init)
+{
+   	memset(dev_priv, 0, sizeof(drm_i915_private_t));
+
+	DRM_GETSAREA();
+	if(!dev_priv->sarea) {
+		DRM_ERROR("can not find sarea!\n");
+		dev->dev_private = (void *)dev_priv;
+		i915_cleanup(dev);
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_FIND_MAP( dev_priv->mmio_map, init->mmio_offset );
+	if(!dev_priv->mmio_map) {
+		dev->dev_private = (void *)dev_priv;
+		i915_cleanup(dev);
+		DRM_ERROR("can not find mmio map!\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	dev_priv->sarea_priv = (drm_i915_sarea_t *)
+		((u8 *)dev_priv->sarea->handle +
+		 init->sarea_priv_offset);
+
+   	dev_priv->ring.Start = init->ring_start;
+   	dev_priv->ring.End = init->ring_end;
+   	dev_priv->ring.Size = init->ring_size;
+   	dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
+		
+	dev_priv->ring.map.offset = init->ring_start;
+	dev_priv->ring.map.size = init->ring_size;
+	dev_priv->ring.map.type = 0;
+	dev_priv->ring.map.flags = 0;
+	dev_priv->ring.map.mtrr = 0;
+
+	DRM_IOREMAP( &dev_priv->ring.map, dev );
+
+   	if (dev_priv->ring.map.handle == NULL) {
+		dev->dev_private = (void *) dev_priv;
+	   	i915_cleanup(dev);
+	   	DRM_ERROR("can not ioremap virtual address for"
+			  " ring buffer\n");
+	   	return DRM_ERR(ENOMEM);
+	}
+
+   	dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
+   
+	dev_priv->back_offset = init->back_offset;
+	dev_priv->front_offset = init->front_offset;
+	dev_priv->current_page = 0;
+	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
+
+	/* We are using separate values as placeholders for mechanisms for
+	 * private backbuffer/depthbuffer usage.
+	 */
+	dev_priv->use_mi_batchbuffer_start = 0;
+
+	/* Allow hardware batchbuffers unless told otherwise.
+	 */
+	dev_priv->allow_batchbuffer = 1;
+
+   	/* Program Hardware Status Page */
+   	dev_priv->hw_status_page =
+		pci_alloc_consistent( dev->pdev, PAGE_SIZE, 
+						&dev_priv->dma_status_page );
+
+   	if (!dev_priv->hw_status_page) {
+		dev->dev_private = (void *)dev_priv;
+		i915_cleanup(dev);
+		DRM_ERROR("Can not allocate hardware status page\n");
+		return DRM_ERR(ENOMEM);
+	}
+   	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
+   
+   	I915_WRITE(0x02080, dev_priv->dma_status_page);
+	DRM_DEBUG("Enabled hardware status page\n");
+   
+	dev->dev_private = (void *)dev_priv;
+
+   	return 0;
+}
+
+
+static int i915_resume(drm_device_t *dev)
+{
+	drm_i915_private_t *dev_priv = 
+		(drm_i915_private_t *) dev->dev_private;
+
+	DRM_DEBUG( "%s\n", __FUNCTION__);
+		   
+	if(!dev_priv->sarea) {
+		DRM_ERROR("can not find sarea!\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	if(!dev_priv->mmio_map) {
+		DRM_ERROR("can not find mmio map!\n");
+		return DRM_ERR(EINVAL);
+	}
+
+   	if (dev_priv->ring.map.handle == NULL) {
+	   	DRM_ERROR("can not ioremap virtual address for"
+			  " ring buffer\n");
+	   	return DRM_ERR(ENOMEM);
+	}
+
+   	/* Program Hardware Status Page */
+   	if (!dev_priv->hw_status_page) {
+		DRM_ERROR("Can not find hardware status page\n");
+		return DRM_ERR(EINVAL);
+	}
+	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
+   
+   	I915_WRITE(0x02080, dev_priv->dma_status_page);
+	DRM_DEBUG("Enabled hardware status page\n");
+
+   	return 0;
+}
+
+
+int i915_dma_init( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+   	drm_i915_private_t *dev_priv;
+   	drm_i915_init_t init;
+   	int retcode = 0;
+	
+  	DRM_COPY_FROM_USER_IOCTL( init, (drm_i915_init_t *)data, sizeof(init));
+	
+   	switch(init.func) {
+	 	case I915_INIT_DMA:
+			dev_priv = DRM(alloc)(sizeof(drm_i915_private_t), 
+					      DRM_MEM_DRIVER);
+	   		if(dev_priv == NULL) 
+				return DRM_ERR(ENOMEM);
+	   		retcode = i915_initialize(dev, dev_priv, &init);
+	   	break;
+	 	case I915_CLEANUP_DMA:
+	   		retcode = i915_cleanup(dev);
+	   	break;
+		case I915_RESUME_DMA:
+			retcode = i915_resume(dev);
+	   	break;
+	 	default:
+	   		retcode = -EINVAL;
+	   	break;
+	}
+   
+   	return retcode;
+}
+
+
+
+/* Implement basically the same security restrictions as hardware does
+ * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
+ *
+ * Most of the calculations below involve calculating the size of a
+ * particular instruction.  It's important to get the size right as
+ * that tells us where the next instruction to check is.  Any illegal
+ * instruction detected will be given a size of zero, which is a
+ * signal to abort the rest of the buffer.
+ */
+static int do_validate_cmd( int cmd )
+{
+	switch (((cmd>>29) & 0x7)) {
+	case 0x0:
+		switch ((cmd>>23) & 0x3f) {
+		case 0x0: 
+			return 1; /* MI_NOOP */
+		case 0x4: 
+			return 1; /* MI_FLUSH */
+		default: 
+			return 0; /* disallow everything else */
+		}
+		break;
+	case 0x1: 
+		return 0;	/* reserved */
+	case 0x2: 
+		return (cmd & 0xff) + 2; /* 2d commands */
+	case 0x3:
+		if (((cmd>>24) & 0x1f) <= 0x18)
+			return 1;
+
+		switch ((cmd>>24) & 0x1f) {
+		case 0x1c: 
+			return 1;
+		case 0x1d:
+			return (cmd & 0xffff) + 2;
+		case 0x1e: 
+			if (cmd & (1<<23)) 
+				return (cmd & 0xffff) + 1;
+			else
+				return 1;
+		case 0x1f:
+			if ((cmd & (1<<23)) == 0) /* inline vertices */
+				return (cmd & 0x1ffff) + 2;
+			else if (cmd & (1<<17)) /* indirect random */
+				if ((cmd & 0xffff) == 0)
+					return 0; /* unknown length, too hard */
+				else
+					return (((cmd & 0xffff) + 1) / 2) + 1;
+			else
+				return 2; /* indirect sequential */
+		default: 
+			return 0;
+		}
+	default:
+		return 0;
+	}
+
+	return 0;
+}
+
+static int validate_cmd( int cmd )
+{
+	int ret = do_validate_cmd( cmd );
+	
+/* 	printk("validate_cmd( %x ): %d\n", cmd, ret); */
+
+	return ret;
+}
+	
+	
+
+static int i915_emit_cmds( drm_device_t *dev,
+			   int *buffer,
+			   int dwords )
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+	int i;
+	RING_LOCALS;
+
+	for (i = 0 ; i < dwords ; ) {
+		int cmd, sz;
+
+		if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
+			return DRM_ERR( EINVAL );
+
+/* 		printk("%d/%d ", i, dwords); */
+
+		if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) 
+			return DRM_ERR( EINVAL );
+
+		BEGIN_LP_RING( sz );
+		OUT_RING(cmd);
+
+		while (++i, --sz) {
+			if (DRM_COPY_FROM_USER_UNCHECKED( &cmd, &buffer[i], 
+							  sizeof(cmd))) {
+				return DRM_ERR( EINVAL );
+			}
+			OUT_RING(cmd);
+		}
+		ADVANCE_LP_RING();
+	}
+
+	return 0;
+}
+
+static int i915_emit_box( drm_device_t *dev,
+			  drm_clip_rect_t *boxes,
+			  int i,
+			  int DR1,
+			  int DR4)
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+   	drm_clip_rect_t box;
+   	RING_LOCALS;
+
+	if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) {
+		return EFAULT;
+	}
+
+	if (box.y2 <= box.y1 ||
+	    box.x2 <= box.x1 ||
+	    box.y2 <= 0 ||
+	    box.x2 <= 0) {
+		DRM_ERROR("Bad box %d,%d..%d,%d\n",
+			  box.x1, box.y1, box.x2, box.y2);
+		return DRM_ERR(EINVAL);
+	}
+				
+
+	BEGIN_LP_RING(6);
+	OUT_RING( GFX_OP_DRAWRECT_INFO );
+	OUT_RING( DR1 );
+	OUT_RING( (box.x1 & 0xffff) | (box.y1<<16) );
+	OUT_RING( ((box.x2-1) & 0xffff) | ((box.y2-1)<<16) );
+	OUT_RING( DR4 );
+	OUT_RING( 0 );
+	ADVANCE_LP_RING();
+	
+	return 0;
+}
+
+
+static int i915_dispatch_cmdbuffer(drm_device_t *dev, 
+				   drm_i915_cmdbuffer_t *cmd )
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+   	int nbox = cmd->num_cliprects;
+	int i = 0, count, ret;
+   	RING_LOCALS;
+
+	if (cmd->sz & 0x3) {
+		DRM_ERROR("alignment");
+		return DRM_ERR(EINVAL);
+	}
+		
+   	i915_kernel_lost_context(dev);
+
+	count = nbox ? nbox : 1;
+
+	for (i = 0 ; i < count ; i++) {
+		if (i < nbox) {
+			ret = i915_emit_box( dev, cmd->cliprects, i, 
+					     cmd->DR1, cmd->DR4);
+			if (ret) 
+				return ret;
+		}
+
+		ret = i915_emit_cmds( dev, (int *)cmd->buf, cmd->sz / 4 );
+		if (ret) 
+			return ret;
+	}
+
+	return 0;
+}
+
+
+
+
+static int i915_dispatch_batchbuffer(drm_device_t *dev, 
+				    drm_i915_batchbuffer_t *batch )
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+   	drm_clip_rect_t box, *boxes = batch->cliprects;
+   	int nbox = batch->num_cliprects;
+	int i = 0, count;
+   	RING_LOCALS;
+
+	if ((batch->start | batch->used) & 0x7) {
+		DRM_ERROR("alignment");
+		return DRM_ERR(EINVAL);
+	}
+		
+   	i915_kernel_lost_context(dev);
+
+	count = nbox ? nbox : 1;
+
+	for (i = 0 ; i < count ; i++) {
+		if (i < nbox) {
+			int ret = i915_emit_box( dev, boxes, i,
+						 batch->DR1, batch->DR4);
+			if (ret) 
+				return ret;
+		}
+
+		if (dev_priv->use_mi_batchbuffer_start) {
+			BEGIN_LP_RING(2);
+			OUT_RING( MI_BATCH_BUFFER_START | (2<<6) );
+			OUT_RING( batch->start | MI_BATCH_NON_SECURE );
+			ADVANCE_LP_RING();
+		} 
+		else {
+			BEGIN_LP_RING(4);
+			OUT_RING( MI_BATCH_BUFFER );
+			OUT_RING( batch->start | MI_BATCH_NON_SECURE );
+			OUT_RING( batch->start + batch->used - 4 );
+			OUT_RING( 0 );
+			ADVANCE_LP_RING();
+		}
+	}
+
+	
+	dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
+
+	BEGIN_LP_RING(4);
+	OUT_RING( CMD_STORE_DWORD_IDX );
+	OUT_RING( 20 );
+	OUT_RING( dev_priv->counter );
+	OUT_RING( 0 );
+	ADVANCE_LP_RING();
+
+	return 0;
+}
+
+static int i915_dispatch_flip( drm_device_t *dev )
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+	RING_LOCALS;
+
+	DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", 
+		   __FUNCTION__, 
+		   dev_priv->current_page,
+		   dev_priv->sarea_priv->pf_current_page);
+
+  	i915_kernel_lost_context(dev);
+
+
+	BEGIN_LP_RING( 2 );
+    	OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); 
+	OUT_RING( 0 );
+	ADVANCE_LP_RING();
+
+	BEGIN_LP_RING( 6 );
+	OUT_RING( CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP );	
+	OUT_RING( 0 );
+	if ( dev_priv->current_page == 0 ) {
+		OUT_RING( dev_priv->back_offset );
+		dev_priv->current_page = 1;
+	} else {
+		OUT_RING( dev_priv->front_offset );
+		dev_priv->current_page = 0;
+	}
+	OUT_RING(0);
+	ADVANCE_LP_RING();
+
+
+	BEGIN_LP_RING( 2 );
+	OUT_RING( MI_WAIT_FOR_EVENT |
+		  MI_WAIT_FOR_PLANE_A_FLIP );
+	OUT_RING( 0 );
+	ADVANCE_LP_RING();
+	
+
+	dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
+
+	BEGIN_LP_RING(4);
+	OUT_RING( CMD_STORE_DWORD_IDX );
+	OUT_RING( 20 );
+	OUT_RING( dev_priv->counter );
+	OUT_RING( 0 );
+	ADVANCE_LP_RING();
+
+	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
+	return 0;
+}
+
+
+static int i915_quiescent(drm_device_t *dev)
+{
+   	drm_i915_private_t *dev_priv = dev->dev_private;
+
+  	i915_kernel_lost_context(dev);
+	return i915_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ );
+}
+
+
+int i915_flush_ioctl( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i915_flush_ioctl called without lock held\n");
+		return DRM_ERR(EINVAL);
+	}
+
+    	return i915_quiescent(dev); 
+}
+
+int i915_batchbuffer( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+   	drm_i915_private_t *dev_priv = (drm_i915_private_t *)dev->dev_private;
+      	u32 *hw_status = dev_priv->hw_status_page;
+   	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 
+     					dev_priv->sarea_priv; 
+	drm_i915_batchbuffer_t batch;
+	int ret;
+
+	if (!dev_priv->allow_batchbuffer) {
+		DRM_ERROR("Batchbuffer ioctl disabled\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( batch, (drm_i915_batchbuffer_t *)data, 
+				  sizeof(batch) );
+
+	DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
+		  batch.start, batch.used, batch.num_cliprects);
+
+
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i915_batchbuffer called without lock held\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects, 
+						       batch.num_cliprects *
+						       sizeof(drm_clip_rect_t)))
+		return DRM_ERR(EFAULT);
+
+	ret = i915_dispatch_batchbuffer( dev, &batch );
+
+   	sarea_priv->last_dispatch = (int) hw_status[5];   
+	return ret;
+}
+
+int i915_cmdbuffer( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+   	drm_i915_private_t *dev_priv = (drm_i915_private_t *)dev->dev_private;
+      	u32 *hw_status = dev_priv->hw_status_page;
+   	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 
+		dev_priv->sarea_priv; 
+	drm_i915_cmdbuffer_t cmdbuf;
+	int ret;
+
+	DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_i915_cmdbuffer_t *)data, 
+				  sizeof(cmdbuf) );
+
+	DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
+		  cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
+
+
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i915_cmdbuffer called without lock held\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	if (cmdbuf.num_cliprects && 
+	    DRM_VERIFYAREA_READ(cmdbuf.cliprects, 
+				cmdbuf.num_cliprects *
+				sizeof(drm_clip_rect_t))) {
+		DRM_ERROR("Fault accessing cliprects\n");
+		return DRM_ERR(EFAULT);
+	}
+
+	ret = i915_dispatch_cmdbuffer( dev, &cmdbuf );
+	if (ret) {
+		DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
+		return ret;
+	}
+
+   	sarea_priv->last_dispatch = (int) hw_status[5];   
+	return 0;
+}
+
+
+
+int i915_do_cleanup_pageflip( drm_device_t *dev )
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	DRM_DEBUG("%s\n", __FUNCTION__);
+	if (dev_priv->current_page != 0)
+		i915_dispatch_flip( dev );
+
+	return 0;
+}
+
+int i915_flip_bufs( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+
+	DRM_DEBUG("%s\n", __FUNCTION__);
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i915_flip_buf called without lock held\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	return i915_dispatch_flip( dev );
+}
+
+
+
+int i915_getparam( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_getparam_t param;
+	int value;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t *)data, 
+				 sizeof(param));
+
+	switch( param.param ) {
+	case I915_PARAM_IRQ_ACTIVE:
+		value = dev->irq ? 1 : 0;
+		break;
+	case I915_PARAM_ALLOW_BATCHBUFFER:
+		value = dev_priv->allow_batchbuffer ? 1 : 0;
+		break;
+	default:
+		DRM_ERROR("Unkown parameter %d\n", param.param);
+		return DRM_ERR(EINVAL);
+	}
+
+	if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
+		DRM_ERROR("DRM_COPY_TO_USER failed\n");
+		return DRM_ERR(EFAULT);
+	}
+	
+	return 0;
+}
+
+
+int i915_setparam( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_setparam_t param;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( param, (drm_i915_setparam_t *)data, 
+				  sizeof(param) );
+
+	switch( param.param ) {
+	case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
+		dev_priv->use_mi_batchbuffer_start = param.value;
+		break;
+	case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
+		dev_priv->tex_lru_log_granularity = param.value;
+		break;
+	case I915_SETPARAM_ALLOW_BATCHBUFFER:
+		dev_priv->allow_batchbuffer = param.value;
+		break;
+	default:
+		DRM_ERROR("unknown parameter %d\n", param.param);
+		return DRM_ERR(EINVAL);
+	}
+
+
+	return 0;
+}
diff --git a/shared/i915_drm.h b/shared/i915_drm.h
new file mode 100644
index 00000000..707e553c
--- /dev/null
+++ b/shared/i915_drm.h
@@ -0,0 +1,162 @@
+#ifndef _I915_DRM_H_
+#define _I915_DRM_H_
+
+/* Please note that modifications to all structs defined here are
+ * subject to backwards-compatibility constraints.
+ */
+
+#include "drm.h"
+
+/* Each region is a minimum of 16k, and there are at most 255 of them.
+ */
+#define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
+				 * of chars for next/prev indices */
+#define I915_LOG_MIN_TEX_REGION_SIZE 14
+
+
+typedef struct _drm_i915_init {
+	enum {
+		I915_INIT_DMA = 0x01,
+		I915_CLEANUP_DMA = 0x02,
+		I915_RESUME_DMA = 0x03
+	} func;
+	unsigned int mmio_offset;
+	int sarea_priv_offset;
+	unsigned int ring_start;
+	unsigned int ring_end;
+	unsigned int ring_size;
+	unsigned int front_offset;
+	unsigned int back_offset;
+	unsigned int depth_offset;
+	unsigned int w;
+	unsigned int h;
+	unsigned int pitch;
+	unsigned int pitch_bits;
+	unsigned int back_pitch;
+	unsigned int depth_pitch;
+	unsigned int cpp;
+        unsigned int chipset;
+} drm_i915_init_t;
+
+
+typedef struct _drm_i915_sarea {
+	drm_tex_region_t texList[I915_NR_TEX_REGIONS+1];
+        int last_upload;	/* last time texture was uploaded */
+        int last_enqueue;	/* last time a buffer was enqueued */
+	int last_dispatch;	/* age of the most recently dispatched buffer */
+	int ctxOwner;		/* last context to upload state */
+	int texAge;
+        int pf_enabled;		/* is pageflipping allowed? */
+        int pf_active;               
+        int pf_current_page;	/* which buffer is being displayed? */
+        int perf_boxes;	        /* performance boxes to be displayed */   
+} drm_i915_sarea_t;
+
+/* Flags for perf_boxes
+ */
+#define I915_BOX_RING_EMPTY    0x1 
+#define I915_BOX_FLIP          0x2 
+#define I915_BOX_WAIT          0x4 
+#define I915_BOX_TEXTURE_LOAD  0x8 
+#define I915_BOX_LOST_CONTEXT  0x10 
+
+
+/* I915 specific ioctls
+ * The device specific ioctl range is 0x40 to 0x79.
+ */
+#define DRM_IOCTL_I915_INIT		DRM_IOW( 0x40, drm_i915_init_t)
+#define DRM_IOCTL_I915_FLUSH		DRM_IO ( 0x41)
+#define DRM_IOCTL_I915_FLIP		DRM_IO ( 0x42)
+#define DRM_IOCTL_I915_BATCHBUFFER	DRM_IOW( 0x43, drm_i915_batchbuffer_t)
+#define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(0x44, drm_i915_irq_emit_t)
+#define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( 0x45, drm_i915_irq_wait_t)
+#define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(0x46, drm_i915_getparam_t)
+#define DRM_IOCTL_I915_SETPARAM         DRM_IOW( 0x47, drm_i915_setparam_t)
+#define DRM_IOCTL_I915_ALLOC            DRM_IOWR(0x48, drm_i915_mem_alloc_t)
+#define DRM_IOCTL_I915_FREE             DRM_IOW( 0x49, drm_i915_mem_free_t)
+#define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( 0x4a, drm_i915_mem_init_heap_t)
+#define DRM_IOCTL_I915_CMDBUFFER	DRM_IOW( 0x4b, drm_i915_cmdbuffer_t)
+
+
+/* Allow drivers to submit batchbuffers directly to hardware, relying
+ * on the security mechanisms provided by hardware.
+ */
+typedef struct _drm_i915_batchbuffer {
+   	int start;		/* agp offset */
+	int used;		/* nr bytes in use */
+	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
+        int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO*/
+	int num_cliprects;	/* mulitpass with multiple cliprects? */
+        drm_clip_rect_t *cliprects; /* pointer to userspace cliprects */
+} drm_i915_batchbuffer_t;
+
+/* As above, but pass a pointer to userspace buffer which can be
+ * validated by the kernel prior to sending to hardware.
+ */
+typedef struct _drm_i915_cmdbuffer {
+   	char *buf;	        /* pointer to userspace command buffer */
+	int sz;		        /* nr bytes in buf */
+	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
+        int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO*/
+	int num_cliprects;	/* mulitpass with multiple cliprects? */
+        drm_clip_rect_t *cliprects; /* pointer to userspace cliprects */
+} drm_i915_cmdbuffer_t;
+
+
+/* Userspace can request & wait on irq's:
+ */
+typedef struct drm_i915_irq_emit {
+	int *irq_seq;
+} drm_i915_irq_emit_t;
+
+typedef struct drm_i915_irq_wait {
+	int irq_seq;
+} drm_i915_irq_wait_t;
+
+
+/* Ioctl to query kernel params:
+ */
+#define I915_PARAM_IRQ_ACTIVE            1
+#define I915_PARAM_ALLOW_BATCHBUFFER     2
+
+typedef struct drm_i915_getparam {
+	int param;
+	int *value;
+} drm_i915_getparam_t;
+
+
+/* Ioctl to set kernel params:
+ */
+#define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
+#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
+#define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
+
+typedef struct drm_i915_setparam {
+	int param;
+	int value;
+} drm_i915_setparam_t;
+
+/* A memory manager for regions of shared memory:
+ */
+#define I915_MEM_REGION_AGP 1
+
+typedef struct drm_i915_mem_alloc {
+	int region;
+	int alignment;
+	int size;
+	int *region_offset;	/* offset from start of fb or agp */
+} drm_i915_mem_alloc_t;
+
+typedef struct drm_i915_mem_free {
+	int region;
+	int region_offset;
+} drm_i915_mem_free_t;
+
+typedef struct drm_i915_mem_init_heap {
+	int region;
+	int size;
+	int start;	
+} drm_i915_mem_init_heap_t;
+
+
+#endif /* _I915_DRM_H_ */
diff --git a/shared/i915_drv.h b/shared/i915_drv.h
new file mode 100644
index 00000000..ba306c65
--- /dev/null
+++ b/shared/i915_drv.h
@@ -0,0 +1,228 @@
+/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
+ */
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ **************************************************************************/
+
+#ifndef _I915_DRV_H_
+#define _I915_DRV_H_
+
+
+typedef struct _drm_i915_ring_buffer{
+	int tail_mask;
+	unsigned long Start;
+	unsigned long End;
+	unsigned long Size;
+	u8 *virtual_start;
+	int head;
+	int tail;
+	int space;
+	drm_local_map_t map;
+} drm_i915_ring_buffer_t;
+
+struct mem_block {
+	struct mem_block *next;
+	struct mem_block *prev;
+	int start;
+	int size;
+	DRMFILE filp;		/* 0: free, -1: heap, other: real files */
+};
+
+typedef struct drm_i915_private {
+	drm_local_map_t *sarea;
+	drm_local_map_t *mmio_map;
+
+	drm_i915_sarea_t *sarea_priv;
+   	drm_i915_ring_buffer_t ring;
+
+      	void * hw_status_page;
+   	unsigned long counter;
+	dma_addr_t dma_status_page;
+
+	
+	int back_offset;
+	int front_offset;
+	int current_page;
+	int page_flipping;
+	int use_mi_batchbuffer_start;
+	
+
+	wait_queue_head_t irq_queue;
+   	atomic_t irq_received;
+   	atomic_t irq_emitted;
+
+	int tex_lru_log_granularity;
+	int allow_batchbuffer;
+	struct mem_block *agp_heap;
+} drm_i915_private_t;
+
+				/* i915_dma.c */
+extern int i915_dma_init( DRM_IOCTL_ARGS );
+extern int i915_cleanup(drm_device_t *dev);
+extern int i915_flush_ioctl( DRM_IOCTL_ARGS );
+extern int i915_batchbuffer( DRM_IOCTL_ARGS );
+extern int i915_flip_bufs( DRM_IOCTL_ARGS );
+extern int i915_getparam(  DRM_IOCTL_ARGS );
+extern int i915_setparam(  DRM_IOCTL_ARGS );
+extern int i915_cmdbuffer( DRM_IOCTL_ARGS );
+extern void i915_kernel_lost_context(drm_device_t *dev);
+
+/* i915_irq.c */
+extern int i915_irq_emit(  DRM_IOCTL_ARGS );
+extern int i915_irq_wait(  DRM_IOCTL_ARGS );
+extern int i915_wait_irq(drm_device_t *dev, int irq_nr);
+extern int i915_emit_irq(drm_device_t *dev);
+
+
+/* i915_mem.c */
+extern int i915_mem_alloc( DRM_IOCTL_ARGS );
+extern int i915_mem_free( DRM_IOCTL_ARGS );
+extern int i915_mem_init_heap( DRM_IOCTL_ARGS );
+extern void i915_mem_takedown( struct mem_block **heap );
+extern void i915_mem_release( drm_device_t *dev, 
+			      DRMFILE filp, struct mem_block *heap );
+
+#define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, reg)
+#define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, reg, val)
+#define I915_READ16(reg) 	DRM_READ16(dev_priv->mmio_map, reg)
+#define I915_WRITE16(reg,val)	DRM_WRITE16(dev_priv->mmio_map, reg, val)
+
+
+
+#define I915_VERBOSE 0
+
+#define RING_LOCALS	unsigned int outring, ringmask, outcount; \
+                        volatile char *virt;
+
+#define BEGIN_LP_RING(n) do {				\
+	if (I915_VERBOSE)				\
+		DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",	\
+			  n, __FUNCTION__);		\
+	if (dev_priv->ring.space < n*4)			\
+		i915_wait_ring(dev, n*4, __FUNCTION__);		\
+	outcount = 0;					\
+	outring = dev_priv->ring.tail;			\
+	ringmask = dev_priv->ring.tail_mask;		\
+	virt = dev_priv->ring.virtual_start;		\
+} while (0)
+
+
+#define OUT_RING(n) do {					\
+	if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
+	*(volatile unsigned int *)(virt + outring) = n;		\
+        outcount++;						\
+	outring += 4;						\
+	outring &= ringmask;					\
+} while (0)
+
+#define ADVANCE_LP_RING() do {						\
+	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);	\
+	dev_priv->ring.tail = outring;					\
+	dev_priv->ring.space -= outcount * 4;				\
+	I915_WRITE(LP_RING + RING_TAIL, outring);			\
+} while(0)
+
+extern int i915_wait_ring(drm_device_t *dev, int n, const char *caller);
+
+
+#define GFX_OP_USER_INTERRUPT 		((0<<29)|(2<<23))
+#define GFX_OP_BREAKPOINT_INTERRUPT	((0<<29)|(1<<23))
+#define CMD_REPORT_HEAD			(7<<23)
+#define CMD_STORE_DWORD_IDX		((0x21<<23) | 0x1)
+#define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
+
+#define INST_PARSER_CLIENT   0x00000000
+#define INST_OP_FLUSH        0x02000000
+#define INST_FLUSH_MAP_CACHE 0x00000001
+
+
+#define BB1_START_ADDR_MASK   (~0x7)
+#define BB1_PROTECTED         (1<<0)
+#define BB1_UNPROTECTED       (0<<0)
+#define BB2_END_ADDR_MASK     (~0x7)
+
+#define I915REG_HWSTAM		0x02098
+#define I915REG_INT_IDENTITY_R	0x020a4
+#define I915REG_INT_MASK_R 	0x020a8
+#define I915REG_INT_ENABLE_R	0x020a0
+
+#define SRX_INDEX		0x3c4
+#define SRX_DATA		0x3c5
+#define SR01			1
+#define SR01_SCREEN_OFF 	(1<<5)
+
+#define PPCR			0x61204
+#define PPCR_ON			(1<<0)
+
+#define ADPA			0x61100
+#define ADPA_DPMS_MASK		(~(3<<10))
+#define ADPA_DPMS_ON		(0<<10)
+#define ADPA_DPMS_SUSPEND	(1<<10)
+#define ADPA_DPMS_STANDBY	(2<<10)
+#define ADPA_DPMS_OFF		(3<<10)
+
+#define NOPID                   0x2094
+#define LP_RING     		0x2030
+#define HP_RING     		0x2040
+#define RING_TAIL      		0x00
+#define TAIL_ADDR		0x001FFFF8
+#define RING_HEAD      		0x04
+#define HEAD_WRAP_COUNT     	0xFFE00000
+#define HEAD_WRAP_ONE       	0x00200000
+#define HEAD_ADDR           	0x001FFFFC
+#define RING_START     		0x08
+#define START_ADDR          	0x0xFFFFF000
+#define RING_LEN       		0x0C
+#define RING_NR_PAGES       	0x001FF000 
+#define RING_REPORT_MASK    	0x00000006
+#define RING_REPORT_64K     	0x00000002
+#define RING_REPORT_128K    	0x00000004
+#define RING_NO_REPORT      	0x00000000
+#define RING_VALID_MASK     	0x00000001
+#define RING_VALID          	0x00000001
+#define RING_INVALID        	0x00000000
+
+#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define SC_UPDATE_SCISSOR       (0x1<<1)
+#define SC_ENABLE_MASK          (0x1<<0)
+#define SC_ENABLE               (0x1<<0)
+
+#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
+#define SCI_YMIN_MASK      (0xffff<<16)
+#define SCI_XMIN_MASK      (0xffff<<0)
+#define SCI_YMAX_MASK      (0xffff<<16)
+#define SCI_XMAX_MASK      (0xffff<<0)
+
+#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
+#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
+#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
+#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
+#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
+#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
+
+
+#define MI_BATCH_BUFFER 	((0x30<<23)|1)
+#define MI_BATCH_BUFFER_START 	(0x31<<23)
+#define MI_BATCH_BUFFER_END 	(0xA<<23)
+#define MI_BATCH_NON_SECURE	(1)
+
+
+
+#define MI_WAIT_FOR_EVENT       ((0x3<<23))
+#define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2) 
+#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 
+
+
+#define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
+
+#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
+#define ASYNC_FLIP                (1<<22)
+
+#define CMD_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
+
+#endif
+
diff --git a/shared/i915_irq.c b/shared/i915_irq.c
new file mode 100644
index 00000000..f9d5d4b7
--- /dev/null
+++ b/shared/i915_irq.c
@@ -0,0 +1,173 @@
+/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
+ */
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ **************************************************************************/
+
+#define __NO_VERSION__
+#include "i915.h"
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+#define USER_INT_FLAG 0x2
+#define MAX_NOPID ((u32)~0)
+#define READ_BREADCRUMB(dev_priv)  (((u32*)(dev_priv->hw_status_page))[5])
+
+
+irqreturn_t DRM(irq_handler)( DRM_IRQ_ARGS )
+{
+	drm_device_t	 *dev = (drm_device_t *)arg;
+      	drm_i915_private_t *dev_priv = (drm_i915_private_t *)dev->dev_private;
+   	u16 temp;
+
+      	temp = I915_READ16(I915REG_INT_IDENTITY_R);
+	temp &= USER_INT_FLAG;
+	
+	DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
+
+   	if (temp == 0) 
+		return IRQ_NONE;
+
+	I915_WRITE16(I915REG_INT_IDENTITY_R, temp); 
+	DRM_WAKEUP( &dev_priv->irq_queue ); 
+
+	return IRQ_HANDLED;
+}
+
+
+int i915_emit_irq(drm_device_t *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	u32 ret;
+	RING_LOCALS;
+
+   	i915_kernel_lost_context(dev);
+
+	DRM_DEBUG("%s\n", __FUNCTION__);
+
+	ret = dev_priv->counter;
+
+   	BEGIN_LP_RING(2);
+      	OUT_RING( 0 );
+      	OUT_RING( GFX_OP_USER_INTERRUPT );
+      	ADVANCE_LP_RING();
+
+	return ret;
+}
+
+
+int i915_wait_irq(drm_device_t *dev, int irq_nr)
+{
+  	drm_i915_private_t *dev_priv = 
+	   (drm_i915_private_t *)dev->dev_private;
+	int ret = 0;
+
+	DRM_DEBUG("%s irq_nr=%d breadcrumb=%d\n", __FUNCTION__, irq_nr, READ_BREADCRUMB(dev_priv));
+
+ 	if (READ_BREADCRUMB(dev_priv) >= irq_nr)  
+ 		return 0; 
+
+	dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
+
+	DRM_WAIT_ON( ret, dev_priv->irq_queue, 3 * DRM_HZ,
+		     READ_BREADCRUMB(dev_priv) >= irq_nr );
+
+	if (ret == DRM_ERR(EBUSY)) {
+		DRM_ERROR("%s: EBUSY -- rec: %d emitted: %d\n", 
+			  __FUNCTION__,
+			  READ_BREADCRUMB(dev_priv),
+			  (int)dev_priv->counter);
+	}
+
+      	dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
+	return ret;
+}
+
+
+/* Needs the lock as it touches the ring.
+ */
+int i915_irq_emit( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_irq_emit_t emit;
+	int result;
+
+   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("i915_irq_emit called without lock held\n");
+		return DRM_ERR(EINVAL);
+	}
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( emit, (drm_i915_irq_emit_t *)data,
+				  sizeof(emit) );
+
+	result = i915_emit_irq( dev );
+
+	if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
+		DRM_ERROR( "copy_to_user\n" );
+		return DRM_ERR(EFAULT);
+	}
+
+	return 0;
+}
+
+
+/* Doesn't need the hardware lock.
+ */
+int i915_irq_wait( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_irq_wait_t irqwait;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_i915_irq_wait_t *)data, 
+				  sizeof(irqwait) );
+
+	return i915_wait_irq( dev, irqwait.irq_seq );
+}
+
+
+/* drm_dma.h hooks
+*/
+void DRM(driver_irq_preinstall)( drm_device_t *dev ) {
+	drm_i915_private_t *dev_priv =
+		(drm_i915_private_t *)dev->dev_private;
+
+	I915_WRITE16( I915REG_HWSTAM, 0xfffe );
+	I915_WRITE16( I915REG_INT_MASK_R, 0x0 );
+	I915_WRITE16( I915REG_INT_ENABLE_R, 0x0 );
+}
+
+void DRM(driver_irq_postinstall)( drm_device_t *dev ) {
+	drm_i915_private_t *dev_priv =
+		(drm_i915_private_t *)dev->dev_private;
+
+	I915_WRITE16( I915REG_INT_ENABLE_R, USER_INT_FLAG );
+	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
+}
+
+void DRM(driver_irq_uninstall)( drm_device_t *dev ) {
+	drm_i915_private_t *dev_priv =
+		(drm_i915_private_t *)dev->dev_private;
+	if (!dev_priv)
+		return;
+
+	I915_WRITE16( I915REG_HWSTAM, 0xffff );
+	I915_WRITE16( I915REG_INT_MASK_R, 0xffff );
+	I915_WRITE16( I915REG_INT_ENABLE_R, 0x0 );
+}
diff --git a/shared/i915_mem.c b/shared/i915_mem.c
new file mode 100644
index 00000000..58f7b888
--- /dev/null
+++ b/shared/i915_mem.c
@@ -0,0 +1,361 @@
+/* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*-
+ */
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ **************************************************************************/
+
+#include "i915.h"
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+/* This memory manager is integrated into the global/local lru
+ * mechanisms used by the clients.  Specifically, it operates by
+ * setting the 'in_use' fields of the global LRU to indicate whether
+ * this region is privately allocated to a client.
+ *
+ * This does require the client to actually respect that field.
+ *
+ * Currently no effort is made to allocate 'private' memory in any
+ * clever way - the LRU information isn't used to determine which
+ * block to allocate, and the ring is drained prior to allocations --
+ * in other words allocation is expensive.
+ */
+static void mark_block( drm_device_t *dev, struct mem_block *p,
+			int in_use )
+{
+   drm_i915_private_t *dev_priv = dev->dev_private;
+   drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
+   drm_tex_region_t *list;
+   unsigned   shift, nr;
+   unsigned   start;
+   unsigned   end;
+   unsigned   i;
+   int age;
+
+   shift = dev_priv->tex_lru_log_granularity;
+   nr = I915_NR_TEX_REGIONS;
+
+   start = p->start >> shift;
+   end = (p->start + p->size - 1) >> shift;
+
+   age = ++sarea_priv->texAge;
+   list = sarea_priv->texList;
+
+   /* Mark the regions with the new flag and update their age.  Move
+    * them to head of list to preserve LRU semantics.
+    */
+   for (i = start ; i <= end ; i++) {
+      list[i].in_use = in_use;
+      list[i].age = age;
+
+      /* remove_from_list(i)
+       */
+      list[(unsigned)list[i].next].prev = list[i].prev;
+      list[(unsigned)list[i].prev].next = list[i].next;
+
+      /* insert_at_head(list, i)
+       */
+      list[i].prev = nr;
+      list[i].next = list[nr].next;
+      list[(unsigned)list[nr].next].prev = i;
+      list[nr].next = i;
+   }
+}
+
+
+/* Very simple allocator for agp memory, working on a static range
+ * already mapped into each client's address space.  
+ */
+
+static struct mem_block *split_block(struct mem_block *p, int start, int size,
+				     DRMFILE filp )
+{
+	/* Maybe cut off the start of an existing block */
+	if (start > p->start) {
+		struct mem_block *newblock = DRM_MALLOC(sizeof(*newblock));
+		if (!newblock) 
+			goto out;
+		newblock->start = start;
+		newblock->size = p->size - (start - p->start);
+		newblock->filp = 0;
+		newblock->next = p->next;
+		newblock->prev = p;
+		p->next->prev = newblock;
+		p->next = newblock;
+		p->size -= newblock->size;
+		p = newblock;
+	}
+   
+	/* Maybe cut off the end of an existing block */
+	if (size < p->size) {
+		struct mem_block *newblock = DRM_MALLOC(sizeof(*newblock));
+		if (!newblock)
+			goto out;
+		newblock->start = start + size;
+		newblock->size = p->size - size;
+		newblock->filp = 0;
+		newblock->next = p->next;
+		newblock->prev = p;
+		p->next->prev = newblock;
+		p->next = newblock;
+		p->size = size;
+	}
+
+ out:
+	/* Our block is in the middle */
+	p->filp = filp;
+	return p;
+}
+
+static struct mem_block *alloc_block( struct mem_block *heap, int size, 
+				      int align2, DRMFILE filp )
+{
+	struct mem_block *p;
+	int mask = (1 << align2)-1;
+
+	for (p = heap->next ; p != heap ; p = p->next) {
+		int start = (p->start + mask) & ~mask;
+		if (p->filp == 0 && start + size <= p->start + p->size)
+			return split_block( p, start, size, filp );
+	}
+
+	return NULL;
+}
+
+static struct mem_block *find_block( struct mem_block *heap, int start )
+{
+	struct mem_block *p;
+
+	for (p = heap->next ; p != heap ; p = p->next) 
+		if (p->start == start)
+			return p;
+
+	return NULL;
+}
+
+
+static void free_block( struct mem_block *p )
+{
+	p->filp = 0;
+
+	/* Assumes a single contiguous range.  Needs a special filp in
+	 * 'heap' to stop it being subsumed.
+	 */
+	if (p->next->filp == 0) {
+		struct mem_block *q = p->next;
+		p->size += q->size;
+		p->next = q->next;
+		p->next->prev = p;
+		DRM_FREE(q, sizeof(*q));
+	}
+
+	if (p->prev->filp == 0) {
+		struct mem_block *q = p->prev;
+		q->size += p->size;
+		q->next = p->next;
+		q->next->prev = q;
+		DRM_FREE(p, sizeof(*q));
+	}
+}
+
+/* Initialize.  How to check for an uninitialized heap?
+ */
+static int init_heap(struct mem_block **heap, int start, int size)
+{
+	struct mem_block *blocks = DRM_MALLOC(sizeof(*blocks));
+
+	if (!blocks) 
+		return -ENOMEM;
+	
+	*heap = DRM_MALLOC(sizeof(**heap));
+	if (!*heap) {
+		DRM_FREE( blocks, sizeof(*blocks) );
+		return -ENOMEM;
+	}
+
+	blocks->start = start;
+	blocks->size = size;
+	blocks->filp = 0;
+	blocks->next = blocks->prev = *heap;
+
+	memset( *heap, 0, sizeof(**heap) );
+	(*heap)->filp = (DRMFILE) -1;
+	(*heap)->next = (*heap)->prev = blocks;
+	return 0;
+}
+
+
+/* Free all blocks associated with the releasing file.
+ */
+void i915_mem_release( drm_device_t *dev, 
+		       DRMFILE filp, struct mem_block *heap )
+{
+	struct mem_block *p;
+
+	if (!heap || !heap->next)
+		return;
+
+	for (p = heap->next ; p != heap ; p = p->next) {
+		if (p->filp == filp) {
+			p->filp = 0;
+			mark_block( dev, p, 0 );
+		}
+	}
+
+	/* Assumes a single contiguous range.  Needs a special filp in
+	 * 'heap' to stop it being subsumed.
+	 */
+	for (p = heap->next ; p != heap ; p = p->next) {
+		while (p->filp == 0 && p->next->filp == 0) {
+			struct mem_block *q = p->next;
+			p->size += q->size;
+			p->next = q->next;
+			p->next->prev = p;
+			DRM_FREE(q, sizeof(*q));
+		}
+	}
+}
+
+/* Shutdown.
+ */
+void i915_mem_takedown( struct mem_block **heap )
+{
+	struct mem_block *p;
+	
+	if (!*heap)
+		return;
+
+	for (p = (*heap)->next ; p != *heap ; ) {
+		struct mem_block *q = p;
+		p = p->next;
+		DRM_FREE(q, sizeof(*q));
+	}
+
+	DRM_FREE( *heap, sizeof(**heap) );
+	*heap = 0;
+}
+
+
+
+static struct mem_block **get_heap( drm_i915_private_t *dev_priv,
+				   int region )
+{
+	switch( region ) {
+	case I915_MEM_REGION_AGP:
+ 		return &dev_priv->agp_heap; 
+	default:
+		return 0;
+	}
+}
+
+
+/* IOCTL HANDLERS */
+
+int i915_mem_alloc( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_mem_alloc_t alloc;
+	struct mem_block *block, **heap;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( alloc, (drm_i915_mem_alloc_t *)data,
+				  sizeof(alloc) );
+
+	heap = get_heap( dev_priv, alloc.region );
+	if (!heap || !*heap)
+		return DRM_ERR(EFAULT);
+	
+	/* Make things easier on ourselves: all allocations at least
+	 * 4k aligned.
+	 */
+	if (alloc.alignment < 12)
+		alloc.alignment = 12;
+
+	block = alloc_block( *heap, alloc.size, alloc.alignment,
+			     filp );
+
+	if (!block) 
+		return DRM_ERR(ENOMEM);
+
+	mark_block( dev, block, 1 );
+
+	if ( DRM_COPY_TO_USER( alloc.region_offset, &block->start, 
+			       sizeof(int) ) ) {
+		DRM_ERROR( "copy_to_user\n" );
+		return DRM_ERR(EFAULT);
+	}
+	
+	return 0;
+}
+
+
+
+int i915_mem_free( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_mem_free_t memfree;
+	struct mem_block *block, **heap;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( memfree, (drm_i915_mem_free_t *)data,
+				  sizeof(memfree) );
+
+	heap = get_heap( dev_priv, memfree.region );
+	if (!heap || !*heap)
+		return DRM_ERR(EFAULT);
+	
+	block = find_block( *heap, memfree.region_offset );
+	if (!block)
+		return DRM_ERR(EFAULT);
+
+	if (block->filp != filp)
+		return DRM_ERR(EPERM);
+
+	mark_block( dev, block, 0 );
+	free_block( block );	
+	return 0;
+}
+
+int i915_mem_init_heap( DRM_IOCTL_ARGS )
+{
+	DRM_DEVICE;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	drm_i915_mem_init_heap_t initheap;
+	struct mem_block **heap;
+
+	if ( !dev_priv ) {
+		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+		return DRM_ERR(EINVAL);
+	}
+
+	DRM_COPY_FROM_USER_IOCTL( initheap, (drm_i915_mem_init_heap_t *)data,
+				  sizeof(initheap) );
+
+	heap = get_heap( dev_priv, initheap.region );
+	if (!heap) 
+		return DRM_ERR(EFAULT);
+	
+	if (*heap) {
+		DRM_ERROR("heap already initialized?");
+		return DRM_ERR(EFAULT);
+	}
+		
+	return init_heap( heap, initheap.start, initheap.size );
+}
+
+