diff options
author | Keith Whitwell <keith@tungstengraphics.com> | 2003-04-22 09:49:14 +0000 |
---|---|---|
committer | Keith Whitwell <keith@tungstengraphics.com> | 2003-04-22 09:49:14 +0000 |
commit | 13211ad82c184e3daf68c06203412d3f1c949291 (patch) | |
tree | ef0df20b2b74802f15d6549e679138a9dc467100 | |
parent | fc4fb6b51b50e37ff697e872b297b6460c3617af (diff) |
add more get_param queries for embedded project
-rw-r--r-- | shared-core/radeon_cp.c | 7 | ||||
-rw-r--r-- | shared-core/radeon_drm.h | 4 | ||||
-rw-r--r-- | shared-core/radeon_drv.h | 7 | ||||
-rw-r--r-- | shared-core/radeon_state.c | 13 | ||||
-rw-r--r-- | shared/radeon.h | 1 | ||||
-rw-r--r-- | shared/radeon_cp.c | 7 | ||||
-rw-r--r-- | shared/radeon_drm.h | 4 | ||||
-rw-r--r-- | shared/radeon_drv.h | 7 | ||||
-rw-r--r-- | shared/radeon_state.c | 13 |
9 files changed, 63 insertions, 0 deletions
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index ee4beb1a..460c0691 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -1097,6 +1097,13 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) RADEON_ROUND_PREC_8TH_PIX); DRM_GETSAREA(); + + dev_priv->fb_offset = init->fb_offset; + dev_priv->mmio_offset = init->mmio_offset; + dev_priv->ring_offset = init->ring_offset; + dev_priv->ring_rptr_offset = init->ring_rptr_offset; + dev_priv->buffers_offset = init->buffers_offset; + dev_priv->agp_textures_offset = init->agp_textures_offset; if(!dev_priv->sarea) { DRM_ERROR("could not find sarea!\n"); diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h index 3ab57309..27eeb003 100644 --- a/shared-core/radeon_drm.h +++ b/shared-core/radeon_drm.h @@ -532,6 +532,10 @@ typedef struct drm_radeon_indirect { #define RADEON_PARAM_LAST_CLEAR 4 #define RADEON_PARAM_IRQ_NR 5 #define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */ +#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ +#define RADEON_PARAM_STATUS_HANDLE 8 +#define RADEON_PARAM_SAREA_HANDLE 9 +#define RADEON_PARAM_AGP_TEX_HANDLE 10 typedef struct drm_radeon_getparam { int param; diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 7faffa7a..198ac77a 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -126,6 +126,13 @@ typedef struct drm_radeon_private { u32 depth_pitch_offset; drm_radeon_depth_clear_t depth_clear; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; + unsigned long agp_textures_offset; drm_local_map_t *sarea; drm_local_map_t *fb; diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index 86cbead5..8e9485a7 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -2191,6 +2191,19 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS ) case RADEON_PARAM_AGP_BASE: value = dev_priv->agp_vm_start; break; + case RADEON_PARAM_REGISTER_HANDLE: + value = dev_priv->mmio_offset; + break; + case RADEON_PARAM_STATUS_HANDLE: + value = dev_priv->ring_rptr_offset; + break; + case RADEON_PARAM_SAREA_HANDLE: + /* The lock is the first dword in the sarea. */ + value = (int)dev->lock.hw_lock; + break; + case RADEON_PARAM_AGP_TEX_HANDLE: + value = dev_priv->agp_textures_offset; + break; default: return DRM_ERR(EINVAL); } diff --git a/shared/radeon.h b/shared/radeon.h index d465773e..7e75e69d 100644 --- a/shared/radeon.h +++ b/shared/radeon.h @@ -78,6 +78,7 @@ * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) + * Add 'GET' queries for starting additional clients on different VT's. */ #define DRIVER_IOCTLS \ [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \ diff --git a/shared/radeon_cp.c b/shared/radeon_cp.c index ee4beb1a..460c0691 100644 --- a/shared/radeon_cp.c +++ b/shared/radeon_cp.c @@ -1097,6 +1097,13 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) RADEON_ROUND_PREC_8TH_PIX); DRM_GETSAREA(); + + dev_priv->fb_offset = init->fb_offset; + dev_priv->mmio_offset = init->mmio_offset; + dev_priv->ring_offset = init->ring_offset; + dev_priv->ring_rptr_offset = init->ring_rptr_offset; + dev_priv->buffers_offset = init->buffers_offset; + dev_priv->agp_textures_offset = init->agp_textures_offset; if(!dev_priv->sarea) { DRM_ERROR("could not find sarea!\n"); diff --git a/shared/radeon_drm.h b/shared/radeon_drm.h index 3ab57309..27eeb003 100644 --- a/shared/radeon_drm.h +++ b/shared/radeon_drm.h @@ -532,6 +532,10 @@ typedef struct drm_radeon_indirect { #define RADEON_PARAM_LAST_CLEAR 4 #define RADEON_PARAM_IRQ_NR 5 #define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */ +#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ +#define RADEON_PARAM_STATUS_HANDLE 8 +#define RADEON_PARAM_SAREA_HANDLE 9 +#define RADEON_PARAM_AGP_TEX_HANDLE 10 typedef struct drm_radeon_getparam { int param; diff --git a/shared/radeon_drv.h b/shared/radeon_drv.h index 7faffa7a..198ac77a 100644 --- a/shared/radeon_drv.h +++ b/shared/radeon_drv.h @@ -126,6 +126,13 @@ typedef struct drm_radeon_private { u32 depth_pitch_offset; drm_radeon_depth_clear_t depth_clear; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; + unsigned long agp_textures_offset; drm_local_map_t *sarea; drm_local_map_t *fb; diff --git a/shared/radeon_state.c b/shared/radeon_state.c index 86cbead5..8e9485a7 100644 --- a/shared/radeon_state.c +++ b/shared/radeon_state.c @@ -2191,6 +2191,19 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS ) case RADEON_PARAM_AGP_BASE: value = dev_priv->agp_vm_start; break; + case RADEON_PARAM_REGISTER_HANDLE: + value = dev_priv->mmio_offset; + break; + case RADEON_PARAM_STATUS_HANDLE: + value = dev_priv->ring_rptr_offset; + break; + case RADEON_PARAM_SAREA_HANDLE: + /* The lock is the first dword in the sarea. */ + value = (int)dev->lock.hw_lock; + break; + case RADEON_PARAM_AGP_TEX_HANDLE: + value = dev_priv->agp_textures_offset; + break; default: return DRM_ERR(EINVAL); } |