Lindent of core build. Drivers checked for no binary diffs. A few files

    weren't Lindent's because their comments didn't convert very well. A
    bunch of other minor clean up with no code implact included.

46 files changed, 14958 insertions, 15125 deletions

diff --git a/shared-core/drm.h b/shared-core/drm.h
index f9469129..0d907629 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -1,7 +1,7 @@
 /**
- * \file drm.h 
+ * \file drm.h
  * Header for the Direct Rendering Manager
- * 
+ *
  * \author Rickard E. (Rik) Faith <faith@valinux.com>
  *
  * \par Acknowledgments:
@@ -39,7 +39,7 @@
  * The Direct Rendering Manager (DRM) is a device-independent kernel-level
  * device driver that provides support for the XFree86 Direct Rendering
  * Infrastructure (DRI).
- * 
+ *
  * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
  * ways:
  *     -# The DRM provides synchronized access to the graphics hardware via
@@ -52,8 +52,8 @@
  *        switch.
  *     -# The DRM is extensible via the use of small device-specific modules
  *        that rely extensively on the API exported by the DRM module.
- * 
- */ 
+ *
+ */
 
 #ifndef _DRM_H_
 #define _DRM_H_
@@ -79,7 +79,7 @@
 #define ioctl(a,b,c)		xf86ioctl(a,b,c)
 #else
 #include <sys/ioccom.h>
-#endif /* __FreeBSD__ && xf86ioctl */
+#endif				/* __FreeBSD__ && xf86ioctl */
 #define DRM_IOCTL_NR(n)		((n) & 0xff)
 #define DRM_IOC_VOID		IOC_VOID
 #define DRM_IOC_READ		IOC_OUT
@@ -125,16 +125,14 @@
 #define _DRM_LOCK_IS_CONT(lock)	   ((lock) & _DRM_LOCK_CONT)
 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
 
-
-typedef unsigned long drm_handle_t;     /**< To mapped regions */
-typedef unsigned int  drm_context_t;    /**< GLXContext handle */
-typedef unsigned int  drm_drawable_t;
-typedef unsigned int  drm_magic_t;      /**< Magic for authentication */
-
+typedef unsigned long drm_handle_t;	/**< To mapped regions */
+typedef unsigned int drm_context_t;	/**< GLXContext handle */
+typedef unsigned int drm_drawable_t;
+typedef unsigned int drm_magic_t;	/**< Magic for authentication */
 
 /**
  * Cliprect.
- * 
+ *
  * \warning If you change this structure, make sure you change
  * XF86DRIClipRectRec in the server as well
  *
@@ -142,22 +140,21 @@ typedef unsigned int  drm_magic_t;      /**< Magic for authentication */
  * backwards-compatibility reasons.
  */
 typedef struct drm_clip_rect {
-	unsigned short	x1;
-	unsigned short	y1;
-	unsigned short	x2;
-	unsigned short	y2;
+	unsigned short x1;
+	unsigned short y1;
+	unsigned short x2;
+	unsigned short y2;
 } drm_clip_rect_t;
 
-
 /**
  * Texture region,
  */
 typedef struct drm_tex_region {
-	unsigned char	next;
-	unsigned char	prev;
-	unsigned char	in_use;
-	unsigned char	padding;
-	unsigned int	age;
+	unsigned char next;
+	unsigned char prev;
+	unsigned char in_use;
+	unsigned char padding;
+	unsigned int age;
 } drm_tex_region_t;
 
 /**
@@ -169,14 +166,13 @@ typedef struct drm_tex_region {
  */
 typedef struct drm_hw_lock {
 	__volatile__ unsigned int lock;		/**< lock variable */
-	char			  padding[60];	/**< Pad to cache line */
+	char padding[60];			/**< Pad to cache line */
 } drm_hw_lock_t;
 
-
 /* This is beyond ugly, and only works on GCC.  However, it allows me to use
  * drm.h in places (i.e., in the X-server) where I can't use size_t.  The real
  * fix is to use uint32_t instead of size_t, but that fix will break existing
- * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems.  That *will* 
+ * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems.  That *will*
  * eventually happen, though.  I chose 'unsigned long' to be the fallback type
  * because that works on all the platforms I know about.  Hopefully, the
  * real fix will happen before that bites us.
@@ -191,22 +187,21 @@ typedef struct drm_hw_lock {
 
 /**
  * DRM_IOCTL_VERSION ioctl argument type.
- * 
+ *
  * \sa drmGetVersion().
  */
 typedef struct drm_version {
-	int    version_major;	  /**< Major version */
-	int    version_minor;	  /**< Minor version */
-	int    version_patchlevel;/**< Patch level */
+	int version_major;	  /**< Major version */
+	int version_minor;	  /**< Minor version */
+	int version_patchlevel;	  /**< Patch level */
 	DRM_SIZE_T name_len;	  /**< Length of name buffer */
-	char   __user *name;		  /**< Name of driver */
+	char __user *name;		  /**< Name of driver */
 	DRM_SIZE_T date_len;	  /**< Length of date buffer */
-	char   __user *date;		  /**< User-space buffer to hold date */
+	char __user *date;		  /**< User-space buffer to hold date */
 	DRM_SIZE_T desc_len;	  /**< Length of desc buffer */
-	char   __user *desc;		  /**< User-space buffer to hold desc */
+	char __user *desc;		  /**< User-space buffer to hold desc */
 } drm_version_t;
 
-
 /**
  * DRM_IOCTL_GET_UNIQUE ioctl argument type.
  *
@@ -214,22 +209,20 @@ typedef struct drm_version {
  */
 typedef struct drm_unique {
 	DRM_SIZE_T unique_len;	  /**< Length of unique */
-	char   __user *unique;		  /**< Unique name for driver instantiation */
+	char __user *unique;		  /**< Unique name for driver instantiation */
 } drm_unique_t;
 
 #undef DRM_SIZE_T
 
 typedef struct drm_list {
-	int		 count;	  /**< Length of user-space structures */
-	drm_version_t	 __user *version;
+	int count;		  /**< Length of user-space structures */
+	drm_version_t __user *version;
 } drm_list_t;
 
-
 typedef struct drm_block {
-	int		 unused;
+	int unused;
 } drm_block_t;
 
-
 /**
  * DRM_IOCTL_CONTROL ioctl argument type.
  *
@@ -241,43 +234,39 @@ typedef struct drm_control {
 		DRM_RM_COMMAND,
 		DRM_INST_HANDLER,
 		DRM_UNINST_HANDLER
-	}		 func;
-	int		 irq;
+	} func;
+	int irq;
 } drm_control_t;
 
-
 /**
  * Type of memory to map.
  */
 typedef enum drm_map_type {
-	_DRM_FRAME_BUFFER   = 0,  /**< WC (no caching), no core dump */
-	_DRM_REGISTERS	    = 1,  /**< no caching, no core dump */
-	_DRM_SHM	    = 2,  /**< shared, cached */
-	_DRM_AGP            = 3,  /**< AGP/GART */
+	_DRM_FRAME_BUFFER = 0,	  /**< WC (no caching), no core dump */
+	_DRM_REGISTERS = 1,	  /**< no caching, no core dump */
+	_DRM_SHM = 2,		  /**< shared, cached */
+	_DRM_AGP = 3,		  /**< AGP/GART */
 	_DRM_SCATTER_GATHER = 4	  /**< Scatter/gather memory for PCI DMA */
 } drm_map_type_t;
 
-
 /**
  * Memory mapping flags.
  */
 typedef enum drm_map_flags {
-	_DRM_RESTRICTED	     = 0x01, /**< Cannot be mapped to user-virtual */
-	_DRM_READ_ONLY	     = 0x02,
-	_DRM_LOCKED	     = 0x04, /**< shared, cached, locked */
-	_DRM_KERNEL	     = 0x08, /**< kernel requires access */
+	_DRM_RESTRICTED = 0x01,	     /**< Cannot be mapped to user-virtual */
+	_DRM_READ_ONLY = 0x02,
+	_DRM_LOCKED = 0x04,	     /**< shared, cached, locked */
+	_DRM_KERNEL = 0x08,	     /**< kernel requires access */
 	_DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
-	_DRM_CONTAINS_LOCK   = 0x20, /**< SHM page that contains lock */
-	_DRM_REMOVABLE	     = 0x40  /**< Removable mapping */
+	_DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
+	_DRM_REMOVABLE = 0x40	     /**< Removable mapping */
 } drm_map_flags_t;
 
-
 typedef struct drm_ctx_priv_map {
-	unsigned int	ctx_id;  /**< Context requesting private mapping */
-	void		*handle; /**< Handle of map */
+	unsigned int ctx_id;	 /**< Context requesting private mapping */
+	void *handle;		 /**< Handle of map */
 } drm_ctx_priv_map_t;
 
-
 /**
  * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
  * argument type.
@@ -285,30 +274,28 @@ typedef struct drm_ctx_priv_map {
  * \sa drmAddMap().
  */
 typedef struct drm_map {
-	unsigned long	offset;	 /**< Requested physical address (0 for SAREA)*/
-	unsigned long	size;	 /**< Requested physical size (bytes) */
-	drm_map_type_t	type;	 /**< Type of memory to map */
+	unsigned long offset;	 /**< Requested physical address (0 for SAREA)*/
+	unsigned long size;	 /**< Requested physical size (bytes) */
+	drm_map_type_t type;	 /**< Type of memory to map */
 	drm_map_flags_t flags;	 /**< Flags */
-	void		*handle; /**< User-space: "Handle" to pass to mmap() */
+	void *handle;		 /**< User-space: "Handle" to pass to mmap() */
 				 /**< Kernel-space: kernel-virtual address */
-	int		mtrr;	 /**< MTRR slot used */
-				 /*   Private data */
+	int mtrr;		 /**< MTRR slot used */
+	/*   Private data */
 } drm_map_t;
 
-
 /**
  * DRM_IOCTL_GET_CLIENT ioctl argument type.
  */
 typedef struct drm_client {
-	int		idx;	/**< Which client desired? */
-	int		auth;	/**< Is client authenticated? */
-	unsigned long	pid;	/**< Process ID */
-	unsigned long	uid;	/**< User ID */
-	unsigned long	magic;	/**< Magic */
-	unsigned long	iocs;	/**< Ioctl count */
+	int idx;		/**< Which client desired? */
+	int auth;		/**< Is client authenticated? */
+	unsigned long pid;	/**< Process ID */
+	unsigned long uid;	/**< User ID */
+	unsigned long magic;	/**< Magic */
+	unsigned long iocs;	/**< Ioctl count */
 } drm_client_t;
 
-
 typedef enum {
 	_DRM_STAT_LOCK,
 	_DRM_STAT_OPENS,
@@ -326,63 +313,58 @@ typedef enum {
 	_DRM_STAT_DMA,		/**< DMA */
 	_DRM_STAT_SPECIAL,	/**< Special DMA (e.g., priority or polled) */
 	_DRM_STAT_MISSED	/**< Missed DMA opportunity */
-
-				/* Add to the *END* of the list */
+	    /* Add to the *END* of the list */
 } drm_stat_type_t;
 
-
 /**
  * DRM_IOCTL_GET_STATS ioctl argument type.
  */
 typedef struct drm_stats {
 	unsigned long count;
 	struct {
-		unsigned long   value;
+		unsigned long value;
 		drm_stat_type_t type;
 	} data[15];
 } drm_stats_t;
 
-
 /**
  * Hardware locking flags.
  */
 typedef enum drm_lock_flags {
-	_DRM_LOCK_READY	     = 0x01, /**< Wait until hardware is ready for DMA */
-	_DRM_LOCK_QUIESCENT  = 0x02, /**< Wait until hardware quiescent */
-	_DRM_LOCK_FLUSH	     = 0x04, /**< Flush this context's DMA queue first */
-	_DRM_LOCK_FLUSH_ALL  = 0x08, /**< Flush all DMA queues first */
-				/* These *HALT* flags aren't supported yet
-				   -- they will be used to support the
-				   full-screen DGA-like mode. */
+	_DRM_LOCK_READY = 0x01,	     /**< Wait until hardware is ready for DMA */
+	_DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
+	_DRM_LOCK_FLUSH = 0x04,	     /**< Flush this context's DMA queue first */
+	_DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
+	/* These *HALT* flags aren't supported yet
+	   -- they will be used to support the
+	   full-screen DGA-like mode. */
 	_DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
 	_DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
 } drm_lock_flags_t;
 
-
 /**
  * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
- * 
+ *
  * \sa drmGetLock() and drmUnlock().
  */
 typedef struct drm_lock {
-	int		 context;
+	int context;
 	drm_lock_flags_t flags;
 } drm_lock_t;
 
-
 /**
  * DMA flags
  *
- * \warning 
+ * \warning
  * These values \e must match xf86drm.h.
  *
  * \sa drm_dma.
  */
-typedef enum drm_dma_flags {	      
-				      /* Flags for DMA buffer dispatch */
-	_DRM_DMA_BLOCK	      = 0x01, /**<
+typedef enum drm_dma_flags {
+	/* Flags for DMA buffer dispatch */
+	_DRM_DMA_BLOCK = 0x01,	      /**<
 				       * Block until buffer dispatched.
-				       * 
+				       *
 				       * \note The buffer may not yet have
 				       * been processed by the hardware --
 				       * getting a hardware lock with the
@@ -391,78 +373,72 @@ typedef enum drm_dma_flags {
 				       * processed.
 				       */
 	_DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
-	_DRM_DMA_PRIORITY     = 0x04, /**< High priority dispatch */
+	_DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */
 
-				      /* Flags for DMA buffer request */
-	_DRM_DMA_WAIT	      = 0x10, /**< Wait for free buffers */
-	_DRM_DMA_SMALLER_OK   = 0x20, /**< Smaller-than-requested buffers OK */
-	_DRM_DMA_LARGER_OK    = 0x40  /**< Larger-than-requested buffers OK */
+	/* Flags for DMA buffer request */
+	_DRM_DMA_WAIT = 0x10,	      /**< Wait for free buffers */
+	_DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
+	_DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
 } drm_dma_flags_t;
 
-
 /**
  * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
  *
  * \sa drmAddBufs().
  */
 typedef struct drm_buf_desc {
-	int	      count;	 /**< Number of buffers of this size */
-	int	      size;	 /**< Size in bytes */
-	int	      low_mark;	 /**< Low water mark */
-	int	      high_mark; /**< High water mark */
+	int count;		 /**< Number of buffers of this size */
+	int size;		 /**< Size in bytes */
+	int low_mark;		 /**< Low water mark */
+	int high_mark;		 /**< High water mark */
 	enum {
-		_DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
-		_DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
-		_DRM_SG_BUFFER  = 0x04  /**< Scatter/gather memory buffer */
-	}	      flags;
-	unsigned long agp_start; /**< 
+		_DRM_PAGE_ALIGN = 0x01,	/**< Align on page boundaries for DMA */
+		_DRM_AGP_BUFFER = 0x02,	/**< Buffer is in AGP space */
+		_DRM_SG_BUFFER = 0x04	/**< Scatter/gather memory buffer */
+	} flags;
+	unsigned long agp_start; /**<
 				  * Start address of where the AGP buffers are
 				  * in the AGP aperture
 				  */
 } drm_buf_desc_t;
 
-
 /**
  * DRM_IOCTL_INFO_BUFS ioctl argument type.
  */
 typedef struct drm_buf_info {
-	int	       count;	  /**< Number of buffers described in list */
+	int count;		  /**< Number of buffers described in list */
 	drm_buf_desc_t __user *list;	  /**< List of buffer descriptions */
 } drm_buf_info_t;
 
-
 /**
  * DRM_IOCTL_FREE_BUFS ioctl argument type.
  */
 typedef struct drm_buf_free {
-	int	       count;
-	int	       __user *list;
+	int count;
+	int __user *list;
 } drm_buf_free_t;
 
-
 /**
  * Buffer information
  *
  * \sa drm_buf_map.
  */
 typedef struct drm_buf_pub {
-	int		  idx;	       /**< Index into the master buffer list */
-	int		  total;       /**< Buffer size */
-	int		  used;	       /**< Amount of buffer in use (for DMA) */
-	void	  __user *address;     /**< Address of buffer */
+	int idx;		       /**< Index into the master buffer list */
+	int total;		       /**< Buffer size */
+	int used;		       /**< Amount of buffer in use (for DMA) */
+	void __user *address;	       /**< Address of buffer */
 } drm_buf_pub_t;
 
-
 /**
  * DRM_IOCTL_MAP_BUFS ioctl argument type.
  */
 typedef struct drm_buf_map {
-	int	      count;	/**< Length of the buffer list */
-	void	      __user *virtual;	/**< Mmap'd area in user-virtual */
+	int count;		/**< Length of the buffer list */
+	void __user *virtual;		/**< Mmap'd area in user-virtual */
 	drm_buf_pub_t __user *list;	/**< Buffer information */
 } drm_buf_map_t;
 
-
 /**
  * DRM_IOCTL_DMA ioctl argument type.
  *
@@ -471,61 +447,55 @@ typedef struct drm_buf_map {
  * \sa drmDMA().
  */
 typedef struct drm_dma {
-	int		context;	  /**< Context handle */
-	int		send_count;	  /**< Number of buffers to send */
-	int	__user *send_indices;	  /**< List of handles to buffers */
-	int	__user *send_sizes;	  /**< Lengths of data to send */
+	int context;			  /**< Context handle */
+	int send_count;			  /**< Number of buffers to send */
+	int __user *send_indices;	  /**< List of handles to buffers */
+	int __user *send_sizes;		  /**< Lengths of data to send */
 	drm_dma_flags_t flags;		  /**< Flags */
-	int		request_count;	  /**< Number of buffers requested */
-	int		request_size;	  /**< Desired size for buffers */
-	int	__user *request_indices; /**< Buffer information */
-	int	__user *request_sizes;
-	int		granted_count;	  /**< Number of buffers granted */
+	int request_count;		  /**< Number of buffers requested */
+	int request_size;		  /**< Desired size for buffers */
+	int __user *request_indices;	 /**< Buffer information */
+	int __user *request_sizes;
+	int granted_count;		  /**< Number of buffers granted */
 } drm_dma_t;
 
-
 typedef enum {
 	_DRM_CONTEXT_PRESERVED = 0x01,
-	_DRM_CONTEXT_2DONLY    = 0x02
+	_DRM_CONTEXT_2DONLY = 0x02
 } drm_ctx_flags_t;
 
-
 /**
  * DRM_IOCTL_ADD_CTX ioctl argument type.
  *
  * \sa drmCreateContext() and drmDestroyContext().
  */
 typedef struct drm_ctx {
-	drm_context_t	handle;
+	drm_context_t handle;
 	drm_ctx_flags_t flags;
 } drm_ctx_t;
 
-
 /**
  * DRM_IOCTL_RES_CTX ioctl argument type.
  */
 typedef struct drm_ctx_res {
-	int		count;
-	drm_ctx_t	__user *contexts;
+	int count;
+	drm_ctx_t __user *contexts;
 } drm_ctx_res_t;
 
-
 /**
  * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
  */
 typedef struct drm_draw {
-	drm_drawable_t	handle;
+	drm_drawable_t handle;
 } drm_draw_t;
 
-
 /**
  * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
  */
 typedef struct drm_auth {
-	drm_magic_t	magic;
+	drm_magic_t magic;
 } drm_auth_t;
 
-
 /**
  * DRM_IOCTL_IRQ_BUSID ioctl argument type.
  *
@@ -538,24 +508,20 @@ typedef struct drm_irq_busid {
 	int funcnum;	/**< function number */
 } drm_irq_busid_t;
 
-
 typedef enum {
-    _DRM_VBLANK_ABSOLUTE = 0x0,		/**< Wait for specific vblank sequence number */
-    _DRM_VBLANK_RELATIVE = 0x1,		/**< Wait for given number of vblanks */
-    _DRM_VBLANK_SIGNAL   = 0x40000000	/**< Send signal instead of blocking */
+	_DRM_VBLANK_ABSOLUTE = 0x0,	/**< Wait for specific vblank sequence number */
+	_DRM_VBLANK_RELATIVE = 0x1,	/**< Wait for given number of vblanks */
+	_DRM_VBLANK_SIGNAL = 0x40000000	/**< Send signal instead of blocking */
 } drm_vblank_seq_type_t;
 
-
 #define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL
 
-
 struct drm_wait_vblank_request {
 	drm_vblank_seq_type_t type;
 	unsigned int sequence;
 	unsigned long signal;
 };
 
-
 struct drm_wait_vblank_reply {
 	drm_vblank_seq_type_t type;
 	unsigned int sequence;
@@ -563,7 +529,6 @@ struct drm_wait_vblank_reply {
 	long tval_usec;
 };
 
-
 /**
  * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
  *
@@ -574,7 +539,6 @@ typedef union drm_wait_vblank {
 	struct drm_wait_vblank_reply reply;
 } drm_wait_vblank_t;
 
-
 /**
  * DRM_IOCTL_AGP_ENABLE ioctl argument type.
  *
@@ -584,7 +548,6 @@ typedef struct drm_agp_mode {
 	unsigned long mode;	/**< AGP mode */
 } drm_agp_mode_t;
 
-
 /**
  * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
  *
@@ -593,22 +556,20 @@ typedef struct drm_agp_mode {
 typedef struct drm_agp_buffer {
 	unsigned long size;	/**< In bytes -- will round to page boundary */
 	unsigned long handle;	/**< Used for binding / unbinding */
-	unsigned long type;     /**< Type of memory to allocate */
-        unsigned long physical; /**< Physical used by i810 */
+	unsigned long type;	/**< Type of memory to allocate */
+	unsigned long physical;	/**< Physical used by i810 */
 } drm_agp_buffer_t;
 
-
 /**
  * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
  *
  * \sa drmAgpBind() and drmAgpUnbind().
  */
 typedef struct drm_agp_binding {
-	unsigned long handle;   /**< From drm_agp_buffer */
+	unsigned long handle;	/**< From drm_agp_buffer */
 	unsigned long offset;	/**< In bytes -- will round to page boundary */
 } drm_agp_binding_t;
 
-
 /**
  * DRM_IOCTL_AGP_INFO ioctl argument type.
  *
@@ -617,22 +578,21 @@ typedef struct drm_agp_binding {
  * drmAgpVendorId() and drmAgpDeviceId().
  */
 typedef struct drm_agp_info {
-	int            agp_version_major;
-	int            agp_version_minor;
-	unsigned long  mode;
-	unsigned long  aperture_base;  /**< physical address */
-	unsigned long  aperture_size;  /**< bytes */
-	unsigned long  memory_allowed; /**< bytes */
-	unsigned long  memory_used;
+	int agp_version_major;
+	int agp_version_minor;
+	unsigned long mode;
+	unsigned long aperture_base;   /**< physical address */
+	unsigned long aperture_size;   /**< bytes */
+	unsigned long memory_allowed;  /**< bytes */
+	unsigned long memory_used;
 
 	/** \name PCI information */
-	/*@{*/
+	/*@{ */
 	unsigned short id_vendor;
 	unsigned short id_device;
-	/*@}*/
+	/*@} */
 } drm_agp_info_t;
 
-
 /**
  * DRM_IOCTL_SG_ALLOC ioctl argument type.
  */
@@ -651,7 +611,6 @@ typedef struct drm_set_version {
 	int drm_dd_minor;
 } drm_set_version_t;
 
-
 /**
  * \name Ioctls Definitions
  */
@@ -719,7 +678,6 @@ typedef struct drm_set_version {
 
 /*@}*/
 
-
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x79.
diff --git a/shared-core/drm_sarea.h b/shared-core/drm_sarea.h
index 40f7d5f1..0d5baf69 100644
--- a/shared-core/drm_sarea.h
+++ b/shared-core/drm_sarea.h
@@ -1,5 +1,5 @@
 /**
- * \file drm_sarea.h 
+ * \file drm_sarea.h
  * \brief SAREA definitions
  *
  * \author Michel D�zer <michel@daenzer.net>
@@ -38,7 +38,7 @@
 #if defined(__alpha__)
 #define SAREA_MAX                       0x2000
 #elif defined(__ia64__)
-#define SAREA_MAX                       0x10000         /* 64kB */
+#define SAREA_MAX                       0x10000	/* 64kB */
 #else
 /* Intel 830M driver needs at least 8k SAREA */
 #define SAREA_MAX                       0x2000
@@ -51,28 +51,28 @@
 
 /** SAREA drawable */
 typedef struct drm_sarea_drawable {
-    unsigned int	stamp;
-    unsigned int	flags;
+	unsigned int stamp;
+	unsigned int flags;
 } drm_sarea_drawable_t;
 
 /** SAREA frame */
 typedef struct drm_sarea_frame {
-    unsigned int        x;
-    unsigned int        y;
-    unsigned int        width;
-    unsigned int        height;
-    unsigned int        fullscreen;
+	unsigned int x;
+	unsigned int y;
+	unsigned int width;
+	unsigned int height;
+	unsigned int fullscreen;
 } drm_sarea_frame_t;
 
 /** SAREA */
 typedef struct drm_sarea {
     /** first thing is always the DRM locking structure */
-    drm_hw_lock_t		lock;
+	drm_hw_lock_t lock;
     /** \todo Use readers/writer lock for drm_sarea::drawable_lock */
-    drm_hw_lock_t		drawable_lock;
-    drm_sarea_drawable_t	drawableTable[SAREA_MAX_DRAWABLES];	/**< drawables */
-    drm_sarea_frame_t		frame;	/**< frame */
-    drm_context_t		dummy_context;
+	drm_hw_lock_t drawable_lock;
+	drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES];	/**< drawables */
+	drm_sarea_frame_t frame;	/**< frame */
+	drm_context_t dummy_context;
 } drm_sarea_t;
 
-#endif	/* _DRM_SAREA_H_ */
+#endif				/* _DRM_SAREA_H_ */
diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index 1b91c60a..9007bd2c 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -1,10 +1,10 @@
 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
  */
 /**************************************************************************
- * 
+ *
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
- * 
+ *
  **************************************************************************/
 
 #include "drmP.h"
@@ -83,7 +83,7 @@ int i915_dma_cleanup(drm_device_t * dev)
 	 * is freed, it's too late.
 	 */
 	if (dev->irq)
-		drm_irq_uninstall (dev);
+		drm_irq_uninstall(dev);
 
 	if (dev->dev_private) {
 		drm_i915_private_t *dev_priv =
@@ -108,8 +108,8 @@ int i915_dma_cleanup(drm_device_t * dev)
 			I915_WRITE(0x02080, 0x1ffff000);
 		}
 
-		drm_free (dev->dev_private, sizeof(drm_i915_private_t),
-			   DRM_MEM_DRIVER);
+		drm_free(dev->dev_private, sizeof(drm_i915_private_t),
+			 DRM_MEM_DRIVER);
 
 		dev->dev_private = NULL;
 	}
@@ -254,8 +254,8 @@ int i915_dma_init(DRM_IOCTL_ARGS)
 
 	switch (init.func) {
 	case I915_INIT_DMA:
-		dev_priv = drm_alloc (sizeof(drm_i915_private_t),
-				       DRM_MEM_DRIVER);
+		dev_priv = drm_alloc(sizeof(drm_i915_private_t),
+				     DRM_MEM_DRIVER);
 		if (dev_priv == NULL)
 			return DRM_ERR(ENOMEM);
 		retcode = i915_initialize(dev, dev_priv, &init);
@@ -732,7 +732,7 @@ int i915_setparam(DRM_IOCTL_ARGS)
 	return 0;
 }
 
-void i915_driver_pretakedown(drm_device_t *dev)
+void i915_driver_pretakedown(drm_device_t * dev)
 {
 	if (dev->dev_private) {
 		drm_i915_private_t *dev_priv = dev->dev_private;
@@ -741,7 +741,7 @@ void i915_driver_pretakedown(drm_device_t *dev)
 	i915_dma_cleanup(dev);
 }
 
-void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp)
+void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp)
 {
 	if (dev->dev_private) {
 		drm_i915_private_t *dev_priv = dev->dev_private;
diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index f6ca92a5..19f8c0ad 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -1,10 +1,10 @@
 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  */
 /**************************************************************************
- * 
+ *
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
- * 
+ *
  **************************************************************************/
 
 #ifndef _I915_DRV_H_
@@ -88,8 +88,8 @@ extern int i915_getparam(DRM_IOCTL_ARGS);
 extern int i915_setparam(DRM_IOCTL_ARGS);
 extern int i915_cmdbuffer(DRM_IOCTL_ARGS);
 extern void i915_kernel_lost_context(drm_device_t * dev);
-extern void i915_driver_pretakedown(drm_device_t *dev);
-extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp);
+extern void i915_driver_pretakedown(drm_device_t * dev);
+extern void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp);
 
 /* i915_irq.c */
 extern int i915_irq_emit(DRM_IOCTL_ARGS);
@@ -98,9 +98,9 @@ extern int i915_wait_irq(drm_device_t * dev, int irq_nr);
 extern int i915_emit_irq(drm_device_t * dev);
 
 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
-extern void i915_driver_irq_preinstall(drm_device_t *dev);
-extern void i915_driver_irq_postinstall(drm_device_t *dev);
-extern void i915_driver_irq_uninstall(drm_device_t *dev);
+extern void i915_driver_irq_preinstall(drm_device_t * dev);
+extern void i915_driver_irq_postinstall(drm_device_t * dev);
+extern void i915_driver_irq_uninstall(drm_device_t * dev);
 
 /* i915_mem.c */
 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index 581d3f22..04c627b9 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -1,10 +1,10 @@
 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
  */
 /**************************************************************************
- * 
+ *
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
- * 
+ *
  **************************************************************************/
 
 #include "drmP.h"
diff --git a/shared-core/i915_mem.c b/shared-core/i915_mem.c
index d54a3005..0023d19c 100644
--- a/shared-core/i915_mem.c
+++ b/shared-core/i915_mem.c
@@ -1,10 +1,10 @@
 /* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*-
  */
 /**************************************************************************
- * 
+ *
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
- * 
+ *
  **************************************************************************/
 
 #include "drmP.h"
@@ -66,7 +66,7 @@ static void mark_block(drm_device_t * dev, struct mem_block *p, int in_use)
 }
 
 /* Very simple allocator for agp memory, working on a static range
- * already mapped into each client's address space.  
+ * already mapped into each client's address space.
  */
 
 static struct mem_block *split_block(struct mem_block *p, int start, int size,
@@ -74,7 +74,8 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size,
 {
 	/* Maybe cut off the start of an existing block */
 	if (start > p->start) {
-		struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS);
+		struct mem_block *newblock =
+		    drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS);
 		if (!newblock)
 			goto out;
 		newblock->start = start;
@@ -90,7 +91,8 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size,
 
 	/* Maybe cut off the end of an existing block */
 	if (size < p->size) {
-		struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS);
+		struct mem_block *newblock =
+		    drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS);
 		if (!newblock)
 			goto out;
 		newblock->start = start + size;
diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c
index c463b6cf..f06873e7 100644
--- a/shared-core/mach64_dma.c
+++ b/shared-core/mach64_dma.c
@@ -36,70 +36,71 @@
 #include "mach64_drm.h"
 #include "mach64_drv.h"
 
-
 /* ================================================================
  * Engine, FIFO control
  */
 
-int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv, int entries )
+int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv, int entries)
 {
 	int slots = 0, i;
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		slots = (MACH64_READ( MACH64_FIFO_STAT ) &
-			 MACH64_FIFO_SLOT_MASK);
-		if ( slots <= (0x8000 >> entries) ) return 0;
-		DRM_UDELAY( 1 );
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		slots = (MACH64_READ(MACH64_FIFO_STAT) & MACH64_FIFO_SLOT_MASK);
+		if (slots <= (0x8000 >> entries))
+			return 0;
+		DRM_UDELAY(1);
 	}
 
-	DRM_INFO( "%s failed! slots=%d entries=%d\n", __FUNCTION__, slots, entries );
+	DRM_INFO("%s failed! slots=%d entries=%d\n", __FUNCTION__, slots,
+		 entries);
 	return DRM_ERR(EBUSY);
 }
 
-int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv )
+int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv)
 {
 	int i, ret;
 
-	ret = mach64_do_wait_for_fifo( dev_priv, 16 );
-	if ( ret < 0 ) return ret;
+	ret = mach64_do_wait_for_fifo(dev_priv, 16);
+	if (ret < 0)
+		return ret;
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(MACH64_READ( MACH64_GUI_STAT ) & MACH64_GUI_ACTIVE) ) {
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		if (!(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE)) {
 			return 0;
 		}
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
-	DRM_INFO( "%s failed! GUI_STAT=0x%08x\n", __FUNCTION__, 
-		   MACH64_READ( MACH64_GUI_STAT ) );
-	mach64_dump_ring_info( dev_priv );
+	DRM_INFO("%s failed! GUI_STAT=0x%08x\n", __FUNCTION__,
+		 MACH64_READ(MACH64_GUI_STAT));
+	mach64_dump_ring_info(dev_priv);
 	return DRM_ERR(EBUSY);
 }
 
-int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n )
+int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
 	int i;
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		mach64_update_ring_snapshot( dev_priv );
-		if ( ring->space >= n ) {
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		mach64_update_ring_snapshot(dev_priv);
+		if (ring->space >= n) {
 			if (i > 0) {
-				DRM_DEBUG( "%s: %d usecs\n", __FUNCTION__, i );
+				DRM_DEBUG("%s: %d usecs\n", __FUNCTION__, i);
 			}
 			return 0;
 		}
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
 	/* FIXME: This is being ignored... */
-	DRM_ERROR( "failed!\n" );
-	mach64_dump_ring_info( dev_priv );
+	DRM_ERROR("failed!\n");
+	mach64_dump_ring_info(dev_priv);
 	return DRM_ERR(EBUSY);
 }
 
 /* Wait until all DMA requests have been processed... */
-static int mach64_ring_idle( drm_mach64_private_t *dev_priv )
+static int mach64_ring_idle(drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
 	u32 head;
@@ -107,108 +108,106 @@ static int mach64_ring_idle( drm_mach64_private_t *dev_priv )
 
 	head = ring->head;
 	i = 0;
-	while ( i < dev_priv->usec_timeout ) {
-		mach64_update_ring_snapshot( dev_priv );
-		if ( ring->head == ring->tail && 
-		     !(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE) ) {
+	while (i < dev_priv->usec_timeout) {
+		mach64_update_ring_snapshot(dev_priv);
+		if (ring->head == ring->tail &&
+		    !(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE)) {
 			if (i > 0) {
-				DRM_DEBUG( "%s: %d usecs\n", __FUNCTION__, i );
+				DRM_DEBUG("%s: %d usecs\n", __FUNCTION__, i);
 			}
 			return 0;
-		} 
-		if ( ring->head == head ) {
+		}
+		if (ring->head == head) {
 			++i;
 		} else {
 			head = ring->head;
 			i = 0;
 		}
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
-	DRM_INFO( "%s failed! GUI_STAT=0x%08x\n", __FUNCTION__, 
-		   MACH64_READ( MACH64_GUI_STAT ) );
-	mach64_dump_ring_info( dev_priv );
+	DRM_INFO("%s failed! GUI_STAT=0x%08x\n", __FUNCTION__,
+		 MACH64_READ(MACH64_GUI_STAT));
+	mach64_dump_ring_info(dev_priv);
 	return DRM_ERR(EBUSY);
 }
 
-static void mach64_ring_reset( drm_mach64_private_t *dev_priv )
+static void mach64_ring_reset(drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
 
-	mach64_do_release_used_buffers( dev_priv );
+	mach64_do_release_used_buffers(dev_priv);
 	ring->head_addr = ring->start_addr;
 	ring->head = ring->tail = 0;
 	ring->space = ring->size;
-	
-	MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, 
-		      ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB );
+
+	MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
+		     ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
 
 	dev_priv->ring_running = 0;
 }
 
-int mach64_do_dma_flush( drm_mach64_private_t *dev_priv )
+int mach64_do_dma_flush(drm_mach64_private_t * dev_priv)
 {
-	/* FIXME: It's not necessary to wait for idle when flushing 
+	/* FIXME: It's not necessary to wait for idle when flushing
 	 * we just need to ensure the ring will be completely processed
 	 * in finite time without another ioctl
 	 */
-	return mach64_ring_idle( dev_priv );
+	return mach64_ring_idle(dev_priv);
 }
 
-int mach64_do_dma_idle( drm_mach64_private_t *dev_priv )
+int mach64_do_dma_idle(drm_mach64_private_t * dev_priv)
 {
 	int ret;
 
 	/* wait for completion */
-	if ( (ret = mach64_ring_idle( dev_priv )) < 0 ) {
-		DRM_ERROR( "%s failed BM_GUI_TABLE=0x%08x tail: %u\n", __FUNCTION__, 
-			   MACH64_READ(MACH64_BM_GUI_TABLE), dev_priv->ring.tail );
+	if ((ret = mach64_ring_idle(dev_priv)) < 0) {
+		DRM_ERROR("%s failed BM_GUI_TABLE=0x%08x tail: %u\n",
+			  __FUNCTION__, MACH64_READ(MACH64_BM_GUI_TABLE),
+			  dev_priv->ring.tail);
 		return ret;
 	}
 
-	mach64_ring_stop( dev_priv );
+	mach64_ring_stop(dev_priv);
 
 	/* clean up after pass */
-	mach64_do_release_used_buffers( dev_priv );
+	mach64_do_release_used_buffers(dev_priv);
 	return 0;
 }
 
 /* Reset the engine.  This will stop the DMA if it is running.
  */
-int mach64_do_engine_reset( drm_mach64_private_t *dev_priv )
+int mach64_do_engine_reset(drm_mach64_private_t * dev_priv)
 {
 	u32 tmp;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
 	/* Kill off any outstanding DMA transfers.
 	 */
-	tmp = MACH64_READ( MACH64_BUS_CNTL );
-	MACH64_WRITE( MACH64_BUS_CNTL,
-				  tmp | MACH64_BUS_MASTER_DIS );
-	
+	tmp = MACH64_READ(MACH64_BUS_CNTL);
+	MACH64_WRITE(MACH64_BUS_CNTL, tmp | MACH64_BUS_MASTER_DIS);
+
 	/* Reset the GUI engine (high to low transition).
 	 */
-	tmp = MACH64_READ( MACH64_GEN_TEST_CNTL );
-	MACH64_WRITE( MACH64_GEN_TEST_CNTL,
-				  tmp & ~MACH64_GUI_ENGINE_ENABLE );
+	tmp = MACH64_READ(MACH64_GEN_TEST_CNTL);
+	MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp & ~MACH64_GUI_ENGINE_ENABLE);
 	/* Enable the GUI engine
 	 */
-	tmp = MACH64_READ( MACH64_GEN_TEST_CNTL );
-	MACH64_WRITE( MACH64_GEN_TEST_CNTL,
-				  tmp | MACH64_GUI_ENGINE_ENABLE );
+	tmp = MACH64_READ(MACH64_GEN_TEST_CNTL);
+	MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp | MACH64_GUI_ENGINE_ENABLE);
 
 	/* ensure engine is not locked up by clearing any FIFO or HOST errors
-	*/
-	tmp = MACH64_READ( MACH64_BUS_CNTL );
-	MACH64_WRITE( MACH64_BUS_CNTL, tmp | 0x00a00000 );
+	 */
+	tmp = MACH64_READ(MACH64_BUS_CNTL);
+	MACH64_WRITE(MACH64_BUS_CNTL, tmp | 0x00a00000);
 
 	/* Once GUI engine is restored, disable bus mastering */
-	MACH64_WRITE( MACH64_SRC_CNTL, 0 );
+	MACH64_WRITE(MACH64_SRC_CNTL, 0);
 
 	/* Reset descriptor ring */
-	mach64_ring_reset( dev_priv );
-	
+	mach64_ring_reset(dev_priv);
+
 	return 0;
 }
 
@@ -216,220 +215,282 @@ int mach64_do_engine_reset( drm_mach64_private_t *dev_priv )
  * Debugging output
  */
 
-void mach64_dump_engine_info( drm_mach64_private_t *dev_priv )
+void mach64_dump_engine_info(drm_mach64_private_t * dev_priv)
 {
-	DRM_INFO( "\n" );
-	if ( !dev_priv->is_pci )
-	{
-		DRM_INFO( "           AGP_BASE = 0x%08x\n", MACH64_READ( MACH64_AGP_BASE ) );
-		DRM_INFO( "           AGP_CNTL = 0x%08x\n", MACH64_READ( MACH64_AGP_CNTL ) );
+	DRM_INFO("\n");
+	if (!dev_priv->is_pci) {
+		DRM_INFO("           AGP_BASE = 0x%08x\n",
+			 MACH64_READ(MACH64_AGP_BASE));
+		DRM_INFO("           AGP_CNTL = 0x%08x\n",
+			 MACH64_READ(MACH64_AGP_CNTL));
 	}
-	DRM_INFO( "     ALPHA_TST_CNTL = 0x%08x\n", MACH64_READ( MACH64_ALPHA_TST_CNTL ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "         BM_COMMAND = 0x%08x\n", MACH64_READ( MACH64_BM_COMMAND ) );
-	DRM_INFO( "BM_FRAME_BUF_OFFSET = 0x%08x\n", MACH64_READ( MACH64_BM_FRAME_BUF_OFFSET ) );
-	DRM_INFO( "       BM_GUI_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_GUI_TABLE ) );
-	DRM_INFO( "          BM_STATUS = 0x%08x\n", MACH64_READ( MACH64_BM_STATUS ) );
-	DRM_INFO( " BM_SYSTEM_MEM_ADDR = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR ) );
-	DRM_INFO( "    BM_SYSTEM_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_TABLE ) );
-	DRM_INFO( "           BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) );
-	DRM_INFO( "\n" );
+	DRM_INFO("     ALPHA_TST_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_ALPHA_TST_CNTL));
+	DRM_INFO("\n");
+	DRM_INFO("         BM_COMMAND = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_COMMAND));
+	DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET));
+	DRM_INFO("       BM_GUI_TABLE = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_GUI_TABLE));
+	DRM_INFO("          BM_STATUS = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_STATUS));
+	DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR));
+	DRM_INFO("    BM_SYSTEM_TABLE = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_SYSTEM_TABLE));
+	DRM_INFO("           BUS_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_BUS_CNTL));
+	DRM_INFO("\n");
 	/* DRM_INFO( "         CLOCK_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLOCK_CNTL ) ); */
-	DRM_INFO( "        CLR_CMP_CLR = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_CLR ) );
-	DRM_INFO( "       CLR_CMP_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_CNTL ) );
+	DRM_INFO("        CLR_CMP_CLR = 0x%08x\n",
+		 MACH64_READ(MACH64_CLR_CMP_CLR));
+	DRM_INFO("       CLR_CMP_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_CLR_CMP_CNTL));
 	/* DRM_INFO( "        CLR_CMP_MSK = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_MSK ) ); */
-	DRM_INFO( "     CONFIG_CHIP_ID = 0x%08x\n", MACH64_READ( MACH64_CONFIG_CHIP_ID ) );
-	DRM_INFO( "        CONFIG_CNTL = 0x%08x\n", MACH64_READ( MACH64_CONFIG_CNTL ) );
-	DRM_INFO( "       CONFIG_STAT0 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT0 ) );
-	DRM_INFO( "       CONFIG_STAT1 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT1 ) );
-	DRM_INFO( "       CONFIG_STAT2 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT2 ) );
-	DRM_INFO( "            CRC_SIG = 0x%08x\n", MACH64_READ( MACH64_CRC_SIG ) );
-	DRM_INFO( "  CUSTOM_MACRO_CNTL = 0x%08x\n", MACH64_READ( MACH64_CUSTOM_MACRO_CNTL ) );
-	DRM_INFO( "\n" );
+	DRM_INFO("     CONFIG_CHIP_ID = 0x%08x\n",
+		 MACH64_READ(MACH64_CONFIG_CHIP_ID));
+	DRM_INFO("        CONFIG_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_CONFIG_CNTL));
+	DRM_INFO("       CONFIG_STAT0 = 0x%08x\n",
+		 MACH64_READ(MACH64_CONFIG_STAT0));
+	DRM_INFO("       CONFIG_STAT1 = 0x%08x\n",
+		 MACH64_READ(MACH64_CONFIG_STAT1));
+	DRM_INFO("       CONFIG_STAT2 = 0x%08x\n",
+		 MACH64_READ(MACH64_CONFIG_STAT2));
+	DRM_INFO("            CRC_SIG = 0x%08x\n", MACH64_READ(MACH64_CRC_SIG));
+	DRM_INFO("  CUSTOM_MACRO_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_CUSTOM_MACRO_CNTL));
+	DRM_INFO("\n");
 	/* DRM_INFO( "           DAC_CNTL = 0x%08x\n", MACH64_READ( MACH64_DAC_CNTL ) ); */
 	/* DRM_INFO( "           DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_DAC_REGS ) ); */
-	DRM_INFO( "        DP_BKGD_CLR = 0x%08x\n", MACH64_READ( MACH64_DP_BKGD_CLR ) );
-	DRM_INFO( "        DP_FRGD_CLR = 0x%08x\n", MACH64_READ( MACH64_DP_FRGD_CLR ) );
-	DRM_INFO( "             DP_MIX = 0x%08x\n", MACH64_READ( MACH64_DP_MIX ) );
-	DRM_INFO( "       DP_PIX_WIDTH = 0x%08x\n", MACH64_READ( MACH64_DP_PIX_WIDTH ) );
-	DRM_INFO( "             DP_SRC = 0x%08x\n", MACH64_READ( MACH64_DP_SRC ) );
-	DRM_INFO( "      DP_WRITE_MASK = 0x%08x\n", MACH64_READ( MACH64_DP_WRITE_MASK ) );
-	DRM_INFO( "         DSP_CONFIG = 0x%08x\n", MACH64_READ( MACH64_DSP_CONFIG ) );
-	DRM_INFO( "         DSP_ON_OFF = 0x%08x\n", MACH64_READ( MACH64_DSP_ON_OFF ) );
-	DRM_INFO( "           DST_CNTL = 0x%08x\n", MACH64_READ( MACH64_DST_CNTL ) );
-	DRM_INFO( "      DST_OFF_PITCH = 0x%08x\n", MACH64_READ( MACH64_DST_OFF_PITCH ) );
-	DRM_INFO( "\n" );
+	DRM_INFO("        DP_BKGD_CLR = 0x%08x\n",
+		 MACH64_READ(MACH64_DP_BKGD_CLR));
+	DRM_INFO("        DP_FRGD_CLR = 0x%08x\n",
+		 MACH64_READ(MACH64_DP_FRGD_CLR));
+	DRM_INFO("             DP_MIX = 0x%08x\n", MACH64_READ(MACH64_DP_MIX));
+	DRM_INFO("       DP_PIX_WIDTH = 0x%08x\n",
+		 MACH64_READ(MACH64_DP_PIX_WIDTH));
+	DRM_INFO("             DP_SRC = 0x%08x\n", MACH64_READ(MACH64_DP_SRC));
+	DRM_INFO("      DP_WRITE_MASK = 0x%08x\n",
+		 MACH64_READ(MACH64_DP_WRITE_MASK));
+	DRM_INFO("         DSP_CONFIG = 0x%08x\n",
+		 MACH64_READ(MACH64_DSP_CONFIG));
+	DRM_INFO("         DSP_ON_OFF = 0x%08x\n",
+		 MACH64_READ(MACH64_DSP_ON_OFF));
+	DRM_INFO("           DST_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_DST_CNTL));
+	DRM_INFO("      DST_OFF_PITCH = 0x%08x\n",
+		 MACH64_READ(MACH64_DST_OFF_PITCH));
+	DRM_INFO("\n");
 	/* DRM_INFO( "       EXT_DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_EXT_DAC_REGS ) ); */
-	DRM_INFO( "       EXT_MEM_CNTL = 0x%08x\n", MACH64_READ( MACH64_EXT_MEM_CNTL ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "          FIFO_STAT = 0x%08x\n", MACH64_READ( MACH64_FIFO_STAT ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "      GEN_TEST_CNTL = 0x%08x\n", MACH64_READ( MACH64_GEN_TEST_CNTL ) );
+	DRM_INFO("       EXT_MEM_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_EXT_MEM_CNTL));
+	DRM_INFO("\n");
+	DRM_INFO("          FIFO_STAT = 0x%08x\n",
+		 MACH64_READ(MACH64_FIFO_STAT));
+	DRM_INFO("\n");
+	DRM_INFO("      GEN_TEST_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_GEN_TEST_CNTL));
 	/* DRM_INFO( "              GP_IO = 0x%08x\n", MACH64_READ( MACH64_GP_IO ) ); */
-	DRM_INFO( "   GUI_CMDFIFO_DATA = 0x%08x\n", MACH64_READ( MACH64_GUI_CMDFIFO_DATA ) );
-	DRM_INFO( "  GUI_CMDFIFO_DEBUG = 0x%08x\n", MACH64_READ( MACH64_GUI_CMDFIFO_DEBUG ) );
-	DRM_INFO( "           GUI_CNTL = 0x%08x\n", MACH64_READ( MACH64_GUI_CNTL ) );
-	DRM_INFO( "           GUI_STAT = 0x%08x\n", MACH64_READ( MACH64_GUI_STAT ) );
-	DRM_INFO( "      GUI_TRAJ_CNTL = 0x%08x\n", MACH64_READ( MACH64_GUI_TRAJ_CNTL ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "          HOST_CNTL = 0x%08x\n", MACH64_READ( MACH64_HOST_CNTL ) );
-	DRM_INFO( "           HW_DEBUG = 0x%08x\n", MACH64_READ( MACH64_HW_DEBUG ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "    MEM_ADDR_CONFIG = 0x%08x\n", MACH64_READ( MACH64_MEM_ADDR_CONFIG ) );
-	DRM_INFO( "       MEM_BUF_CNTL = 0x%08x\n", MACH64_READ( MACH64_MEM_BUF_CNTL ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "           PAT_REG0 = 0x%08x\n", MACH64_READ( MACH64_PAT_REG0 ) );
-	DRM_INFO( "           PAT_REG1 = 0x%08x\n", MACH64_READ( MACH64_PAT_REG1 ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "            SC_LEFT = 0x%08x\n", MACH64_READ( MACH64_SC_LEFT ) );
-	DRM_INFO( "           SC_RIGHT = 0x%08x\n", MACH64_READ( MACH64_SC_RIGHT ) );
-	DRM_INFO( "             SC_TOP = 0x%08x\n", MACH64_READ( MACH64_SC_TOP ) );
-	DRM_INFO( "          SC_BOTTOM = 0x%08x\n", MACH64_READ( MACH64_SC_BOTTOM ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "      SCALE_3D_CNTL = 0x%08x\n", MACH64_READ( MACH64_SCALE_3D_CNTL ) );
-	DRM_INFO( "       SCRATCH_REG0 = 0x%08x\n", MACH64_READ( MACH64_SCRATCH_REG0 ) );
-	DRM_INFO( "       SCRATCH_REG1 = 0x%08x\n", MACH64_READ( MACH64_SCRATCH_REG1 ) );
-	DRM_INFO( "         SETUP_CNTL = 0x%08x\n", MACH64_READ( MACH64_SETUP_CNTL ) );
-	DRM_INFO( "           SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "           TEX_CNTL = 0x%08x\n", MACH64_READ( MACH64_TEX_CNTL ) );
-	DRM_INFO( "     TEX_SIZE_PITCH = 0x%08x\n", MACH64_READ( MACH64_TEX_SIZE_PITCH ) );
-	DRM_INFO( "       TIMER_CONFIG = 0x%08x\n", MACH64_READ( MACH64_TIMER_CONFIG ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "             Z_CNTL = 0x%08x\n", MACH64_READ( MACH64_Z_CNTL ) );
-	DRM_INFO( "        Z_OFF_PITCH = 0x%08x\n", MACH64_READ( MACH64_Z_OFF_PITCH ) );
-	DRM_INFO( "\n" );
+	DRM_INFO("   GUI_CMDFIFO_DATA = 0x%08x\n",
+		 MACH64_READ(MACH64_GUI_CMDFIFO_DATA));
+	DRM_INFO("  GUI_CMDFIFO_DEBUG = 0x%08x\n",
+		 MACH64_READ(MACH64_GUI_CMDFIFO_DEBUG));
+	DRM_INFO("           GUI_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_GUI_CNTL));
+	DRM_INFO("           GUI_STAT = 0x%08x\n",
+		 MACH64_READ(MACH64_GUI_STAT));
+	DRM_INFO("      GUI_TRAJ_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_GUI_TRAJ_CNTL));
+	DRM_INFO("\n");
+	DRM_INFO("          HOST_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_HOST_CNTL));
+	DRM_INFO("           HW_DEBUG = 0x%08x\n",
+		 MACH64_READ(MACH64_HW_DEBUG));
+	DRM_INFO("\n");
+	DRM_INFO("    MEM_ADDR_CONFIG = 0x%08x\n",
+		 MACH64_READ(MACH64_MEM_ADDR_CONFIG));
+	DRM_INFO("       MEM_BUF_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_MEM_BUF_CNTL));
+	DRM_INFO("\n");
+	DRM_INFO("           PAT_REG0 = 0x%08x\n",
+		 MACH64_READ(MACH64_PAT_REG0));
+	DRM_INFO("           PAT_REG1 = 0x%08x\n",
+		 MACH64_READ(MACH64_PAT_REG1));
+	DRM_INFO("\n");
+	DRM_INFO("            SC_LEFT = 0x%08x\n", MACH64_READ(MACH64_SC_LEFT));
+	DRM_INFO("           SC_RIGHT = 0x%08x\n",
+		 MACH64_READ(MACH64_SC_RIGHT));
+	DRM_INFO("             SC_TOP = 0x%08x\n", MACH64_READ(MACH64_SC_TOP));
+	DRM_INFO("          SC_BOTTOM = 0x%08x\n",
+		 MACH64_READ(MACH64_SC_BOTTOM));
+	DRM_INFO("\n");
+	DRM_INFO("      SCALE_3D_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_SCALE_3D_CNTL));
+	DRM_INFO("       SCRATCH_REG0 = 0x%08x\n",
+		 MACH64_READ(MACH64_SCRATCH_REG0));
+	DRM_INFO("       SCRATCH_REG1 = 0x%08x\n",
+		 MACH64_READ(MACH64_SCRATCH_REG1));
+	DRM_INFO("         SETUP_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_SETUP_CNTL));
+	DRM_INFO("           SRC_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_SRC_CNTL));
+	DRM_INFO("\n");
+	DRM_INFO("           TEX_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_TEX_CNTL));
+	DRM_INFO("     TEX_SIZE_PITCH = 0x%08x\n",
+		 MACH64_READ(MACH64_TEX_SIZE_PITCH));
+	DRM_INFO("       TIMER_CONFIG = 0x%08x\n",
+		 MACH64_READ(MACH64_TIMER_CONFIG));
+	DRM_INFO("\n");
+	DRM_INFO("             Z_CNTL = 0x%08x\n", MACH64_READ(MACH64_Z_CNTL));
+	DRM_INFO("        Z_OFF_PITCH = 0x%08x\n",
+		 MACH64_READ(MACH64_Z_OFF_PITCH));
+	DRM_INFO("\n");
 }
 
 #define MACH64_DUMP_CONTEXT	3
 
-static void mach64_dump_buf_info( drm_mach64_private_t *dev_priv, drm_buf_t *buf)
+static void mach64_dump_buf_info(drm_mach64_private_t * dev_priv,
+				 drm_buf_t * buf)
 {
-	u32 addr = GETBUFADDR( buf );
+	u32 addr = GETBUFADDR(buf);
 	u32 used = buf->used >> 2;
-	u32 sys_addr = MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR );
-	u32 *p = GETBUFPTR( buf );
+	u32 sys_addr = MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR);
+	u32 *p = GETBUFPTR(buf);
 	int skipped = 0;
 
-	DRM_INFO( "buffer contents:\n" );
-	
-	while ( used ) {
+	DRM_INFO("buffer contents:\n");
+
+	while (used) {
 		u32 reg, count;
 
 		reg = le32_to_cpu(*p++);
-		if( addr <= GETBUFADDR( buf ) + MACH64_DUMP_CONTEXT * 4 ||
+		if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 ||
 		    (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 &&
-		    addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) ||
-		    addr >= GETBUFADDR( buf ) + buf->used - MACH64_DUMP_CONTEXT * 4) {
+		     addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) ||
+		    addr >=
+		    GETBUFADDR(buf) + buf->used - MACH64_DUMP_CONTEXT * 4) {
 			DRM_INFO("%08x:  0x%08x\n", addr, reg);
 		}
 		addr += 4;
 		used--;
-		
+
 		count = (reg >> 16) + 1;
 		reg = reg & 0xffff;
-		reg = MMSELECT( reg );
-		while ( count && used ) {
-			if( addr <= GETBUFADDR( buf ) + MACH64_DUMP_CONTEXT * 4 ||
+		reg = MMSELECT(reg);
+		while (count && used) {
+			if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 ||
 			    (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 &&
-			    addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) ||
-			    addr >= GETBUFADDR( buf ) + buf->used - MACH64_DUMP_CONTEXT * 4) {
-				DRM_INFO("%08x:    0x%04x = 0x%08x\n", addr, reg, le32_to_cpu(*p));
+			     addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) ||
+			    addr >=
+			    GETBUFADDR(buf) + buf->used -
+			    MACH64_DUMP_CONTEXT * 4) {
+				DRM_INFO("%08x:    0x%04x = 0x%08x\n", addr,
+					 reg, le32_to_cpu(*p));
 				skipped = 0;
 			} else {
-				if( !skipped ) {
-					DRM_INFO( "  ...\n" );
+				if (!skipped) {
+					DRM_INFO("  ...\n");
 					skipped = 1;
 				}
 			}
 			p++;
 			addr += 4;
 			used--;
-			
+
 			reg += 4;
 			count--;
 		}
 	}
-	
-	DRM_INFO( "\n" );
+
+	DRM_INFO("\n");
 }
 
-void mach64_dump_ring_info( drm_mach64_private_t *dev_priv )
+void mach64_dump_ring_info(drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
 	int i, skipped;
-	
-	DRM_INFO( "\n" );
-	
+
+	DRM_INFO("\n");
+
 	DRM_INFO("ring contents:\n");
-	DRM_INFO("  head_addr: 0x%08x head: %u tail: %u\n\n", 
-		 ring->head_addr, ring->head, ring->tail );
-	
+	DRM_INFO("  head_addr: 0x%08x head: %u tail: %u\n\n",
+		 ring->head_addr, ring->head, ring->tail);
+
 	skipped = 0;
-	for ( i = 0; i < ring->size / sizeof(u32); i += 4) {
-		if( i <= MACH64_DUMP_CONTEXT * 4 || 
+	for (i = 0; i < ring->size / sizeof(u32); i += 4) {
+		if (i <= MACH64_DUMP_CONTEXT * 4 ||
 		    i >= ring->size / sizeof(u32) - MACH64_DUMP_CONTEXT * 4 ||
 		    (i >= ring->tail - MACH64_DUMP_CONTEXT * 4 &&
-		    i <= ring->tail + MACH64_DUMP_CONTEXT * 4) ||
+		     i <= ring->tail + MACH64_DUMP_CONTEXT * 4) ||
 		    (i >= ring->head - MACH64_DUMP_CONTEXT * 4 &&
-		    i <= ring->head + MACH64_DUMP_CONTEXT * 4)) {
-			DRM_INFO( "  0x%08x:  0x%08x 0x%08x 0x%08x 0x%08x%s%s\n",
-				ring->start_addr + i * sizeof(u32),
-				le32_to_cpu(((u32*) ring->start)[i + 0]),
-				le32_to_cpu(((u32*) ring->start)[i + 1]),
-				le32_to_cpu(((u32*) ring->start)[i + 2]), 
-				le32_to_cpu(((u32*) ring->start)[i + 3]),
-				i == ring->head ? " (head)" : "",
-				i == ring->tail ? " (tail)" : ""
-			);
+		     i <= ring->head + MACH64_DUMP_CONTEXT * 4)) {
+			DRM_INFO("  0x%08x:  0x%08x 0x%08x 0x%08x 0x%08x%s%s\n",
+				 ring->start_addr + i * sizeof(u32),
+				 le32_to_cpu(((u32 *) ring->start)[i + 0]),
+				 le32_to_cpu(((u32 *) ring->start)[i + 1]),
+				 le32_to_cpu(((u32 *) ring->start)[i + 2]),
+				 le32_to_cpu(((u32 *) ring->start)[i + 3]),
+				 i == ring->head ? " (head)" : "",
+				 i == ring->tail ? " (tail)" : "");
 			skipped = 0;
 		} else {
-			if( !skipped ) {
-				DRM_INFO( "  ...\n" );
+			if (!skipped) {
+				DRM_INFO("  ...\n");
 				skipped = 1;
 			}
 		}
 	}
 
-	DRM_INFO( "\n" );
-	
-	if( ring->head >= 0 && ring->head < ring->size / sizeof(u32) ) {
+	DRM_INFO("\n");
+
+	if (ring->head >= 0 && ring->head < ring->size / sizeof(u32)) {
 		struct list_head *ptr;
-		u32 addr = le32_to_cpu(((u32 *)ring->start)[ring->head + 1]);
+		u32 addr = le32_to_cpu(((u32 *) ring->start)[ring->head + 1]);
 
 		list_for_each(ptr, &dev_priv->pending) {
-			drm_mach64_freelist_t *entry = 
-				list_entry(ptr, drm_mach64_freelist_t, list);
+			drm_mach64_freelist_t *entry =
+			    list_entry(ptr, drm_mach64_freelist_t, list);
 			drm_buf_t *buf = entry->buf;
 
-			u32 buf_addr = GETBUFADDR( buf );
-			
-			if ( buf_addr <= addr && addr < buf_addr + buf->used ) {
-				mach64_dump_buf_info ( dev_priv, buf );
+			u32 buf_addr = GETBUFADDR(buf);
+
+			if (buf_addr <= addr && addr < buf_addr + buf->used) {
+				mach64_dump_buf_info(dev_priv, buf);
 			}
 		}
 	}
 
-	DRM_INFO( "\n" );
-	DRM_INFO( "       BM_GUI_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_GUI_TABLE ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "BM_FRAME_BUF_OFFSET = 0x%08x\n", MACH64_READ( MACH64_BM_FRAME_BUF_OFFSET ) );
-	DRM_INFO( " BM_SYSTEM_MEM_ADDR = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR ) );
-	DRM_INFO( "         BM_COMMAND = 0x%08x\n", MACH64_READ( MACH64_BM_COMMAND ) );
-	DRM_INFO( "\n" );
-	DRM_INFO( "          BM_STATUS = 0x%08x\n", MACH64_READ( MACH64_BM_STATUS ) );
-	DRM_INFO( "           BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) );
-	DRM_INFO( "          FIFO_STAT = 0x%08x\n", MACH64_READ( MACH64_FIFO_STAT ) );
-	DRM_INFO( "           GUI_STAT = 0x%08x\n", MACH64_READ( MACH64_GUI_STAT ) );
-	DRM_INFO( "           SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) );
+	DRM_INFO("\n");
+	DRM_INFO("       BM_GUI_TABLE = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_GUI_TABLE));
+	DRM_INFO("\n");
+	DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET));
+	DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR));
+	DRM_INFO("         BM_COMMAND = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_COMMAND));
+	DRM_INFO("\n");
+	DRM_INFO("          BM_STATUS = 0x%08x\n",
+		 MACH64_READ(MACH64_BM_STATUS));
+	DRM_INFO("           BUS_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_BUS_CNTL));
+	DRM_INFO("          FIFO_STAT = 0x%08x\n",
+		 MACH64_READ(MACH64_FIFO_STAT));
+	DRM_INFO("           GUI_STAT = 0x%08x\n",
+		 MACH64_READ(MACH64_GUI_STAT));
+	DRM_INFO("           SRC_CNTL = 0x%08x\n",
+		 MACH64_READ(MACH64_SRC_CNTL));
 }
 
-
 /* ================================================================
  * DMA test and initialization
  */
 
-static int mach64_bm_dma_test( drm_device_t *dev )
+static int mach64_bm_dma_test(drm_device_t * dev)
 {
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 	dma_addr_t data_handle;
@@ -440,15 +501,16 @@ static int mach64_bm_dma_test( drm_device_t *dev )
 	u32 src_cntl, pat_reg0, pat_reg1;
 	int i, count, failed;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
 	table = (u32 *) dev_priv->ring.start;
 
 	/* FIXME: get a dma buffer from the freelist here */
-	DRM_DEBUG( "Allocating data memory ...\n" );
-	cpu_addr_data = drm_pci_alloc( dev, 0x1000, 0x1000, 0xfffffffful, &data_handle );
+	DRM_DEBUG("Allocating data memory ...\n");
+	cpu_addr_data =
+	    drm_pci_alloc(dev, 0x1000, 0x1000, 0xfffffffful, &data_handle);
 	if (!cpu_addr_data || !data_handle) {
-		DRM_INFO( "data-memory allocation failed!\n" );
+		DRM_INFO("data-memory allocation failed!\n");
 		return DRM_ERR(ENOMEM);
 	} else {
 		data = (u32 *) cpu_addr_data;
@@ -459,28 +521,28 @@ static int mach64_bm_dma_test( drm_device_t *dev )
 	 * in case our test fails.  This prevents the X server
 	 * from disabling it's cache for this register
 	 */
-	src_cntl = MACH64_READ( MACH64_SRC_CNTL );
-	pat_reg0 = MACH64_READ( MACH64_PAT_REG0 );
-	pat_reg1 = MACH64_READ( MACH64_PAT_REG1 );
+	src_cntl = MACH64_READ(MACH64_SRC_CNTL);
+	pat_reg0 = MACH64_READ(MACH64_PAT_REG0);
+	pat_reg1 = MACH64_READ(MACH64_PAT_REG1);
 
-	mach64_do_wait_for_fifo( dev_priv, 3 );
+	mach64_do_wait_for_fifo(dev_priv, 3);
 
-	MACH64_WRITE( MACH64_SRC_CNTL, 0 );
-	MACH64_WRITE( MACH64_PAT_REG0, 0x11111111 );
-	MACH64_WRITE( MACH64_PAT_REG1, 0x11111111 );
+	MACH64_WRITE(MACH64_SRC_CNTL, 0);
+	MACH64_WRITE(MACH64_PAT_REG0, 0x11111111);
+	MACH64_WRITE(MACH64_PAT_REG1, 0x11111111);
 
-	mach64_do_wait_for_idle( dev_priv );
+	mach64_do_wait_for_idle(dev_priv);
 
-	for (i=0; i < 2; i++) {
+	for (i = 0; i < 2; i++) {
 		u32 reg;
-		reg = MACH64_READ( (MACH64_PAT_REG0 + i*4) );
-		DRM_DEBUG( "(Before DMA Transfer) reg %d = 0x%08x\n", i, reg );
-		if ( reg != 0x11111111 ) {
-			DRM_INFO( "Error initializing test registers\n" );
-			DRM_INFO( "resetting engine ...\n");
-			mach64_do_engine_reset( dev_priv );
-			DRM_INFO( "freeing data buffer memory.\n" );
-			drm_pci_free( dev, 0x1000, cpu_addr_data, data_handle );
+		reg = MACH64_READ((MACH64_PAT_REG0 + i * 4));
+		DRM_DEBUG("(Before DMA Transfer) reg %d = 0x%08x\n", i, reg);
+		if (reg != 0x11111111) {
+			DRM_INFO("Error initializing test registers\n");
+			DRM_INFO("resetting engine ...\n");
+			mach64_do_engine_reset(dev_priv);
+			DRM_INFO("freeing data buffer memory.\n");
+			drm_pci_free(dev, 0x1000, cpu_addr_data, data_handle);
 			return DRM_ERR(EIO);
 		}
 	}
@@ -493,153 +555,152 @@ static int mach64_bm_dma_test( drm_device_t *dev )
 	data[count++] = expected[1] = 0xaaaaaaaa;
 
 	while (count < 1020) {
-		data[count++] = cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16));
+		data[count++] =
+		    cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16));
 		data[count++] = 0x22222222;
 		data[count++] = 0xaaaaaaaa;
 	}
 	data[count++] = cpu_to_le32(DMAREG(MACH64_SRC_CNTL) | (0 << 16));
 	data[count++] = 0;
 
-	DRM_DEBUG( "Preparing table ...\n" );
-	table[MACH64_DMA_FRAME_BUF_OFFSET] = cpu_to_le32(MACH64_BM_ADDR + 
+	DRM_DEBUG("Preparing table ...\n");
+	table[MACH64_DMA_FRAME_BUF_OFFSET] = cpu_to_le32(MACH64_BM_ADDR +
 							 MACH64_APERTURE_OFFSET);
-	table[MACH64_DMA_SYS_MEM_ADDR]     = cpu_to_le32(data_addr);
-	table[MACH64_DMA_COMMAND]          = cpu_to_le32(count * sizeof( u32 ) 
-							 | MACH64_DMA_HOLD_OFFSET 
-							 | MACH64_DMA_EOL);
-	table[MACH64_DMA_RESERVED]         = 0;
-
-	DRM_DEBUG( "table[0] = 0x%08x\n", table[0] );
-	DRM_DEBUG( "table[1] = 0x%08x\n", table[1] );
-	DRM_DEBUG( "table[2] = 0x%08x\n", table[2] );
-	DRM_DEBUG( "table[3] = 0x%08x\n", table[3] );
-
-	for ( i = 0 ; i < 6 ; i++ ) {
-		DRM_DEBUG( " data[%d] = 0x%08x\n", i, data[i] );
+	table[MACH64_DMA_SYS_MEM_ADDR] = cpu_to_le32(data_addr);
+	table[MACH64_DMA_COMMAND] = cpu_to_le32(count * sizeof(u32)
+						| MACH64_DMA_HOLD_OFFSET
+						| MACH64_DMA_EOL);
+	table[MACH64_DMA_RESERVED] = 0;
+
+	DRM_DEBUG("table[0] = 0x%08x\n", table[0]);
+	DRM_DEBUG("table[1] = 0x%08x\n", table[1]);
+	DRM_DEBUG("table[2] = 0x%08x\n", table[2]);
+	DRM_DEBUG("table[3] = 0x%08x\n", table[3]);
+
+	for (i = 0; i < 6; i++) {
+		DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]);
 	}
-	DRM_DEBUG( " ...\n" );
-	for ( i = count-5 ; i < count ; i++ ) {
-		DRM_DEBUG( " data[%d] = 0x%08x\n", i, data[i] );
+	DRM_DEBUG(" ...\n");
+	for (i = count - 5; i < count; i++) {
+		DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]);
 	}
 
 	DRM_MEMORYBARRIER();
 
-	DRM_DEBUG( "waiting for idle...\n" );
-	if ( ( i = mach64_do_wait_for_idle( dev_priv ) ) ) {
-		DRM_INFO( "mach64_do_wait_for_idle failed (result=%d)\n", i);
-		DRM_INFO( "resetting engine ...\n");
-		mach64_do_engine_reset( dev_priv );
-		mach64_do_wait_for_fifo( dev_priv, 3 );
-		MACH64_WRITE( MACH64_SRC_CNTL, src_cntl );
-		MACH64_WRITE( MACH64_PAT_REG0, pat_reg0 );
-		MACH64_WRITE( MACH64_PAT_REG1, pat_reg1 );
-		DRM_INFO( "freeing data buffer memory.\n" );
-		drm_pci_free( dev, 0x1000, cpu_addr_data, data_handle );
+	DRM_DEBUG("waiting for idle...\n");
+	if ((i = mach64_do_wait_for_idle(dev_priv))) {
+		DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i);
+		DRM_INFO("resetting engine ...\n");
+		mach64_do_engine_reset(dev_priv);
+		mach64_do_wait_for_fifo(dev_priv, 3);
+		MACH64_WRITE(MACH64_SRC_CNTL, src_cntl);
+		MACH64_WRITE(MACH64_PAT_REG0, pat_reg0);
+		MACH64_WRITE(MACH64_PAT_REG1, pat_reg1);
+		DRM_INFO("freeing data buffer memory.\n");
+		drm_pci_free(dev, 0x1000, cpu_addr_data, data_handle);
 		return i;
 	}
-	DRM_DEBUG( "waiting for idle...done\n" );
+	DRM_DEBUG("waiting for idle...done\n");
 
-	DRM_DEBUG( "BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) );
-	DRM_DEBUG( "SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) );
-	DRM_DEBUG( "\n" );
-	DRM_DEBUG( "data bus addr = 0x%08x\n", data_addr );
-	DRM_DEBUG( "table bus addr = 0x%08x\n", dev_priv->ring.start_addr );
+	DRM_DEBUG("BUS_CNTL = 0x%08x\n", MACH64_READ(MACH64_BUS_CNTL));
+	DRM_DEBUG("SRC_CNTL = 0x%08x\n", MACH64_READ(MACH64_SRC_CNTL));
+	DRM_DEBUG("\n");
+	DRM_DEBUG("data bus addr = 0x%08x\n", data_addr);
+	DRM_DEBUG("table bus addr = 0x%08x\n", dev_priv->ring.start_addr);
 
-	DRM_DEBUG( "starting DMA transfer...\n" );
-	MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD,
-			  dev_priv->ring.start_addr |
-			  MACH64_CIRCULAR_BUF_SIZE_16KB );
+	DRM_DEBUG("starting DMA transfer...\n");
+	MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
+		     dev_priv->ring.start_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
 
-	MACH64_WRITE( MACH64_SRC_CNTL, 
-		      MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
-		      MACH64_SRC_BM_OP_SYSTEM_TO_REG );
+	MACH64_WRITE(MACH64_SRC_CNTL,
+		     MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
+		     MACH64_SRC_BM_OP_SYSTEM_TO_REG);
 
 	/* Kick off the transfer */
-	DRM_DEBUG( "starting DMA transfer... done.\n" );
-	MACH64_WRITE( MACH64_DST_HEIGHT_WIDTH, 0 );
+	DRM_DEBUG("starting DMA transfer... done.\n");
+	MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0);
 
-	DRM_DEBUG( "waiting for idle...\n" );
+	DRM_DEBUG("waiting for idle...\n");
 
-	if ( ( i = mach64_do_wait_for_idle( dev_priv ) ) ) {
+	if ((i = mach64_do_wait_for_idle(dev_priv))) {
 		/* engine locked up, dump register state and reset */
-		DRM_INFO( "mach64_do_wait_for_idle failed (result=%d)\n", i);
-		mach64_dump_engine_info( dev_priv );
-		DRM_INFO( "resetting engine ...\n");
-		mach64_do_engine_reset( dev_priv );
-		mach64_do_wait_for_fifo( dev_priv, 3 );
-		MACH64_WRITE( MACH64_SRC_CNTL, src_cntl );
-		MACH64_WRITE( MACH64_PAT_REG0, pat_reg0 );
-		MACH64_WRITE( MACH64_PAT_REG1, pat_reg1 );
-		DRM_INFO( "freeing data buffer memory.\n" );
-		drm_pci_free( dev, 0x1000, cpu_addr_data, data_handle );
+		DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i);
+		mach64_dump_engine_info(dev_priv);
+		DRM_INFO("resetting engine ...\n");
+		mach64_do_engine_reset(dev_priv);
+		mach64_do_wait_for_fifo(dev_priv, 3);
+		MACH64_WRITE(MACH64_SRC_CNTL, src_cntl);
+		MACH64_WRITE(MACH64_PAT_REG0, pat_reg0);
+		MACH64_WRITE(MACH64_PAT_REG1, pat_reg1);
+		DRM_INFO("freeing data buffer memory.\n");
+		drm_pci_free(dev, 0x1000, cpu_addr_data, data_handle);
 		return i;
 	}
 
-	DRM_DEBUG( "waiting for idle...done\n" );
+	DRM_DEBUG("waiting for idle...done\n");
 
 	/* restore SRC_CNTL */
-	mach64_do_wait_for_fifo( dev_priv, 1 );
-	MACH64_WRITE( MACH64_SRC_CNTL, src_cntl );
+	mach64_do_wait_for_fifo(dev_priv, 1);
+	MACH64_WRITE(MACH64_SRC_CNTL, src_cntl);
 
 	failed = 0;
 
 	/* Check register values to see if the GUI master operation succeeded */
-	for ( i = 0; i < 2; i++ ) {
+	for (i = 0; i < 2; i++) {
 		u32 reg;
-		reg = MACH64_READ( (MACH64_PAT_REG0 + i*4) );
-		DRM_DEBUG( "(After DMA Transfer) reg %d = 0x%08x\n", i, reg );
+		reg = MACH64_READ((MACH64_PAT_REG0 + i * 4));
+		DRM_DEBUG("(After DMA Transfer) reg %d = 0x%08x\n", i, reg);
 		if (reg != expected[i]) {
 			failed = -1;
 		}
 	}
 
 	/* restore pattern registers */
-	mach64_do_wait_for_fifo( dev_priv, 2 );
-	MACH64_WRITE( MACH64_PAT_REG0, pat_reg0 );
-	MACH64_WRITE( MACH64_PAT_REG1, pat_reg1 );
+	mach64_do_wait_for_fifo(dev_priv, 2);
+	MACH64_WRITE(MACH64_PAT_REG0, pat_reg0);
+	MACH64_WRITE(MACH64_PAT_REG1, pat_reg1);
 
-	DRM_DEBUG( "freeing data buffer memory.\n" );
-	drm_pci_free( dev, 0x1000, cpu_addr_data, data_handle );
-	DRM_DEBUG( "returning ...\n" );
+	DRM_DEBUG("freeing data buffer memory.\n");
+	drm_pci_free(dev, 0x1000, cpu_addr_data, data_handle);
+	DRM_DEBUG("returning ...\n");
 
 	return failed;
 }
 
-
-static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init )
+static int mach64_do_dma_init(drm_device_t * dev, drm_mach64_init_t * init)
 {
 	drm_mach64_private_t *dev_priv;
 	u32 tmp;
 	int i, ret;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	dev_priv = drm_alloc( sizeof(drm_mach64_private_t), DRM_MEM_DRIVER );
-	if ( dev_priv == NULL )
+	dev_priv = drm_alloc(sizeof(drm_mach64_private_t), DRM_MEM_DRIVER);
+	if (dev_priv == NULL)
 		return DRM_ERR(ENOMEM);
-	
-	memset( dev_priv, 0, sizeof(drm_mach64_private_t) );
 
-	dev_priv->is_pci	= init->is_pci;
+	memset(dev_priv, 0, sizeof(drm_mach64_private_t));
+
+	dev_priv->is_pci = init->is_pci;
 
-	dev_priv->fb_bpp	= init->fb_bpp;
-	dev_priv->front_offset  = init->front_offset;
-	dev_priv->front_pitch   = init->front_pitch;
-	dev_priv->back_offset   = init->back_offset;
-	dev_priv->back_pitch    = init->back_pitch;
+	dev_priv->fb_bpp = init->fb_bpp;
+	dev_priv->front_offset = init->front_offset;
+	dev_priv->front_pitch = init->front_pitch;
+	dev_priv->back_offset = init->back_offset;
+	dev_priv->back_pitch = init->back_pitch;
 
-	dev_priv->depth_bpp     = init->depth_bpp;
-	dev_priv->depth_offset  = init->depth_offset;
-	dev_priv->depth_pitch   = init->depth_pitch;
+	dev_priv->depth_bpp = init->depth_bpp;
+	dev_priv->depth_offset = init->depth_offset;
+	dev_priv->depth_pitch = init->depth_pitch;
 
-	dev_priv->front_offset_pitch	= (((dev_priv->front_pitch/8) << 22) |
-					   (dev_priv->front_offset >> 3));
-	dev_priv->back_offset_pitch	= (((dev_priv->back_pitch/8) << 22) |
-					   (dev_priv->back_offset >> 3));
-	dev_priv->depth_offset_pitch	= (((dev_priv->depth_pitch/8) << 22) |
-					   (dev_priv->depth_offset >> 3));
+	dev_priv->front_offset_pitch = (((dev_priv->front_pitch / 8) << 22) |
+					(dev_priv->front_offset >> 3));
+	dev_priv->back_offset_pitch = (((dev_priv->back_pitch / 8) << 22) |
+				       (dev_priv->back_offset >> 3));
+	dev_priv->depth_offset_pitch = (((dev_priv->depth_pitch / 8) << 22) |
+					(dev_priv->depth_offset >> 3));
 
-	dev_priv->usec_timeout		= 1000000;
+	dev_priv->usec_timeout = 1000000;
 
 	/* Set up the freelist, placeholder list and pending list */
 	INIT_LIST_HEAD(&dev_priv->free_list);
@@ -651,152 +712,157 @@ static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init )
 	if (!dev_priv->sarea) {
 		DRM_ERROR("can not find sarea!\n");
 		dev->dev_private = (void *)dev_priv;
-	   	mach64_do_cleanup_dma(dev);
-	   	return DRM_ERR(EINVAL);
+		mach64_do_cleanup_dma(dev);
+		return DRM_ERR(EINVAL);
 	}
 	dev_priv->fb = drm_core_findmap(dev, init->fb_offset);
 	if (!dev_priv->fb) {
 		DRM_ERROR("can not find frame buffer map!\n");
 		dev->dev_private = (void *)dev_priv;
-	   	mach64_do_cleanup_dma(dev);
-	   	return DRM_ERR(EINVAL);
+		mach64_do_cleanup_dma(dev);
+		return DRM_ERR(EINVAL);
 	}
 	dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
 	if (!dev_priv->mmio) {
 		DRM_ERROR("can not find mmio map!\n");
 		dev->dev_private = (void *)dev_priv;
-	   	mach64_do_cleanup_dma(dev);
-	   	return DRM_ERR(EINVAL);
+		mach64_do_cleanup_dma(dev);
+		return DRM_ERR(EINVAL);
 	}
 
 	dev_priv->sarea_priv = (drm_mach64_sarea_t *)
-		((u8 *)dev_priv->sarea->handle +
-		 init->sarea_priv_offset);
+	    ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 
-	if( !dev_priv->is_pci ) {
+	if (!dev_priv->is_pci) {
 		dev_priv->ring_map = drm_core_findmap(dev, init->ring_offset);
-		if ( !dev_priv->ring_map ) {
-			DRM_ERROR( "can not find ring map!\n" );
+		if (!dev_priv->ring_map) {
+			DRM_ERROR("can not find ring map!\n");
 			dev->dev_private = (void *)dev_priv;
 			mach64_do_cleanup_dma(dev);
 			return DRM_ERR(EINVAL);
 		}
-		drm_core_ioremap( dev_priv->ring_map, dev );
-		if ( !dev_priv->ring_map->handle ) {
-		        DRM_ERROR( "can not ioremap virtual address for"
-                                   " descriptor ring\n" );
-			dev->dev_private = (void *) dev_priv;
-			mach64_do_cleanup_dma( dev );
+		drm_core_ioremap(dev_priv->ring_map, dev);
+		if (!dev_priv->ring_map->handle) {
+			DRM_ERROR("can not ioremap virtual address for"
+				  " descriptor ring\n");
+			dev->dev_private = (void *)dev_priv;
+			mach64_do_cleanup_dma(dev);
 			return DRM_ERR(ENOMEM);
-                }
-		dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
-		if ( !dev->agp_buffer_map ) {
-			DRM_ERROR( "can not find dma buffer map!\n" );
+		}
+		dev->agp_buffer_map =
+		    drm_core_findmap(dev, init->buffers_offset);
+		if (!dev->agp_buffer_map) {
+			DRM_ERROR("can not find dma buffer map!\n");
 			dev->dev_private = (void *)dev_priv;
-			mach64_do_cleanup_dma( dev );
+			mach64_do_cleanup_dma(dev);
 			return DRM_ERR(EINVAL);
 		}
-		/* there might be a nicer way to do this - 
+		/* there might be a nicer way to do this -
 		   dev isn't passed all the way though the mach64 - DA */
 		dev_priv->dev_buffers = dev->agp_buffer_map;
 
-		drm_core_ioremap( dev->agp_buffer_map, dev );
-		if ( !dev->agp_buffer_map->handle ) {
-			DRM_ERROR( "can not ioremap virtual address for"
-				   " dma buffer\n" );
-			dev->dev_private = (void *) dev_priv;
-			mach64_do_cleanup_dma( dev );
+		drm_core_ioremap(dev->agp_buffer_map, dev);
+		if (!dev->agp_buffer_map->handle) {
+			DRM_ERROR("can not ioremap virtual address for"
+				  " dma buffer\n");
+			dev->dev_private = (void *)dev_priv;
+			mach64_do_cleanup_dma(dev);
 			return DRM_ERR(ENOMEM);
 		}
-		dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset);
+		dev_priv->agp_textures =
+		    drm_core_findmap(dev, init->agp_textures_offset);
 		if (!dev_priv->agp_textures) {
-			DRM_ERROR( "can not find agp texture region!\n" );
+			DRM_ERROR("can not find agp texture region!\n");
 			dev->dev_private = (void *)dev_priv;
-			mach64_do_cleanup_dma( dev );
+			mach64_do_cleanup_dma(dev);
 			return DRM_ERR(EINVAL);
 		}
 	}
 
-	dev->dev_private = (void *) dev_priv;
+	dev->dev_private = (void *)dev_priv;
 
 	dev_priv->driver_mode = init->dma_mode;
 
 	/* changing the FIFO size from the default causes problems with DMA */
-	tmp = MACH64_READ( MACH64_GUI_CNTL );
-	if ( (tmp & MACH64_CMDFIFO_SIZE_MASK) != MACH64_CMDFIFO_SIZE_128 ) {
-		DRM_INFO( "Setting FIFO size to 128 entries\n");
+	tmp = MACH64_READ(MACH64_GUI_CNTL);
+	if ((tmp & MACH64_CMDFIFO_SIZE_MASK) != MACH64_CMDFIFO_SIZE_128) {
+		DRM_INFO("Setting FIFO size to 128 entries\n");
 		/* FIFO must be empty to change the FIFO depth */
-		if ((ret=mach64_do_wait_for_idle( dev_priv ))) {
-			DRM_ERROR("wait for idle failed before changing FIFO depth!\n");
-			mach64_do_cleanup_dma( dev );
+		if ((ret = mach64_do_wait_for_idle(dev_priv))) {
+			DRM_ERROR
+			    ("wait for idle failed before changing FIFO depth!\n");
+			mach64_do_cleanup_dma(dev);
 			return ret;
 		}
-		MACH64_WRITE( MACH64_GUI_CNTL, ( ( tmp & ~MACH64_CMDFIFO_SIZE_MASK ) \
-						 | MACH64_CMDFIFO_SIZE_128 ) );
+		MACH64_WRITE(MACH64_GUI_CNTL, ((tmp & ~MACH64_CMDFIFO_SIZE_MASK)
+					       | MACH64_CMDFIFO_SIZE_128));
 		/* need to read GUI_STAT for proper sync according to docs */
-		if ((ret=mach64_do_wait_for_idle( dev_priv ))) {
-			DRM_ERROR("wait for idle failed when changing FIFO depth!\n");
-			mach64_do_cleanup_dma( dev );
+		if ((ret = mach64_do_wait_for_idle(dev_priv))) {
+			DRM_ERROR
+			    ("wait for idle failed when changing FIFO depth!\n");
+			mach64_do_cleanup_dma(dev);
 			return ret;
 		}
 	}
 
 	/* allocate descriptor memory from pci pool */
-	DRM_DEBUG( "Allocating dma descriptor ring\n" );
-	dev_priv->ring.size = 0x4000; /* 16KB */
+	DRM_DEBUG("Allocating dma descriptor ring\n");
+	dev_priv->ring.size = 0x4000;	/* 16KB */
 
-	if ( dev_priv->is_pci ) {
-		dev_priv->ring.start = drm_pci_alloc( dev, dev_priv->ring.size, 
-						       dev_priv->ring.size, 0xfffffffful,
-						       &dev_priv->ring.handle );
+	if (dev_priv->is_pci) {
+		dev_priv->ring.start = drm_pci_alloc(dev, dev_priv->ring.size,
+						     dev_priv->ring.size,
+						     0xfffffffful,
+						     &dev_priv->ring.handle);
 
 		if (!dev_priv->ring.start || !dev_priv->ring.handle) {
-			DRM_ERROR( "Allocating dma descriptor ring failed\n");
+			DRM_ERROR("Allocating dma descriptor ring failed\n");
 			return DRM_ERR(ENOMEM);
 		} else {
 			dev_priv->ring.start_addr = (u32) dev_priv->ring.handle;
 		}
-        } else {
+	} else {
 		dev_priv->ring.start = dev_priv->ring_map->handle;
 		dev_priv->ring.start_addr = (u32) dev_priv->ring_map->offset;
 	}
 
-	memset( dev_priv->ring.start, 0, dev_priv->ring.size );
-	DRM_INFO( "descriptor ring: cpu addr 0x%08x, bus addr: 0x%08x\n", 
-		  (u32) dev_priv->ring.start, dev_priv->ring.start_addr );
+	memset(dev_priv->ring.start, 0, dev_priv->ring.size);
+	DRM_INFO("descriptor ring: cpu addr 0x%08x, bus addr: 0x%08x\n",
+		 (u32) dev_priv->ring.start, dev_priv->ring.start_addr);
 
 	ret = 0;
-	if ( dev_priv->driver_mode != MACH64_MODE_MMIO ) {
+	if (dev_priv->driver_mode != MACH64_MODE_MMIO) {
 
 		/* enable block 1 registers and bus mastering */
-		MACH64_WRITE( MACH64_BUS_CNTL, 
-			      ( ( MACH64_READ(MACH64_BUS_CNTL) 
-				  | MACH64_BUS_EXT_REG_EN ) 
-				& ~MACH64_BUS_MASTER_DIS ) );
+		MACH64_WRITE(MACH64_BUS_CNTL, ((MACH64_READ(MACH64_BUS_CNTL)
+						| MACH64_BUS_EXT_REG_EN)
+					       & ~MACH64_BUS_MASTER_DIS));
 
 		/* try a DMA GUI-mastering pass and fall back to MMIO if it fails */
-		DRM_DEBUG( "Starting DMA test...\n");
-		if ( (ret=mach64_bm_dma_test( dev )) ) {
+		DRM_DEBUG("Starting DMA test...\n");
+		if ((ret = mach64_bm_dma_test(dev))) {
 			dev_priv->driver_mode = MACH64_MODE_MMIO;
 		}
 	}
 
 	switch (dev_priv->driver_mode) {
 	case MACH64_MODE_MMIO:
-		MACH64_WRITE( MACH64_BUS_CNTL, ( MACH64_READ(MACH64_BUS_CNTL) 
-						 | MACH64_BUS_EXT_REG_EN
-						 | MACH64_BUS_MASTER_DIS ) );
-		if ( init->dma_mode == MACH64_MODE_MMIO )
-			DRM_INFO( "Forcing pseudo-DMA mode\n" );
+		MACH64_WRITE(MACH64_BUS_CNTL, (MACH64_READ(MACH64_BUS_CNTL)
+					       | MACH64_BUS_EXT_REG_EN
+					       | MACH64_BUS_MASTER_DIS));
+		if (init->dma_mode == MACH64_MODE_MMIO)
+			DRM_INFO("Forcing pseudo-DMA mode\n");
 		else
-			DRM_INFO( "DMA test failed (ret=%d), using pseudo-DMA mode\n", ret );
+			DRM_INFO
+			    ("DMA test failed (ret=%d), using pseudo-DMA mode\n",
+			     ret);
 		break;
 	case MACH64_MODE_DMA_SYNC:
-		DRM_INFO( "DMA test succeeded, using synchronous DMA mode\n");
+		DRM_INFO("DMA test succeeded, using synchronous DMA mode\n");
 		break;
 	case MACH64_MODE_DMA_ASYNC:
 	default:
-		DRM_INFO( "DMA test succeeded, using asynchronous DMA mode\n");
+		DRM_INFO("DMA test succeeded, using asynchronous DMA mode\n");
 	}
 
 	dev_priv->ring_running = 0;
@@ -808,20 +874,21 @@ static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init )
 	dev_priv->ring.space = dev_priv->ring.size;
 
 	/* setup physical address and size of descriptor table */
-	mach64_do_wait_for_fifo( dev_priv, 1 );
-	MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, 
-		      ( dev_priv->ring.head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ) );
+	mach64_do_wait_for_fifo(dev_priv, 1);
+	MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
+		     (dev_priv->ring.
+		      head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB));
 
 	/* init frame counter */
 	dev_priv->sarea_priv->frames_queued = 0;
 	for (i = 0; i < MACH64_MAX_QUEUED_FRAMES; i++) {
-		dev_priv->frame_ofs[i] = ~0; /* All ones indicates placeholder */
+		dev_priv->frame_ofs[i] = ~0;	/* All ones indicates placeholder */
 	}
 
 	/* Allocate the DMA buffer freelist */
-	if ( (ret=mach64_init_freelist( dev )) ) {
+	if ((ret = mach64_init_freelist(dev))) {
 		DRM_ERROR("Freelist allocation failed\n");
-		mach64_do_cleanup_dma( dev );
+		mach64_do_cleanup_dma(dev);
 		return ret;
 	}
 
@@ -832,7 +899,7 @@ static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init )
  * MMIO Pseudo-DMA (intended primarily for debugging, not performance)
  */
 
-int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv )
+int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
 	volatile u32 *ring_read;
@@ -846,45 +913,47 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv )
 	fifo = count = reg = no_idle_wait = 0;
 	target = MACH64_BM_ADDR;
 
-	if ( (ret=mach64_do_wait_for_idle( dev_priv )) < 0) {
-		DRM_INFO( "%s: idle failed before pseudo-dma dispatch, resetting engine\n", 
-			  __FUNCTION__);
-		mach64_dump_engine_info( dev_priv );
-		mach64_do_engine_reset( dev_priv );
+	if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) {
+		DRM_INFO
+		    ("%s: idle failed before pseudo-dma dispatch, resetting engine\n",
+		     __FUNCTION__);
+		mach64_dump_engine_info(dev_priv);
+		mach64_do_engine_reset(dev_priv);
 		return ret;
 	}
 
 	ring_read = (u32 *) ring->start;
 
-	while ( ring->tail != ring->head ) {
-		u32 buf_addr, new_target, offset; 
+	while (ring->tail != ring->head) {
+		u32 buf_addr, new_target, offset;
 		u32 bytes, remaining, head, eol;
 
 		head = ring->head;
 
-		new_target = le32_to_cpu( ring_read[head++] ) - MACH64_APERTURE_OFFSET;
-		buf_addr   = le32_to_cpu( ring_read[head++] );
-		eol        = le32_to_cpu( ring_read[head]   ) & MACH64_DMA_EOL;
-		bytes      = le32_to_cpu( ring_read[head++] )
-			& ~(MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL);
+		new_target =
+		    le32_to_cpu(ring_read[head++]) - MACH64_APERTURE_OFFSET;
+		buf_addr = le32_to_cpu(ring_read[head++]);
+		eol = le32_to_cpu(ring_read[head]) & MACH64_DMA_EOL;
+		bytes = le32_to_cpu(ring_read[head++])
+		    & ~(MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL);
 		head++;
 		head &= ring->tail_mask;
 
-		/* can't wait for idle between a blit setup descriptor 
+		/* can't wait for idle between a blit setup descriptor
 		 * and a HOSTDATA descriptor or the engine will lock
 		 */
-		if (new_target == MACH64_BM_HOSTDATA && target == MACH64_BM_ADDR)
+		if (new_target == MACH64_BM_HOSTDATA
+		    && target == MACH64_BM_ADDR)
 			no_idle_wait = 1;
 
 		target = new_target;
 
 		found = 0;
 		offset = 0;
-		list_for_each(ptr, &dev_priv->pending)
-		{
+		list_for_each(ptr, &dev_priv->pending) {
 			entry = list_entry(ptr, drm_mach64_freelist_t, list);
 			buf = entry->buf;
-			offset = buf_addr - GETBUFADDR( buf );
+			offset = buf_addr - GETBUFADDR(buf);
 			if (offset >= 0 && offset < MACH64_BUFFER_SIZE) {
 				found = 1;
 				break;
@@ -892,30 +961,34 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv )
 		}
 
 		if (!found || buf == NULL) {
-			DRM_ERROR("Couldn't find pending buffer: head: %u tail: %u buf_addr: 0x%08x %s\n",
-				  head, ring->tail, buf_addr, (eol ? "eol" : ""));
-			mach64_dump_ring_info( dev_priv );
-			mach64_do_engine_reset( dev_priv );
+			DRM_ERROR
+			    ("Couldn't find pending buffer: head: %u tail: %u buf_addr: 0x%08x %s\n",
+			     head, ring->tail, buf_addr, (eol ? "eol" : ""));
+			mach64_dump_ring_info(dev_priv);
+			mach64_do_engine_reset(dev_priv);
 			return DRM_ERR(EINVAL);
 		}
 
-		/* Hand feed the buffer to the card via MMIO, waiting for the fifo 
-		 * every 16 writes 
+		/* Hand feed the buffer to the card via MMIO, waiting for the fifo
+		 * every 16 writes
 		 */
-		DRM_DEBUG("target: (0x%08x) %s\n", target, 
-				 (target == MACH64_BM_HOSTDATA ? "BM_HOSTDATA" : "BM_ADDR"));
-		DRM_DEBUG("offset: %u bytes: %u used: %u\n", offset, bytes, buf->used);
+		DRM_DEBUG("target: (0x%08x) %s\n", target,
+			  (target ==
+			   MACH64_BM_HOSTDATA ? "BM_HOSTDATA" : "BM_ADDR"));
+		DRM_DEBUG("offset: %u bytes: %u used: %u\n", offset, bytes,
+			  buf->used);
+
+		remaining = (buf->used - offset) >> 2;	/* dwords remaining in buffer */
+		used = bytes >> 2;	/* dwords in buffer for this descriptor */
+		buf_ptr = (u32 *) ((char *)GETBUFPTR(buf) + offset);
 
-		remaining = (buf->used - offset) >> 2; /* dwords remaining in buffer */
-		used = bytes >> 2; /* dwords in buffer for this descriptor */
-		buf_ptr = (u32 *)((char *)GETBUFPTR( buf ) + offset);
+		while (used) {
 
-		while ( used ) {
-			
 			if (count == 0) {
 				if (target == MACH64_BM_HOSTDATA) {
 					reg = DMAREG(MACH64_HOST_DATA0);
-					count = (remaining > 16) ? 16 : remaining;
+					count =
+					    (remaining > 16) ? 16 : remaining;
 					fifo = 0;
 				} else {
 					reg = le32_to_cpu(*buf_ptr++);
@@ -924,17 +997,21 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv )
 				}
 
 				reg = reg & 0xffff;
-				reg = MMSELECT( reg );
+				reg = MMSELECT(reg);
 			}
-			while ( count && used ) {
-				if ( !fifo ) {
+			while (count && used) {
+				if (!fifo) {
 					if (no_idle_wait) {
-						if ( (ret=mach64_do_wait_for_fifo( dev_priv, 16 )) < 0 ) {
+						if ((ret =
+						     mach64_do_wait_for_fifo
+						     (dev_priv, 16)) < 0) {
 							no_idle_wait = 0;
 							return ret;
 						}
 					} else {
-						if ( (ret=mach64_do_wait_for_idle( dev_priv )) < 0 ) {
+						if ((ret =
+						     mach64_do_wait_for_idle
+						     (dev_priv)) < 0) {
 							return ret;
 						}
 					}
@@ -942,8 +1019,9 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv )
 				}
 				--fifo;
 				MACH64_WRITE(reg, le32_to_cpu(*buf_ptr++));
-				used--; remaining--;
-					
+				used--;
+				remaining--;
+
 				reg += 4;
 				count--;
 			}
@@ -953,13 +1031,13 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv )
 		ring->space += (4 * sizeof(u32));
 	}
 
-	if ( (ret=mach64_do_wait_for_idle( dev_priv )) < 0 ) {
+	if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) {
 		return ret;
 	}
-	MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, 
-		      ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB );
+	MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
+		     ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
 
-	DRM_DEBUG( "%s completed\n", __FUNCTION__ );
+	DRM_DEBUG("%s completed\n", __FUNCTION__);
 	return 0;
 }
 
@@ -967,38 +1045,41 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv )
  * DMA cleanup
  */
 
-int mach64_do_cleanup_dma( drm_device_t *dev )
+int mach64_do_cleanup_dma(drm_device_t * dev)
 {
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
 	/* Make sure interrupts are disabled here because the uninstall ioctl
 	 * may not have been called from userspace and after dev_private
 	 * is freed, it's too late.
 	 */
-	if ( dev->irq ) drm_irq_uninstall(dev);
+	if (dev->irq)
+		drm_irq_uninstall(dev);
 
-	if ( dev->dev_private ) {
+	if (dev->dev_private) {
 		drm_mach64_private_t *dev_priv = dev->dev_private;
 
-		if ( dev_priv->is_pci ) {
-			if ( (dev_priv->ring.start != NULL) && dev_priv->ring.handle ) {
-				drm_pci_free( dev, dev_priv->ring.size, 
-					       dev_priv->ring.start, dev_priv->ring.handle );
+		if (dev_priv->is_pci) {
+			if ((dev_priv->ring.start != NULL)
+			    && dev_priv->ring.handle) {
+				drm_pci_free(dev, dev_priv->ring.size,
+					     dev_priv->ring.start,
+					     dev_priv->ring.handle);
 			}
 		} else {
-			if ( dev_priv->ring_map )
-				drm_core_ioremapfree( dev_priv->ring_map, dev );
+			if (dev_priv->ring_map)
+				drm_core_ioremapfree(dev_priv->ring_map, dev);
 		}
 
-		if ( dev->agp_buffer_map ) {
-			drm_core_ioremapfree( dev->agp_buffer_map, dev );
+		if (dev->agp_buffer_map) {
+			drm_core_ioremapfree(dev->agp_buffer_map, dev);
 			dev->agp_buffer_map = NULL;
 		}
 
-		mach64_destroy_freelist( dev );
+		mach64_destroy_freelist(dev);
 
-		drm_free( dev_priv, sizeof(drm_mach64_private_t),
-			   DRM_MEM_DRIVER );
+		drm_free(dev_priv, sizeof(drm_mach64_private_t),
+			 DRM_MEM_DRIVER);
 		dev->dev_private = NULL;
 	}
 
@@ -1009,70 +1090,69 @@ int mach64_do_cleanup_dma( drm_device_t *dev )
  * IOCTL handlers
  */
 
-int mach64_dma_init( DRM_IOCTL_ARGS )
+int mach64_dma_init(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mach64_init_t init;
-		
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	DRM_DEBUG("%s\n", __FUNCTION__);
+
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( init, (drm_mach64_init_t *)data, 
-	    sizeof(init) );
+	DRM_COPY_FROM_USER_IOCTL(init, (drm_mach64_init_t *) data,
+				 sizeof(init));
 
-	switch ( init.func ) {
+	switch (init.func) {
 	case DRM_MACH64_INIT_DMA:
-		return mach64_do_dma_init( dev, &init );
+		return mach64_do_dma_init(dev, &init);
 	case DRM_MACH64_CLEANUP_DMA:
-		return mach64_do_cleanup_dma( dev );
+		return mach64_do_cleanup_dma(dev);
 	}
-		
+
 	return DRM_ERR(EINVAL);
 }
 
-int mach64_dma_idle( DRM_IOCTL_ARGS )
+int mach64_dma_idle(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	return mach64_do_dma_idle( dev_priv );
+	return mach64_do_dma_idle(dev_priv);
 }
 
-int mach64_dma_flush( DRM_IOCTL_ARGS )
+int mach64_dma_flush(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	return mach64_do_dma_flush( dev_priv );
+	return mach64_do_dma_flush(dev_priv);
 }
 
-int mach64_engine_reset( DRM_IOCTL_ARGS )
+int mach64_engine_reset(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mach64_private_t *dev_priv = dev->dev_private;
-	
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	return mach64_do_engine_reset( dev_priv );
-}
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
+	return mach64_do_engine_reset(dev_priv);
+}
 
 /* ================================================================
  * Freelist management
  */
 
-int mach64_init_freelist( drm_device_t *dev )
+int mach64_init_freelist(drm_device_t * dev)
 {
 	drm_device_dma_t *dma = dev->dma;
 	drm_mach64_private_t *dev_priv = dev->dev_private;
@@ -1080,14 +1160,16 @@ int mach64_init_freelist( drm_device_t *dev )
 	struct list_head *ptr;
 	int i;
 
-	DRM_DEBUG("%s: adding %d buffers to freelist\n", __FUNCTION__, dma->buf_count);
+	DRM_DEBUG("%s: adding %d buffers to freelist\n", __FUNCTION__,
+		  dma->buf_count);
 
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		if ((entry = 
-		     (drm_mach64_freelist_t *) drm_alloc(sizeof(drm_mach64_freelist_t), 
-							  DRM_MEM_BUFLISTS)) == NULL)
+	for (i = 0; i < dma->buf_count; i++) {
+		if ((entry =
+		     (drm_mach64_freelist_t *)
+		     drm_alloc(sizeof(drm_mach64_freelist_t),
+			       DRM_MEM_BUFLISTS)) == NULL)
 			return DRM_ERR(ENOMEM);
-		memset( entry, 0, sizeof(drm_mach64_freelist_t) );
+		memset(entry, 0, sizeof(drm_mach64_freelist_t));
 		entry->buf = dma->buflist[i];
 		ptr = &entry->list;
 		list_add_tail(ptr, &dev_priv->free_list);
@@ -1096,7 +1178,7 @@ int mach64_init_freelist( drm_device_t *dev )
 	return 0;
 }
 
-void mach64_destroy_freelist( drm_device_t *dev )
+void mach64_destroy_freelist(drm_device_t * dev)
 {
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 	drm_mach64_freelist_t *entry;
@@ -1105,44 +1187,40 @@ void mach64_destroy_freelist( drm_device_t *dev )
 
 	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	list_for_each_safe(ptr, tmp, &dev_priv->pending)
-	{
+	list_for_each_safe(ptr, tmp, &dev_priv->pending) {
 		list_del(ptr);
 		entry = list_entry(ptr, drm_mach64_freelist_t, list);
 		drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS);
 	}
-	list_for_each_safe(ptr, tmp, &dev_priv->placeholders)
-	{
+	list_for_each_safe(ptr, tmp, &dev_priv->placeholders) {
 		list_del(ptr);
 		entry = list_entry(ptr, drm_mach64_freelist_t, list);
 		drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS);
 	}
 
-	list_for_each_safe(ptr, tmp, &dev_priv->free_list)
-	{
+	list_for_each_safe(ptr, tmp, &dev_priv->free_list) {
 		list_del(ptr);
 		entry = list_entry(ptr, drm_mach64_freelist_t, list);
 		drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS);
 	}
 }
 
-/* IMPORTANT: This function should only be called when the engine is idle or locked up, 
+/* IMPORTANT: This function should only be called when the engine is idle or locked up,
  * as it assumes all buffers in the pending list have been completed by the hardware.
  */
-int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv )
+int mach64_do_release_used_buffers(drm_mach64_private_t * dev_priv)
 {
 	struct list_head *ptr;
 	struct list_head *tmp;
 	drm_mach64_freelist_t *entry;
 	int i;
 
-	if ( list_empty(&dev_priv->pending) )
+	if (list_empty(&dev_priv->pending))
 		return 0;
 
 	/* Iterate the pending list and move all buffers into the freelist... */
 	i = 0;
-	list_for_each_safe(ptr, tmp, &dev_priv->pending)
-	{
+	list_for_each_safe(ptr, tmp, &dev_priv->pending) {
 		entry = list_entry(ptr, drm_mach64_freelist_t, list);
 		if (entry->discard) {
 			entry->buf->pending = 0;
@@ -1152,12 +1230,13 @@ int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv )
 		}
 	}
 
-	DRM_DEBUG( "%s: released %d buffers from pending list\n", __FUNCTION__, i );
+	DRM_DEBUG("%s: released %d buffers from pending list\n", __FUNCTION__,
+		  i);
 
-        return 0;
+	return 0;
 }
 
-drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv )
+drm_buf_t *mach64_freelist_get(drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
 	drm_mach64_freelist_t *entry;
@@ -1165,62 +1244,78 @@ drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv )
 	struct list_head *tmp;
 	int t;
 
-	if ( list_empty(&dev_priv->free_list) ) {
+	if (list_empty(&dev_priv->free_list)) {
 		u32 head, tail, ofs;
 
-		if ( list_empty( &dev_priv->pending ) ) {
-			DRM_ERROR( "Couldn't get buffer - pending and free lists empty\n" );
+		if (list_empty(&dev_priv->pending)) {
+			DRM_ERROR
+			    ("Couldn't get buffer - pending and free lists empty\n");
 			t = 0;
-			list_for_each( ptr, &dev_priv->placeholders ) {
+			list_for_each(ptr, &dev_priv->placeholders) {
 				t++;
 			}
-			DRM_INFO( "Placeholders: %d\n", t );
+			DRM_INFO("Placeholders: %d\n", t);
 			return NULL;
 		}
 
 		tail = ring->tail;
-		for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
-			mach64_ring_tick( dev_priv, ring );
+		for (t = 0; t < dev_priv->usec_timeout; t++) {
+			mach64_ring_tick(dev_priv, ring);
 			head = ring->head;
 
-			if ( head == tail ) {
+			if (head == tail) {
 #if MACH64_EXTRA_CHECKING
-				if ( MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE ) {
-					DRM_ERROR( "Empty ring with non-idle engine!\n" );
-					mach64_dump_ring_info( dev_priv );
+				if (MACH64_READ(MACH64_GUI_STAT) &
+				    MACH64_GUI_ACTIVE) {
+					DRM_ERROR
+					    ("Empty ring with non-idle engine!\n");
+					mach64_dump_ring_info(dev_priv);
 					return NULL;
 				}
 #endif
 				/* last pass is complete, so release everything */
-				mach64_do_release_used_buffers( dev_priv );
-				DRM_DEBUG( "%s: idle engine, freed all buffers.\n", __FUNCTION__ );
-				if ( list_empty(&dev_priv->free_list) ) {
-					DRM_ERROR( "Freelist empty with idle engine\n" );
+				mach64_do_release_used_buffers(dev_priv);
+				DRM_DEBUG
+				    ("%s: idle engine, freed all buffers.\n",
+				     __FUNCTION__);
+				if (list_empty(&dev_priv->free_list)) {
+					DRM_ERROR
+					    ("Freelist empty with idle engine\n");
 					return NULL;
 				}
 				goto _freelist_entry_found;
 			}
-			/* Look for a completed buffer and bail out of the loop 
+			/* Look for a completed buffer and bail out of the loop
 			 * as soon as we find one -- don't waste time trying
 			 * to free extra bufs here, leave that to do_release_used_buffers
 			 */
 			list_for_each_safe(ptr, tmp, &dev_priv->pending) {
-				entry = list_entry(ptr, drm_mach64_freelist_t, list);
+				entry =
+				    list_entry(ptr, drm_mach64_freelist_t,
+					       list);
 				ofs = entry->ring_ofs;
-				if ( entry->discard &&
-				     ((head < tail && (ofs < head || ofs >= tail)) ||
-				      (head > tail && (ofs < head && ofs >= tail))) ) {
+				if (entry->discard &&
+				    ((head < tail
+				      && (ofs < head || ofs >= tail))
+				     || (head > tail
+					 && (ofs < head && ofs >= tail)))) {
 #if MACH64_EXTRA_CHECKING
 					int i;
-					
-					for ( i = head ; i != tail ; i = (i + 4) & ring->tail_mask ) {
-						u32 o1 = le32_to_cpu(((u32 *)ring->start)[i + 1]);
-						u32 o2 = GETBUFADDR( entry->buf );
-
-						if ( o1 == o2 ) {
-							DRM_ERROR ( "Attempting to free used buffer: "
-								    "i=%d  buf=0x%08x\n", i, o1 );
-							mach64_dump_ring_info( dev_priv );
+
+					for (i = head; i != tail;
+					     i = (i + 4) & ring->tail_mask) {
+						u32 o1 =
+						    le32_to_cpu(((u32 *) ring->
+								 start)[i + 1]);
+						u32 o2 = GETBUFADDR(entry->buf);
+
+						if (o1 == o2) {
+							DRM_ERROR
+							    ("Attempting to free used buffer: "
+							     "i=%d  buf=0x%08x\n",
+							     i, o1);
+							mach64_dump_ring_info
+							    (dev_priv);
 							return NULL;
 						}
 					}
@@ -1229,21 +1324,25 @@ drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv )
 					entry->buf->pending = 0;
 					list_del(ptr);
 					entry->buf->used = 0;
-					list_add_tail(ptr, &dev_priv->placeholders);
-					DRM_DEBUG( "%s: freed processed buffer (head=%d tail=%d "
-						   "buf ring ofs=%d).\n", __FUNCTION__, head, tail, ofs );
+					list_add_tail(ptr,
+						      &dev_priv->placeholders);
+					DRM_DEBUG
+					    ("%s: freed processed buffer (head=%d tail=%d "
+					     "buf ring ofs=%d).\n",
+					     __FUNCTION__, head, tail, ofs);
 					return entry->buf;
 				}
 			}
-			DRM_UDELAY( 1 );
+			DRM_UDELAY(1);
 		}
-		mach64_dump_ring_info( dev_priv );
-		DRM_ERROR( "timeout waiting for buffers: ring head_addr: 0x%08x head: %d tail: %d\n", 
-			   ring->head_addr, ring->head, ring->tail );
+		mach64_dump_ring_info(dev_priv);
+		DRM_ERROR
+		    ("timeout waiting for buffers: ring head_addr: 0x%08x head: %d tail: %d\n",
+		     ring->head_addr, ring->head, ring->tail);
 		return NULL;
 	}
 
-_freelist_entry_found:
+      _freelist_entry_found:
 	ptr = dev_priv->free_list.next;
 	list_del(ptr);
 	entry = list_entry(ptr, drm_mach64_freelist_t, list);
@@ -1256,27 +1355,30 @@ _freelist_entry_found:
  * DMA buffer request and submission IOCTL handler
  */
 
-static int mach64_dma_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
+static int mach64_dma_get_buffers(DRMFILE filp, drm_device_t * dev,
+				  drm_dma_t * d)
 {
 	int i;
 	drm_buf_t *buf;
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 
-	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
-		buf = mach64_freelist_get( dev_priv );
+	for (i = d->granted_count; i < d->request_count; i++) {
+		buf = mach64_freelist_get(dev_priv);
 #if MACH64_EXTRA_CHECKING
-		if ( !buf ) return DRM_ERR(EFAULT);
+		if (!buf)
+			return DRM_ERR(EFAULT);
 #else
-		if ( !buf ) return DRM_ERR(EAGAIN);
+		if (!buf)
+			return DRM_ERR(EAGAIN);
 #endif
 
 		buf->filp = filp;
 
-		if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
-				   sizeof(buf->idx) ) )
+		if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
+				     sizeof(buf->idx)))
 			return DRM_ERR(EFAULT);
-		if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
-				   sizeof(buf->total) ) )
+		if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
+				     sizeof(buf->total)))
 			return DRM_ERR(EFAULT);
 
 		d->granted_count++;
@@ -1284,48 +1386,45 @@ static int mach64_dma_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d
 	return 0;
 }
 
-int mach64_dma_buffers( DRM_IOCTL_ARGS )
+int mach64_dma_buffers(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_device_dma_t *dma = dev->dma;
 	drm_dma_t d;
-        int ret = 0;
+	int ret = 0;
 
-        LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
+	DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t *) data, sizeof(d));
 
-        /* Please don't send us buffers.
+	/* Please don't send us buffers.
 	 */
-        if ( d.send_count != 0 ) 
-        {
-		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
-			   DRM_CURRENTPID, d.send_count );
+	if (d.send_count != 0) {
+		DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
+			  DRM_CURRENTPID, d.send_count);
 		return DRM_ERR(EINVAL);
 	}
 
 	/* We'll send you buffers.
 	 */
-	if ( d.request_count < 0 || d.request_count > dma->buf_count ) 
-	{
-		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
-			   DRM_CURRENTPID, d.request_count, dma->buf_count );
+	if (d.request_count < 0 || d.request_count > dma->buf_count) {
+		DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
+			  DRM_CURRENTPID, d.request_count, dma->buf_count);
 		ret = DRM_ERR(EINVAL);
 	}
 
 	d.granted_count = 0;
 
-	if ( d.request_count ) 
-	{
-		ret = mach64_dma_get_buffers( filp, dev, &d );
+	if (d.request_count) {
+		ret = mach64_dma_get_buffers(filp, dev, &d);
 	}
 
-	DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
+	DRM_COPY_TO_USER_IOCTL((drm_dma_t *) data, d, sizeof(d));
 
-        return ret;
+	return ret;
 }
 
-void mach64_driver_pretakedown(drm_device_t *dev)
+void mach64_driver_pretakedown(drm_device_t * dev)
 {
-	mach64_do_cleanup_dma( dev );
+	mach64_do_cleanup_dma(dev);
 }
diff --git a/shared-core/mach64_drm.h b/shared-core/mach64_drm.h
index 9d748a37..3cf8da64 100644
--- a/shared-core/mach64_drm.h
+++ b/shared-core/mach64_drm.h
@@ -33,7 +33,6 @@
 #ifndef __MACH64_DRM_H__
 #define __MACH64_DRM_H__
 
-
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (mach64_sarea.h)
  */
@@ -57,7 +56,7 @@
 #define MACH64_UPLOAD_TEXTURE		0x0200
 #define MACH64_UPLOAD_TEX0IMAGE		0x0400
 #define MACH64_UPLOAD_TEX1IMAGE		0x0800
-#define MACH64_UPLOAD_CLIPRECTS		0x1000 /* handled client-side */
+#define MACH64_UPLOAD_CLIPRECTS		0x1000	/* handled client-side */
 #define MACH64_UPLOAD_CONTEXT		0x00ff
 #define MACH64_UPLOAD_ALL		0x1fff
 
@@ -78,7 +77,6 @@
  */
 #define MACH64_NR_SAREA_CLIPRECTS	8
 
-
 #define MACH64_CARD_HEAP		0
 #define MACH64_AGP_HEAP			1
 #define MACH64_NR_TEX_HEAPS		2
@@ -90,7 +88,7 @@
 #define MACH64_NR_CONTEXT_REGS		15
 #define MACH64_NR_TEXTURE_REGS		4
 
-#endif /* __MACH64_SAREA_DEFINES__ */
+#endif				/* __MACH64_SAREA_DEFINES__ */
 
 typedef struct {
 	unsigned int dst_off_pitch;
@@ -140,17 +138,17 @@ typedef struct drm_mach64_sarea {
 
 	/* Texture memory LRU.
 	 */
-	drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS+1];
+	drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
+						       1];
 	unsigned int tex_age[MACH64_NR_TEX_HEAPS];
 	int ctx_owner;
 } drm_mach64_sarea_t;
 
-
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (mach64_common.h)
  */
 
-/* Mach64 specific ioctls 
+/* Mach64 specific ioctls
  * The device specific ioctl range is 0x40 to 0x79.
  */
 
@@ -193,11 +191,10 @@ typedef struct drm_mach64_sarea {
 #define MACH64_PRIM_QUAD_STRIP		0x00000008
 #define MACH64_PRIM_POLYGON		0x00000009
 
-
 typedef enum _drm_mach64_dma_mode_t {
-   MACH64_MODE_DMA_ASYNC,
-   MACH64_MODE_DMA_SYNC,
-   MACH64_MODE_MMIO
+	MACH64_MODE_DMA_ASYNC,
+	MACH64_MODE_DMA_SYNC,
+	MACH64_MODE_MMIO
 } drm_mach64_dma_mode_t;
 
 typedef struct drm_mach64_init {
@@ -233,9 +230,9 @@ typedef struct drm_mach64_clear {
 
 typedef struct drm_mach64_vertex {
 	int prim;
-	void *buf;			/* Address of vertex buffer */
-	unsigned long used;		/* Number of bytes in buffer */
-	int discard;			/* Client finished with buffer? */
+	void *buf;		/* Address of vertex buffer */
+	unsigned long used;	/* Number of bytes in buffer */
+	int discard;		/* Client finished with buffer? */
 } drm_mach64_vertex_t;
 
 typedef struct drm_mach64_blit {
diff --git a/shared-core/mach64_drv.h b/shared-core/mach64_drv.h
index f047b7ef..698a6a51 100644
--- a/shared-core/mach64_drv.h
+++ b/shared-core/mach64_drv.h
@@ -49,45 +49,45 @@
 
 /* FIXME: remove these when not needed */
 /* Development driver options */
-#define MACH64_EXTRA_CHECKING     0 /* Extra sanity checks for DMA/freelist management */
-#define MACH64_VERBOSE		  0 /* Verbose debugging output */
+#define MACH64_EXTRA_CHECKING     0	/* Extra sanity checks for DMA/freelist management */
+#define MACH64_VERBOSE		  0	/* Verbose debugging output */
 
 typedef struct drm_mach64_freelist {
-	struct list_head  list;  /* List pointers for free_list, placeholders, or pending list */
-   	drm_buf_t *buf;          /* Pointer to the buffer */
-	int discard;             /* This flag is set when we're done (re)using a buffer */
-	u32 ring_ofs;            /* dword offset in ring of last descriptor for this buffer */
+	struct list_head list;	/* List pointers for free_list, placeholders, or pending list */
+	drm_buf_t *buf;		/* Pointer to the buffer */
+	int discard;		/* This flag is set when we're done (re)using a buffer */
+	u32 ring_ofs;		/* dword offset in ring of last descriptor for this buffer */
 } drm_mach64_freelist_t;
 
 typedef struct drm_mach64_descriptor_ring {
-	dma_addr_t handle;       /* handle (bus address) of ring returned by pci_alloc_consistent() */
-	void *start;             /* write pointer (cpu address) to start of descriptor ring */
-	u32 start_addr;          /* bus address of beginning of descriptor ring */
-       	int size;                /* size of ring in bytes */
-
-	u32 head_addr;           /* bus address of descriptor ring head */
-	u32 head;                /* dword offset of descriptor ring head */
-	u32 tail;                /* dword offset of descriptor ring tail */
-	u32 tail_mask;           /* mask used to wrap ring */
-	int space;               /* number of free bytes in ring */
+	dma_addr_t handle;	/* handle (bus address) of ring returned by pci_alloc_consistent() */
+	void *start;		/* write pointer (cpu address) to start of descriptor ring */
+	u32 start_addr;		/* bus address of beginning of descriptor ring */
+	int size;		/* size of ring in bytes */
+
+	u32 head_addr;		/* bus address of descriptor ring head */
+	u32 head;		/* dword offset of descriptor ring head */
+	u32 tail;		/* dword offset of descriptor ring tail */
+	u32 tail_mask;		/* mask used to wrap ring */
+	int space;		/* number of free bytes in ring */
 } drm_mach64_descriptor_ring_t;
 
 typedef struct drm_mach64_private {
 	drm_mach64_sarea_t *sarea_priv;
 
 	int is_pci;
-	drm_mach64_dma_mode_t driver_mode;       /* Async DMA, sync DMA, or MMIO */
+	drm_mach64_dma_mode_t driver_mode;	/* Async DMA, sync DMA, or MMIO */
 
-	int usec_timeout;                        /* Timeout for the wait functions */
+	int usec_timeout;	/* Timeout for the wait functions */
 
-	drm_mach64_descriptor_ring_t ring;       /* DMA descriptor table (ring buffer) */
-	int ring_running;                        /* Is bus mastering is enabled */
+	drm_mach64_descriptor_ring_t ring;	/* DMA descriptor table (ring buffer) */
+	int ring_running;	/* Is bus mastering is enabled */
 
-	struct list_head free_list;              /* Free-list head */
-	struct list_head placeholders;           /* Placeholder list for buffers held by clients */
-	struct list_head pending;                /* Buffers pending completion */
+	struct list_head free_list;	/* Free-list head */
+	struct list_head placeholders;	/* Placeholder list for buffers held by clients */
+	struct list_head pending;	/* Buffers pending completion */
 
-	u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES]; /* dword ring offsets of most recent frame swaps */
+	u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES];	/* dword ring offsets of most recent frame swaps */
 
 	unsigned int fb_bpp;
 	unsigned int front_offset, front_pitch;
@@ -104,48 +104,49 @@ typedef struct drm_mach64_private {
 	drm_local_map_t *fb;
 	drm_local_map_t *mmio;
 	drm_local_map_t *ring_map;
-	drm_local_map_t *dev_buffers; /* this is a pointer to a structure in dev */
+	drm_local_map_t *dev_buffers;	/* this is a pointer to a structure in dev */
 	drm_local_map_t *agp_textures;
 } drm_mach64_private_t;
 
 				/* mach64_dma.c */
-extern int mach64_dma_init( DRM_IOCTL_ARGS );
-extern int mach64_dma_idle( DRM_IOCTL_ARGS );
-extern int mach64_dma_flush( DRM_IOCTL_ARGS );
-extern int mach64_engine_reset( DRM_IOCTL_ARGS );
-extern int mach64_dma_buffers( DRM_IOCTL_ARGS );
-extern void mach64_driver_pretakedown(drm_device_t *dev);
-
-extern int mach64_init_freelist( drm_device_t *dev );
-extern void mach64_destroy_freelist( drm_device_t *dev );
-extern drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv );
-
-extern int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv,
-				    int entries );
-extern int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv );
-extern int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n );
-extern int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv );
-extern int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv );
-extern void mach64_dump_engine_info( drm_mach64_private_t *dev_priv );
-extern void mach64_dump_ring_info( drm_mach64_private_t *dev_priv );
-extern int mach64_do_engine_reset( drm_mach64_private_t *dev_priv );
-
-extern int mach64_do_dma_idle( drm_mach64_private_t *dev_priv );
-extern int mach64_do_dma_flush( drm_mach64_private_t *dev_priv );
-extern int mach64_do_cleanup_dma( drm_device_t *dev );
+extern int mach64_dma_init(DRM_IOCTL_ARGS);
+extern int mach64_dma_idle(DRM_IOCTL_ARGS);
+extern int mach64_dma_flush(DRM_IOCTL_ARGS);
+extern int mach64_engine_reset(DRM_IOCTL_ARGS);
+extern int mach64_dma_buffers(DRM_IOCTL_ARGS);
+extern void mach64_driver_pretakedown(drm_device_t * dev);
+
+extern int mach64_init_freelist(drm_device_t * dev);
+extern void mach64_destroy_freelist(drm_device_t * dev);
+extern drm_buf_t *mach64_freelist_get(drm_mach64_private_t * dev_priv);
+
+extern int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv,
+				   int entries);
+extern int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv);
+extern int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n);
+extern int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv);
+extern int mach64_do_release_used_buffers(drm_mach64_private_t * dev_priv);
+extern void mach64_dump_engine_info(drm_mach64_private_t * dev_priv);
+extern void mach64_dump_ring_info(drm_mach64_private_t * dev_priv);
+extern int mach64_do_engine_reset(drm_mach64_private_t * dev_priv);
+
+extern int mach64_do_dma_idle(drm_mach64_private_t * dev_priv);
+extern int mach64_do_dma_flush(drm_mach64_private_t * dev_priv);
+extern int mach64_do_cleanup_dma(drm_device_t * dev);
 
 				/* mach64_state.c */
-extern int mach64_dma_clear( DRM_IOCTL_ARGS );
-extern int mach64_dma_swap( DRM_IOCTL_ARGS );
-extern int mach64_dma_vertex( DRM_IOCTL_ARGS );
-extern int mach64_dma_blit( DRM_IOCTL_ARGS );
-extern int mach64_get_param( DRM_IOCTL_ARGS );
-extern int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
-
-extern irqreturn_t mach64_driver_irq_handler( DRM_IRQ_ARGS );
-extern void mach64_driver_irq_preinstall( drm_device_t *dev );
-extern void mach64_driver_irq_postinstall( drm_device_t *dev );
-extern void mach64_driver_irq_uninstall( drm_device_t *dev );
+extern int mach64_dma_clear(DRM_IOCTL_ARGS);
+extern int mach64_dma_swap(DRM_IOCTL_ARGS);
+extern int mach64_dma_vertex(DRM_IOCTL_ARGS);
+extern int mach64_dma_blit(DRM_IOCTL_ARGS);
+extern int mach64_get_param(DRM_IOCTL_ARGS);
+extern int mach64_driver_vblank_wait(drm_device_t * dev,
+				     unsigned int *sequence);
+
+extern irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS);
+extern void mach64_driver_irq_preinstall(drm_device_t * dev);
+extern void mach64_driver_irq_postinstall(drm_device_t * dev);
+extern void mach64_driver_irq_uninstall(drm_device_t * dev);
 
 /* ================================================================
  * Registers
@@ -155,7 +156,6 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
 #define MACH64_AGP_CNTL				0x014c
 #define MACH64_ALPHA_TST_CNTL			0x0550
 
-
 #define MACH64_DSP_CONFIG 			0x0420
 #define MACH64_DSP_ON_OFF 			0x0424
 #define MACH64_EXT_MEM_CNTL 			0x04ac
@@ -165,7 +165,6 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
 #define MACH64_MEM_BUF_CNTL 			0x042c
 #define MACH64_MEM_CNTL 			0x04b0
 
-
 #define MACH64_BM_ADDR				0x0648
 #define MACH64_BM_COMMAND			0x0188
 #define MACH64_BM_DATA				0x0648
@@ -390,17 +389,17 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
 #	define MACH64_CRTC_VBLANK_INT			(1 << 2)
 #	define MACH64_CRTC_VLINE_INT_EN			(1 << 3)
 #	define MACH64_CRTC_VLINE_INT			(1 << 4)
-#	define MACH64_CRTC_VLINE_SYNC			(1 << 5) /* 0=even, 1=odd */
-#	define MACH64_CRTC_FRAME			(1 << 6) /* 0=even, 1=odd */
+#	define MACH64_CRTC_VLINE_SYNC			(1 << 5)	/* 0=even, 1=odd */
+#	define MACH64_CRTC_FRAME			(1 << 6)	/* 0=even, 1=odd */
 #	define MACH64_CRTC_SNAPSHOT_INT_EN		(1 << 7)
 #	define MACH64_CRTC_SNAPSHOT_INT			(1 << 8)
 #	define MACH64_CRTC_I2C_INT_EN			(1 << 9)
 #	define MACH64_CRTC_I2C_INT			(1 << 10)
-#	define MACH64_CRTC2_VBLANK			(1 << 11) /* LT Pro */
-#	define MACH64_CRTC2_VBLANK_INT_EN		(1 << 12) /* LT Pro */
-#	define MACH64_CRTC2_VBLANK_INT			(1 << 13) /* LT Pro */
-#	define MACH64_CRTC2_VLINE_INT_EN		(1 << 14) /* LT Pro */
-#	define MACH64_CRTC2_VLINE_INT			(1 << 15) /* LT Pro */
+#	define MACH64_CRTC2_VBLANK			(1 << 11)	/* LT Pro */
+#	define MACH64_CRTC2_VBLANK_INT_EN		(1 << 12)	/* LT Pro */
+#	define MACH64_CRTC2_VBLANK_INT			(1 << 13)	/* LT Pro */
+#	define MACH64_CRTC2_VLINE_INT_EN		(1 << 14)	/* LT Pro */
+#	define MACH64_CRTC2_VLINE_INT			(1 << 15)	/* LT Pro */
 #	define MACH64_CRTC_CAPBUF0_INT_EN		(1 << 16)
 #	define MACH64_CRTC_CAPBUF0_INT			(1 << 17)
 #	define MACH64_CRTC_CAPBUF1_INT_EN		(1 << 18)
@@ -413,9 +412,9 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
 #	define MACH64_CRTC_BUSMASTER_EOL_INT		(1 << 25)
 #	define MACH64_CRTC_GP_INT_EN			(1 << 26)
 #	define MACH64_CRTC_GP_INT			(1 << 27)
-#	define MACH64_CRTC2_VLINE_SYNC			(1 << 28) /* LT Pro */  /* 0=even, 1=odd */
-#	define MACH64_CRTC_SNAPSHOT2_INT_EN		(1 << 29) /* LT Pro */
-#	define MACH64_CRTC_SNAPSHOT2_INT		(1 << 30) /* LT Pro */
+#	define MACH64_CRTC2_VLINE_SYNC			(1 << 28) /* LT Pro */	/* 0=even, 1=odd */
+#	define MACH64_CRTC_SNAPSHOT2_INT_EN		(1 << 29)	/* LT Pro */
+#	define MACH64_CRTC_SNAPSHOT2_INT		(1 << 30)	/* LT Pro */
 #	define MACH64_CRTC_VBLANK2_INT			(1 << 31)
 #	define MACH64_CRTC_INT_ENS				\
 		(						\
@@ -468,7 +467,6 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
 #define MACH64_READ(reg)	DRM_READ32(dev_priv->mmio, (reg) )
 #define MACH64_WRITE(reg,val)	DRM_WRITE32(dev_priv->mmio, (reg), (val) )
 
-
 #define DWMREG0		0x0400
 #define DWMREG0_END	0x07ff
 #define DWMREG1		0x0000
@@ -492,254 +490,246 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
  */
 
 /* DMA descriptor field indices:
- * The descriptor fields are loaded into the read-only 
+ * The descriptor fields are loaded into the read-only
  * BM_* system bus master registers during a bus-master operation
  */
-#define MACH64_DMA_FRAME_BUF_OFFSET	0        /* BM_FRAME_BUF_OFFSET */
-#define MACH64_DMA_SYS_MEM_ADDR		1        /* BM_SYSTEM_MEM_ADDR */
-#define MACH64_DMA_COMMAND		2        /* BM_COMMAND */
-#define MACH64_DMA_RESERVED		3        /* BM_STATUS */
+#define MACH64_DMA_FRAME_BUF_OFFSET	0	/* BM_FRAME_BUF_OFFSET */
+#define MACH64_DMA_SYS_MEM_ADDR		1	/* BM_SYSTEM_MEM_ADDR */
+#define MACH64_DMA_COMMAND		2	/* BM_COMMAND */
+#define MACH64_DMA_RESERVED		3	/* BM_STATUS */
 
 /* BM_COMMAND descriptor field flags */
-#define MACH64_DMA_HOLD_OFFSET		(1<<30)  /* Don't increment DMA_FRAME_BUF_OFFSET */
-#define MACH64_DMA_EOL			(1<<31)  /* End of descriptor list flag */
-
-#define MACH64_DMA_CHUNKSIZE	        0x1000   /* 4kB per DMA descriptor */
-#define MACH64_APERTURE_OFFSET	        0x7ff800 /* frame-buffer offset for gui-masters */
+#define MACH64_DMA_HOLD_OFFSET		(1<<30)	/* Don't increment DMA_FRAME_BUF_OFFSET */
+#define MACH64_DMA_EOL			(1<<31)	/* End of descriptor list flag */
 
+#define MACH64_DMA_CHUNKSIZE	        0x1000	/* 4kB per DMA descriptor */
+#define MACH64_APERTURE_OFFSET	        0x7ff800	/* frame-buffer offset for gui-masters */
 
 /* ================================================================
  * Misc helper macros
  */
 
-static __inline__ void mach64_set_dma_eol( volatile u32 * addr )
+static __inline__ void mach64_set_dma_eol(volatile u32 * addr)
 {
 #if defined(__i386__)
 	int nr = 31;
-	
+
 	/* Taken from include/asm-i386/bitops.h linux header */
-        __asm__ __volatile__( "lock;"
-                "btsl %1,%0"
-                :"=m" (*addr)
-                :"Ir" (nr));
+	__asm__ __volatile__("lock;" "btsl %1,%0":"=m"(*addr)
+			     :"Ir"(nr));
 #elif defined(__powerpc__)
 	u32 old;
-	u32 mask = cpu_to_le32( MACH64_DMA_EOL );
+	u32 mask = cpu_to_le32(MACH64_DMA_EOL);
 
 	/* Taken from the include/asm-ppc/bitops.h linux header */
 	__asm__ __volatile__("\n\
 1:	lwarx	%0,0,%3 \n\
 	or	%0,%0,%2 \n\
 	stwcx.	%0,0,%3 \n\
-	bne-	1b"
-	: "=&r" (old), "=m" (*addr)
-	: "r" (mask), "r" (addr), "m" (*addr)
-	: "cc");
+	bne-	1b":"=&r"(old), "=m"(*addr)
+			     :"r"(mask), "r"(addr), "m"(*addr)
+			     :"cc");
 #elif defined(__alpha__)
 	u32 temp;
 	u32 mask = MACH64_DMA_EOL;
 
 	/* Taken from the include/asm-alpha/bitops.h linux header */
-	__asm__ __volatile__(
-	"1:	ldl_l %0,%3\n"
-	"	bis %0,%2,%0\n"
-	"	stl_c %0,%1\n"
-	"	beq %0,2f\n"
-	".subsection 2\n"
-	"2:	br 1b\n"
-	".previous"
-	:"=&r" (temp), "=m" (*addr)
-	:"Ir" (mask), "m" (*addr));
+	__asm__ __volatile__("1:	ldl_l %0,%3\n"
+			     "	bis %0,%2,%0\n"
+			     "	stl_c %0,%1\n"
+			     "	beq %0,2f\n"
+			     ".subsection 2\n"
+			     "2:	br 1b\n"
+			     ".previous":"=&r"(temp), "=m"(*addr)
+			     :"Ir"(mask), "m"(*addr));
 #else
-	u32 mask = cpu_to_le32( MACH64_DMA_EOL );
+	u32 mask = cpu_to_le32(MACH64_DMA_EOL);
 
 	*addr |= mask;
 #endif
 }
 
-static __inline__ void mach64_clear_dma_eol( volatile u32 * addr )
+static __inline__ void mach64_clear_dma_eol(volatile u32 * addr)
 {
 #if defined(__i386__)
 	int nr = 31;
-	
+
 	/* Taken from include/asm-i386/bitops.h linux header */
-        __asm__ __volatile__( "lock;"
-                "btrl %1,%0"
-                :"=m" (*addr)
-                :"Ir" (nr));
+	__asm__ __volatile__("lock;" "btrl %1,%0":"=m"(*addr)
+			     :"Ir"(nr));
 #elif defined(__powerpc__)
 	u32 old;
-	u32 mask = cpu_to_le32( MACH64_DMA_EOL );
+	u32 mask = cpu_to_le32(MACH64_DMA_EOL);
 
 	/* Taken from the include/asm-ppc/bitops.h linux header */
 	__asm__ __volatile__("\n\
 1:	lwarx	%0,0,%3 \n\
 	andc	%0,%0,%2 \n\
 	stwcx.	%0,0,%3 \n\
-	bne-	1b"
-	: "=&r" (old), "=m" (*addr)
-	: "r" (mask), "r" (addr), "m" (*addr)
-	: "cc");
+	bne-	1b":"=&r"(old), "=m"(*addr)
+			     :"r"(mask), "r"(addr), "m"(*addr)
+			     :"cc");
 #elif defined(__alpha__)
 	u32 temp;
 	u32 mask = ~MACH64_DMA_EOL;
 
 	/* Taken from the include/asm-alpha/bitops.h linux header */
-	__asm__ __volatile__(
-	"1:	ldl_l %0,%3\n"
-	"	and %0,%2,%0\n"
-	"	stl_c %0,%1\n"
-	"	beq %0,2f\n"
-	".subsection 2\n"
-	"2:	br 1b\n"
-	".previous"
-	:"=&r" (temp), "=m" (*addr)
-	:"Ir" (mask), "m" (*addr));
+	__asm__ __volatile__("1:	ldl_l %0,%3\n"
+			     "	and %0,%2,%0\n"
+			     "	stl_c %0,%1\n"
+			     "	beq %0,2f\n"
+			     ".subsection 2\n"
+			     "2:	br 1b\n"
+			     ".previous":"=&r"(temp), "=m"(*addr)
+			     :"Ir"(mask), "m"(*addr));
 #else
-	u32 mask = cpu_to_le32( ~MACH64_DMA_EOL );
+	u32 mask = cpu_to_le32(~MACH64_DMA_EOL);
 
 	*addr &= mask;
 #endif
 }
 
-static __inline__ void mach64_ring_start( drm_mach64_private_t *dev_priv )
+static __inline__ void mach64_ring_start(drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
-	
-	DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
-		   __FUNCTION__, 
-		   ring->head_addr, ring->head, ring->tail, ring->space );
 
-	if ( mach64_do_wait_for_idle( dev_priv ) < 0 ) {
-		mach64_do_engine_reset( dev_priv );
+	DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
+		  __FUNCTION__,
+		  ring->head_addr, ring->head, ring->tail, ring->space);
+
+	if (mach64_do_wait_for_idle(dev_priv) < 0) {
+		mach64_do_engine_reset(dev_priv);
 	}
 
-	if (dev_priv->driver_mode != MACH64_MODE_MMIO ) {
+	if (dev_priv->driver_mode != MACH64_MODE_MMIO) {
 		/* enable bus mastering and block 1 registers */
-		MACH64_WRITE( MACH64_BUS_CNTL, 
-			      ( MACH64_READ(MACH64_BUS_CNTL) & 	~MACH64_BUS_MASTER_DIS ) 
-			      | MACH64_BUS_EXT_REG_EN );
-		mach64_do_wait_for_idle( dev_priv );
+		MACH64_WRITE(MACH64_BUS_CNTL,
+			     (MACH64_READ(MACH64_BUS_CNTL) &
+			      ~MACH64_BUS_MASTER_DIS)
+			     | MACH64_BUS_EXT_REG_EN);
+		mach64_do_wait_for_idle(dev_priv);
 	}
-	
+
 	/* reset descriptor table ring head */
-	MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, 
-		      ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB );
-	
+	MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
+		     ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
+
 	dev_priv->ring_running = 1;
 }
 
-static __inline__ void mach64_ring_resume( drm_mach64_private_t *dev_priv, 
-					   drm_mach64_descriptor_ring_t *ring )
+static __inline__ void mach64_ring_resume(drm_mach64_private_t * dev_priv,
+					  drm_mach64_descriptor_ring_t * ring)
 {
-	DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
-		   __FUNCTION__, 
-		   ring->head_addr, ring->head, ring->tail, ring->space );
+	DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
+		  __FUNCTION__,
+		  ring->head_addr, ring->head, ring->tail, ring->space);
 
 	/* reset descriptor table ring head */
-	MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, 
-		      ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB );
+	MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
+		     ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
 
-	if ( dev_priv->driver_mode == MACH64_MODE_MMIO ) {
-		mach64_do_dispatch_pseudo_dma( dev_priv );
+	if (dev_priv->driver_mode == MACH64_MODE_MMIO) {
+		mach64_do_dispatch_pseudo_dma(dev_priv);
 	} else {
 		/* enable GUI bus mastering, and sync the bus master to the GUI */
-		MACH64_WRITE( MACH64_SRC_CNTL, 
-			      MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
-			      MACH64_SRC_BM_OP_SYSTEM_TO_REG );
+		MACH64_WRITE(MACH64_SRC_CNTL,
+			     MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
+			     MACH64_SRC_BM_OP_SYSTEM_TO_REG);
 
 		/* kick off the transfer */
-		MACH64_WRITE( MACH64_DST_HEIGHT_WIDTH, 0 );
-		if ( dev_priv->driver_mode == MACH64_MODE_DMA_SYNC ) {
-			if ( (mach64_do_wait_for_idle( dev_priv )) < 0 ) {
-				DRM_ERROR( "%s: idle failed, resetting engine\n", 
-					   __FUNCTION__);
-				mach64_dump_engine_info( dev_priv );
-				mach64_do_engine_reset( dev_priv );
+		MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0);
+		if (dev_priv->driver_mode == MACH64_MODE_DMA_SYNC) {
+			if ((mach64_do_wait_for_idle(dev_priv)) < 0) {
+				DRM_ERROR("%s: idle failed, resetting engine\n",
+					  __FUNCTION__);
+				mach64_dump_engine_info(dev_priv);
+				mach64_do_engine_reset(dev_priv);
 				return;
 			}
-			mach64_do_release_used_buffers( dev_priv );
+			mach64_do_release_used_buffers(dev_priv);
 		}
 	}
 }
 
-static __inline__ void mach64_ring_tick( drm_mach64_private_t *dev_priv, 
-					 drm_mach64_descriptor_ring_t *ring )
+static __inline__ void mach64_ring_tick(drm_mach64_private_t * dev_priv,
+					drm_mach64_descriptor_ring_t * ring)
 {
-	DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
-		   __FUNCTION__, 
-		   ring->head_addr, ring->head, ring->tail, ring->space );
-
-	if ( !dev_priv->ring_running ) {
-		mach64_ring_start( dev_priv );
-		
-		if ( ring->head != ring->tail ) {
-			mach64_ring_resume( dev_priv, ring );
+	DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
+		  __FUNCTION__,
+		  ring->head_addr, ring->head, ring->tail, ring->space);
+
+	if (!dev_priv->ring_running) {
+		mach64_ring_start(dev_priv);
+
+		if (ring->head != ring->tail) {
+			mach64_ring_resume(dev_priv, ring);
 		}
 	} else {
-		/* GUI_ACTIVE must be read before BM_GUI_TABLE to 
-		 * correctly determine the ring head 
+		/* GUI_ACTIVE must be read before BM_GUI_TABLE to
+		 * correctly determine the ring head
 		 */
-		int gui_active = MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE;
-		
+		int gui_active =
+		    MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE;
+
 		ring->head_addr = MACH64_READ(MACH64_BM_GUI_TABLE) & 0xfffffff0;
-		
-		if ( gui_active ) {
-			/* If not idle, BM_GUI_TABLE points one descriptor 
-			 * past the current head 
+
+		if (gui_active) {
+			/* If not idle, BM_GUI_TABLE points one descriptor
+			 * past the current head
 			 */
-			if ( ring->head_addr == ring->start_addr ) {
+			if (ring->head_addr == ring->start_addr) {
 				ring->head_addr += ring->size;
 			}
 			ring->head_addr -= 4 * sizeof(u32);
 		}
 
-		if( ring->head_addr < ring->start_addr || 
-		    ring->head_addr >= ring->start_addr + ring->size ) {
-			DRM_ERROR( "bad ring head address: 0x%08x\n", ring->head_addr );
-			mach64_dump_ring_info( dev_priv );
-			mach64_do_engine_reset( dev_priv );
+		if (ring->head_addr < ring->start_addr ||
+		    ring->head_addr >= ring->start_addr + ring->size) {
+			DRM_ERROR("bad ring head address: 0x%08x\n",
+				  ring->head_addr);
+			mach64_dump_ring_info(dev_priv);
+			mach64_do_engine_reset(dev_priv);
 			return;
 		}
-	
+
 		ring->head = (ring->head_addr - ring->start_addr) / sizeof(u32);
-		
-		if ( !gui_active && ring->head != ring->tail ) {
-			mach64_ring_resume( dev_priv, ring );
+
+		if (!gui_active && ring->head != ring->tail) {
+			mach64_ring_resume(dev_priv, ring);
 		}
 	}
 }
 
-static __inline__ void mach64_ring_stop( drm_mach64_private_t *dev_priv )
+static __inline__ void mach64_ring_stop(drm_mach64_private_t * dev_priv)
 {
-	DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
-		   __FUNCTION__, 
-		   dev_priv->ring.head_addr, dev_priv->ring.head, 
-		   dev_priv->ring.tail, dev_priv->ring.space );
+	DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
+		  __FUNCTION__,
+		  dev_priv->ring.head_addr, dev_priv->ring.head,
+		  dev_priv->ring.tail, dev_priv->ring.space);
 
 	/* restore previous SRC_CNTL to disable busmastering */
-	mach64_do_wait_for_fifo( dev_priv, 1 );
-	MACH64_WRITE( MACH64_SRC_CNTL, 0 );
-
-	/* disable busmastering but keep the block 1 registers enabled */ 
-	mach64_do_wait_for_idle( dev_priv );
-	MACH64_WRITE( MACH64_BUS_CNTL, MACH64_READ( MACH64_BUS_CNTL ) 
-		      | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN );
-		
+	mach64_do_wait_for_fifo(dev_priv, 1);
+	MACH64_WRITE(MACH64_SRC_CNTL, 0);
+
+	/* disable busmastering but keep the block 1 registers enabled */
+	mach64_do_wait_for_idle(dev_priv);
+	MACH64_WRITE(MACH64_BUS_CNTL, MACH64_READ(MACH64_BUS_CNTL)
+		     | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN);
+
 	dev_priv->ring_running = 0;
 }
 
 static __inline__ void
-mach64_update_ring_snapshot( drm_mach64_private_t *dev_priv )
+mach64_update_ring_snapshot(drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-	
-	mach64_ring_tick( dev_priv, ring );
+	DRM_DEBUG("%s\n", __FUNCTION__);
+
+	mach64_ring_tick(dev_priv, ring);
 
 	ring->space = (ring->head - ring->tail) * sizeof(u32);
-	if ( ring->space <= 0 ) {
+	if (ring->space <= 0) {
 		ring->space += ring->size;
 	}
 }
@@ -797,7 +787,6 @@ do {									\
 	mach64_ring_tick( dev_priv, &(dev_priv)->ring );		\
 } while (0)
 
-
 /* ================================================================
  * DMA macros
  */
@@ -816,9 +805,10 @@ do {									\
 
 #define GETRINGOFFSET() (_entry->ring_ofs)
 
-static __inline__ int mach64_find_pending_buf_entry ( drm_mach64_private_t *dev_priv, 
-						      drm_mach64_freelist_t **entry, 
-						      drm_buf_t *buf )
+static __inline__ int mach64_find_pending_buf_entry(drm_mach64_private_t *
+						    dev_priv,
+						    drm_mach64_freelist_t **
+						    entry, drm_buf_t * buf)
 {
 	struct list_head *ptr;
 #if MACH64_EXTRA_CHECKING
@@ -1050,4 +1040,4 @@ do {											 \
 	ADVANCE_RING();									 \
 } while(0)
 
-#endif /* __MACH64_DRV_H__ */
+#endif				/* __MACH64_DRV_H__ */
diff --git a/shared-core/mach64_irq.c b/shared-core/mach64_irq.c
index 966c3c10..b8853c1c 100644
--- a/shared-core/mach64_irq.c
+++ b/shared-core/mach64_irq.c
@@ -39,47 +39,48 @@
 #include "mach64_drm.h"
 #include "mach64_drv.h"
 
-irqreturn_t mach64_driver_irq_handler( DRM_IRQ_ARGS )
+irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS)
 {
 	drm_device_t *dev = (drm_device_t *) arg;
-	drm_mach64_private_t *dev_priv = 
-	   (drm_mach64_private_t *)dev->dev_private;
+	drm_mach64_private_t *dev_priv =
+	    (drm_mach64_private_t *) dev->dev_private;
 	int status;
 
-	status = MACH64_READ( MACH64_CRTC_INT_CNTL );
+	status = MACH64_READ(MACH64_CRTC_INT_CNTL);
 
 	/* VBLANK interrupt */
 	if (status & MACH64_CRTC_VBLANK_INT) {
-	    /* Mask off all interrupt ack bits before setting the ack bit, since
-	     * there may be other handlers outside the DRM.  
-	     *
-	     * NOTE: On mach64, you need to keep the enable bits set when doing
-	     * the ack, despite what the docs say about not acking and enabling
-	     * in a single write.
-	     */
-	    MACH64_WRITE( MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_INT_ACKS)
-			  | MACH64_CRTC_VBLANK_INT );
-
-	    atomic_inc(&dev->vbl_received);
-	    DRM_WAKEUP(&dev->vbl_queue);
-	    drm_vbl_send_signals( dev );
-            return IRQ_HANDLED;
+		/* Mask off all interrupt ack bits before setting the ack bit, since
+		 * there may be other handlers outside the DRM.
+		 *
+		 * NOTE: On mach64, you need to keep the enable bits set when doing
+		 * the ack, despite what the docs say about not acking and enabling
+		 * in a single write.
+		 */
+		MACH64_WRITE(MACH64_CRTC_INT_CNTL,
+			     (status & ~MACH64_CRTC_INT_ACKS)
+			     | MACH64_CRTC_VBLANK_INT);
+
+		atomic_inc(&dev->vbl_received);
+		DRM_WAKEUP(&dev->vbl_queue);
+		drm_vbl_send_signals(dev);
+		return IRQ_HANDLED;
 	}
 	return IRQ_NONE;
 }
 
-int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
+int mach64_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
 {
 	unsigned int cur_vblank;
 	int ret = 0;
 
 	/* Assume that the user has missed the current sequence number
 	 * by about a day rather than she wants to wait for years
-	 * using vertical blanks... 
+	 * using vertical blanks...
 	 */
-	DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, 
-		     ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
-			 - *sequence ) <= (1<<23) ) );
+	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
+		    (((cur_vblank = atomic_read(&dev->vbl_received))
+		      - *sequence) <= (1 << 23)));
 
 	*sequence = cur_vblank;
 
@@ -88,42 +89,47 @@ int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
 
 /* drm_dma.h hooks
 */
-void mach64_driver_irq_preinstall( drm_device_t *dev ) {
+void mach64_driver_irq_preinstall(drm_device_t * dev)
+{
 	drm_mach64_private_t *dev_priv =
-		(drm_mach64_private_t *)dev->dev_private;
+	    (drm_mach64_private_t *) dev->dev_private;
 
-	u32 status = MACH64_READ( MACH64_CRTC_INT_CNTL );
+	u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL);
 
-	DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status );
+	DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status);
 
- 	/* Disable and clear VBLANK interrupt */
-	MACH64_WRITE( MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN) 
-		      | MACH64_CRTC_VBLANK_INT );
+	/* Disable and clear VBLANK interrupt */
+	MACH64_WRITE(MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN)
+		     | MACH64_CRTC_VBLANK_INT);
 }
 
-void mach64_driver_irq_postinstall( drm_device_t *dev ) {
+void mach64_driver_irq_postinstall(drm_device_t * dev)
+{
 	drm_mach64_private_t *dev_priv =
-		(drm_mach64_private_t *)dev->dev_private;
+	    (drm_mach64_private_t *) dev->dev_private;
 
 	/* Turn on VBLANK interrupt */
-   	MACH64_WRITE( MACH64_CRTC_INT_CNTL, MACH64_READ( MACH64_CRTC_INT_CNTL )
-		      | MACH64_CRTC_VBLANK_INT_EN );
+	MACH64_WRITE(MACH64_CRTC_INT_CNTL, MACH64_READ(MACH64_CRTC_INT_CNTL)
+		     | MACH64_CRTC_VBLANK_INT_EN);
 
-	DRM_DEBUG("after install CRTC_INT_CTNL: 0x%08x\n", MACH64_READ( MACH64_CRTC_INT_CNTL ));
+	DRM_DEBUG("after install CRTC_INT_CTNL: 0x%08x\n",
+		  MACH64_READ(MACH64_CRTC_INT_CNTL));
 
 }
 
-void mach64_driver_irq_uninstall( drm_device_t *dev ) {
+void mach64_driver_irq_uninstall(drm_device_t * dev)
+{
 	drm_mach64_private_t *dev_priv =
-		(drm_mach64_private_t *)dev->dev_private;
-	if ( !dev_priv )
+	    (drm_mach64_private_t *) dev->dev_private;
+	if (!dev_priv)
 		return;
 
 	/* Disable and clear VBLANK interrupt */
-	MACH64_WRITE( MACH64_CRTC_INT_CNTL, 
-		      (MACH64_READ( MACH64_CRTC_INT_CNTL ) & ~MACH64_CRTC_VBLANK_INT_EN) 
-		      | MACH64_CRTC_VBLANK_INT );
+	MACH64_WRITE(MACH64_CRTC_INT_CNTL,
+		     (MACH64_READ(MACH64_CRTC_INT_CNTL) &
+		      ~MACH64_CRTC_VBLANK_INT_EN)
+		     | MACH64_CRTC_VBLANK_INT);
 
-	DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n", 
-		  MACH64_READ( MACH64_CRTC_INT_CNTL ));
+	DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n",
+		  MACH64_READ(MACH64_CRTC_INT_CNTL));
 }
diff --git a/shared-core/mach64_state.c b/shared-core/mach64_state.c
index 127f67d2..2d3c4f61 100644
--- a/shared-core/mach64_state.c
+++ b/shared-core/mach64_state.c
@@ -34,28 +34,29 @@
 #include "mach64_drm.h"
 #include "mach64_drv.h"
 
-
 /* ================================================================
  * DMA hardware state programming functions
  */
 
-static void mach64_print_dirty( const char *msg, unsigned int flags )
+static void mach64_print_dirty(const char *msg, unsigned int flags)
 {
-	DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n",
-		msg,
-		flags,
-		(flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " : "",
-		(flags & MACH64_UPLOAD_Z_ALPHA_CNTL)  ? "z_alpha_cntl, " : "",
-		(flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " : "",
-		(flags & MACH64_UPLOAD_DP_FOG_CLR)    ? "dp_fog_clr, " : "",
-		(flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " : "",
-		(flags & MACH64_UPLOAD_DP_PIX_WIDTH)  ? "dp_pix_width, " : "",
-		(flags & MACH64_UPLOAD_SETUP_CNTL)    ? "setup_cntl, " : "",
-		(flags & MACH64_UPLOAD_MISC)          ? "misc, " : "",
-		(flags & MACH64_UPLOAD_TEXTURE)       ? "texture, " : "",
-		(flags & MACH64_UPLOAD_TEX0IMAGE)     ? "tex0 image, " : "",
-		(flags & MACH64_UPLOAD_TEX1IMAGE)     ? "tex1 image, " : "",
-		(flags & MACH64_UPLOAD_CLIPRECTS)     ? "cliprects, " : "" );
+	DRM_DEBUG("%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n",
+		  msg,
+		  flags,
+		  (flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " :
+		  "",
+		  (flags & MACH64_UPLOAD_Z_ALPHA_CNTL) ? "z_alpha_cntl, " : "",
+		  (flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " :
+		  "", (flags & MACH64_UPLOAD_DP_FOG_CLR) ? "dp_fog_clr, " : "",
+		  (flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " :
+		  "",
+		  (flags & MACH64_UPLOAD_DP_PIX_WIDTH) ? "dp_pix_width, " : "",
+		  (flags & MACH64_UPLOAD_SETUP_CNTL) ? "setup_cntl, " : "",
+		  (flags & MACH64_UPLOAD_MISC) ? "misc, " : "",
+		  (flags & MACH64_UPLOAD_TEXTURE) ? "texture, " : "",
+		  (flags & MACH64_UPLOAD_TEX0IMAGE) ? "tex0 image, " : "",
+		  (flags & MACH64_UPLOAD_TEX1IMAGE) ? "tex1 image, " : "",
+		  (flags & MACH64_UPLOAD_CLIPRECTS) ? "cliprects, " : "");
 }
 
 /* Mach64 doesn't have hardware cliprects, just one hardware scissor,
@@ -64,8 +65,8 @@ static void mach64_print_dirty( const char *msg, unsigned int flags )
 /* This function returns 0 on success, 1 for no intersection, and
  * negative for an error
  */
-static int mach64_emit_cliprect( DRMFILE filp, drm_mach64_private_t *dev_priv,
-				 drm_clip_rect_t *box )
+static int mach64_emit_cliprect(DRMFILE filp, drm_mach64_private_t * dev_priv,
+				drm_clip_rect_t * box)
 {
 	u32 sc_left_right, sc_top_bottom;
 	drm_clip_rect_t scissor;
@@ -73,7 +74,7 @@ static int mach64_emit_cliprect( DRMFILE filp, drm_mach64_private_t *dev_priv,
 	drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
 	DMALOCALS;
 
-	DRM_DEBUG( "%s: box=%p\n", __FUNCTION__, box );
+	DRM_DEBUG("%s: box=%p\n", __FUNCTION__, box);
 
 	/* Get GL scissor */
 	/* FIXME: store scissor in SAREA as a cliprect instead of in
@@ -85,28 +86,35 @@ static int mach64_emit_cliprect( DRMFILE filp, drm_mach64_private_t *dev_priv,
 	scissor.y2 = (regs->sc_top_bottom & 0xffff0000) >> 16;
 
 	/* Intersect GL scissor with cliprect */
-	if ( box->x1 > scissor.x1 ) scissor.x1 = box->x1;
-	if ( box->y1 > scissor.y1 ) scissor.y1 = box->y1;
-	if ( box->x2 < scissor.x2 ) scissor.x2 = box->x2;
-	if ( box->y2 < scissor.y2 ) scissor.y2 = box->y2;
-	 /* positive return means skip */
-	if ( scissor.x1 >= scissor.x2 ) return 1;
-	if ( scissor.y1 >= scissor.y2 ) return 1;
-
-	DMAGETPTR( filp, dev_priv, 2 ); /* returns on failure to get buffer */
-
-	sc_left_right = ( (scissor.x1 << 0) | (scissor.x2 << 16) );
-	sc_top_bottom = ( (scissor.y1 << 0) | (scissor.y2 << 16) );
-
-	DMAOUTREG( MACH64_SC_LEFT_RIGHT, sc_left_right );
-	DMAOUTREG( MACH64_SC_TOP_BOTTOM, sc_top_bottom );
-
-	DMAADVANCE( dev_priv, 1 );
+	if (box->x1 > scissor.x1)
+		scissor.x1 = box->x1;
+	if (box->y1 > scissor.y1)
+		scissor.y1 = box->y1;
+	if (box->x2 < scissor.x2)
+		scissor.x2 = box->x2;
+	if (box->y2 < scissor.y2)
+		scissor.y2 = box->y2;
+	/* positive return means skip */
+	if (scissor.x1 >= scissor.x2)
+		return 1;
+	if (scissor.y1 >= scissor.y2)
+		return 1;
+
+	DMAGETPTR(filp, dev_priv, 2);	/* returns on failure to get buffer */
+
+	sc_left_right = ((scissor.x1 << 0) | (scissor.x2 << 16));
+	sc_top_bottom = ((scissor.y1 << 0) | (scissor.y2 << 16));
+
+	DMAOUTREG(MACH64_SC_LEFT_RIGHT, sc_left_right);
+	DMAOUTREG(MACH64_SC_TOP_BOTTOM, sc_top_bottom);
+
+	DMAADVANCE(dev_priv, 1);
 
 	return 0;
 }
 
-static __inline__ int mach64_emit_state( DRMFILE filp, drm_mach64_private_t *dev_priv )
+static __inline__ int mach64_emit_state(DRMFILE filp,
+					drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
@@ -114,65 +122,65 @@ static __inline__ int mach64_emit_state( DRMFILE filp, drm_mach64_private_t *dev
 	u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2);
 	DMALOCALS;
 
-	if ( MACH64_VERBOSE ) {
-		mach64_print_dirty( __FUNCTION__, dirty );
+	if (MACH64_VERBOSE) {
+		mach64_print_dirty(__FUNCTION__, dirty);
 	} else {
-		DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
+		DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty);
 	}
 
-	DMAGETPTR( filp, dev_priv, 17 ); /* returns on failure to get buffer */
+	DMAGETPTR(filp, dev_priv, 17);	/* returns on failure to get buffer */
 
-	if ( dirty & MACH64_UPLOAD_MISC ) {
-		DMAOUTREG( MACH64_DP_MIX, regs->dp_mix );
-		DMAOUTREG( MACH64_DP_SRC, regs->dp_src );
-		DMAOUTREG( MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl );
-		DMAOUTREG( MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl );
+	if (dirty & MACH64_UPLOAD_MISC) {
+		DMAOUTREG(MACH64_DP_MIX, regs->dp_mix);
+		DMAOUTREG(MACH64_DP_SRC, regs->dp_src);
+		DMAOUTREG(MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl);
+		DMAOUTREG(MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl);
 		sarea_priv->dirty &= ~MACH64_UPLOAD_MISC;
 	}
 
-	if ( dirty & MACH64_UPLOAD_DST_OFF_PITCH ) {
-		DMAOUTREG( MACH64_DST_OFF_PITCH, regs->dst_off_pitch );
+	if (dirty & MACH64_UPLOAD_DST_OFF_PITCH) {
+		DMAOUTREG(MACH64_DST_OFF_PITCH, regs->dst_off_pitch);
 		sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH;
 	}
-	if ( dirty & MACH64_UPLOAD_Z_OFF_PITCH ) {
-		DMAOUTREG( MACH64_Z_OFF_PITCH, regs->z_off_pitch );
+	if (dirty & MACH64_UPLOAD_Z_OFF_PITCH) {
+		DMAOUTREG(MACH64_Z_OFF_PITCH, regs->z_off_pitch);
 		sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH;
 	}
-	if ( dirty & MACH64_UPLOAD_Z_ALPHA_CNTL ) {
-		DMAOUTREG( MACH64_Z_CNTL, regs->z_cntl );
-		DMAOUTREG( MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl );
+	if (dirty & MACH64_UPLOAD_Z_ALPHA_CNTL) {
+		DMAOUTREG(MACH64_Z_CNTL, regs->z_cntl);
+		DMAOUTREG(MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl);
 		sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL;
 	}
-	if ( dirty & MACH64_UPLOAD_SCALE_3D_CNTL ) {
-		DMAOUTREG( MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl );
+	if (dirty & MACH64_UPLOAD_SCALE_3D_CNTL) {
+		DMAOUTREG(MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl);
 		sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL;
 	}
-	if ( dirty & MACH64_UPLOAD_DP_FOG_CLR ) {
-		DMAOUTREG( MACH64_DP_FOG_CLR, regs->dp_fog_clr );
+	if (dirty & MACH64_UPLOAD_DP_FOG_CLR) {
+		DMAOUTREG(MACH64_DP_FOG_CLR, regs->dp_fog_clr);
 		sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR;
 	}
-	if ( dirty & MACH64_UPLOAD_DP_WRITE_MASK ) {
-		DMAOUTREG( MACH64_DP_WRITE_MASK, regs->dp_write_mask );
+	if (dirty & MACH64_UPLOAD_DP_WRITE_MASK) {
+		DMAOUTREG(MACH64_DP_WRITE_MASK, regs->dp_write_mask);
 		sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK;
 	}
-	if ( dirty & MACH64_UPLOAD_DP_PIX_WIDTH ) {
-		DMAOUTREG( MACH64_DP_PIX_WIDTH, regs->dp_pix_width );
+	if (dirty & MACH64_UPLOAD_DP_PIX_WIDTH) {
+		DMAOUTREG(MACH64_DP_PIX_WIDTH, regs->dp_pix_width);
 		sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH;
 	}
-	if ( dirty & MACH64_UPLOAD_SETUP_CNTL ) {
-		DMAOUTREG( MACH64_SETUP_CNTL, regs->setup_cntl );
+	if (dirty & MACH64_UPLOAD_SETUP_CNTL) {
+		DMAOUTREG(MACH64_SETUP_CNTL, regs->setup_cntl);
 		sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL;
 	}
 
-	if ( dirty & MACH64_UPLOAD_TEXTURE ) {
-		DMAOUTREG( MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch );
-		DMAOUTREG( MACH64_TEX_CNTL, regs->tex_cntl );
-		DMAOUTREG( MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off );
-		DMAOUTREG( MACH64_TEX_0_OFF + offset, regs->tex_offset );
+	if (dirty & MACH64_UPLOAD_TEXTURE) {
+		DMAOUTREG(MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch);
+		DMAOUTREG(MACH64_TEX_CNTL, regs->tex_cntl);
+		DMAOUTREG(MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off);
+		DMAOUTREG(MACH64_TEX_0_OFF + offset, regs->tex_offset);
 		sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE;
 	}
 
-	DMAADVANCE( dev_priv, 1 );
+	DMAADVANCE(dev_priv, 1);
 
 	sarea_priv->dirty &= MACH64_UPLOAD_CLIPRECTS;
 
@@ -180,16 +188,15 @@ static __inline__ int mach64_emit_state( DRMFILE filp, drm_mach64_private_t *dev
 
 }
 
-
 /* ================================================================
  * DMA command dispatch functions
  */
 
-static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev,
-				      unsigned int flags,
-				      int cx, int cy, int cw, int ch,
-				      unsigned int clear_color,
-				      unsigned int clear_depth )
+static int mach64_dma_dispatch_clear(DRMFILE filp, drm_device_t * dev,
+				     unsigned int flags,
+				     int cx, int cy, int cw, int ch,
+				     unsigned int clear_color,
+				     unsigned int clear_depth)
 {
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 	drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -200,9 +207,9 @@ static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev,
 	int i;
 	DMALOCALS;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	switch ( dev_priv->fb_bpp ) {
+	switch (dev_priv->fb_bpp) {
 	case 16:
 		fb_bpp = MACH64_DATATYPE_RGB565;
 		break;
@@ -212,7 +219,7 @@ static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev,
 	default:
 		return DRM_ERR(EINVAL);
 	}
-	switch ( dev_priv->depth_bpp ) {
+	switch (dev_priv->depth_bpp) {
 	case 16:
 		depth_bpp = MACH64_DATATYPE_RGB565;
 		break;
@@ -224,118 +231,111 @@ static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev,
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( !nbox ) 
+	if (!nbox)
 		return 0;
 
-	DMAGETPTR( filp, dev_priv, nbox * 31 ); /* returns on failure to get buffer */
+	DMAGETPTR(filp, dev_priv, nbox * 31);	/* returns on failure to get buffer */
 
-	for ( i = 0 ; i < nbox ; i++ ) {
+	for (i = 0; i < nbox; i++) {
 		int x = pbox[i].x1;
 		int y = pbox[i].y1;
 		int w = pbox[i].x2 - x;
 		int h = pbox[i].y2 - y;
-		
-		DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
-			   pbox[i].x1, pbox[i].y1,
-			   pbox[i].x2, pbox[i].y2, flags );
-		
-		if ( flags & (MACH64_FRONT | MACH64_BACK) ) {
+
+		DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
+			  pbox[i].x1, pbox[i].y1,
+			  pbox[i].x2, pbox[i].y2, flags);
+
+		if (flags & (MACH64_FRONT | MACH64_BACK)) {
 			/* Setup for color buffer clears
 			 */
-			
-			DMAOUTREG( MACH64_Z_CNTL, 0 );
-			DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
-			
-			DMAOUTREG( MACH64_SC_LEFT_RIGHT, ctx->sc_left_right );
-			DMAOUTREG( MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom );
-
-			DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 );
-			DMAOUTREG( MACH64_GUI_TRAJ_CNTL,
-				   (MACH64_DST_X_LEFT_TO_RIGHT |
-				    MACH64_DST_Y_TOP_TO_BOTTOM) );
-			
-			DMAOUTREG( MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
-							 (fb_bpp << 4) |
-							 (fb_bpp << 8) |
-							 (fb_bpp << 16) |
-							 (fb_bpp << 28)) );
-			
-			DMAOUTREG( MACH64_DP_FRGD_CLR, clear_color );
-			DMAOUTREG( MACH64_DP_WRITE_MASK, ctx->dp_write_mask );
-			DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
-						   MACH64_FRGD_MIX_S) );
-			DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
-						   MACH64_FRGD_SRC_FRGD_CLR |
-						   MACH64_MONO_SRC_ONE) );
-			
-						
+
+			DMAOUTREG(MACH64_Z_CNTL, 0);
+			DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
+
+			DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right);
+			DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom);
+
+			DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
+			DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
+				  (MACH64_DST_X_LEFT_TO_RIGHT |
+				   MACH64_DST_Y_TOP_TO_BOTTOM));
+
+			DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
+							(fb_bpp << 4) |
+							(fb_bpp << 8) |
+							(fb_bpp << 16) |
+							(fb_bpp << 28)));
+
+			DMAOUTREG(MACH64_DP_FRGD_CLR, clear_color);
+			DMAOUTREG(MACH64_DP_WRITE_MASK, ctx->dp_write_mask);
+			DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
+						  MACH64_FRGD_MIX_S));
+			DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
+						  MACH64_FRGD_SRC_FRGD_CLR |
+						  MACH64_MONO_SRC_ONE));
+
 		}
 
-		if ( flags & MACH64_FRONT ) {
-						
-			DMAOUTREG( MACH64_DST_OFF_PITCH,
-				   dev_priv->front_offset_pitch );
-			DMAOUTREG( MACH64_DST_X_Y,
-				   (y << 16) | x );
-			DMAOUTREG( MACH64_DST_WIDTH_HEIGHT,
-				   (h << 16) | w );
-			
+		if (flags & MACH64_FRONT) {
+
+			DMAOUTREG(MACH64_DST_OFF_PITCH,
+				  dev_priv->front_offset_pitch);
+			DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
+			DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
+
 		}
-		
-		if ( flags & MACH64_BACK ) {
-						
-			DMAOUTREG( MACH64_DST_OFF_PITCH,
-				   dev_priv->back_offset_pitch );
-			DMAOUTREG( MACH64_DST_X_Y,
-				   (y << 16) | x );
-			DMAOUTREG( MACH64_DST_WIDTH_HEIGHT,
-				   (h << 16) | w );
-			
+
+		if (flags & MACH64_BACK) {
+
+			DMAOUTREG(MACH64_DST_OFF_PITCH,
+				  dev_priv->back_offset_pitch);
+			DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
+			DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
+
 		}
-				
-		if ( flags & MACH64_DEPTH ) {
+
+		if (flags & MACH64_DEPTH) {
 			/* Setup for depth buffer clear
 			 */
-			DMAOUTREG( MACH64_Z_CNTL, 0 );
-			DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
-			
-			DMAOUTREG( MACH64_SC_LEFT_RIGHT, ctx->sc_left_right );
-			DMAOUTREG( MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom );
-
-			DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 );
-			DMAOUTREG( MACH64_GUI_TRAJ_CNTL,
-				   (MACH64_DST_X_LEFT_TO_RIGHT |
-				    MACH64_DST_Y_TOP_TO_BOTTOM) );
-			
-			DMAOUTREG( MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) |
-							 (depth_bpp << 4) |
-							 (depth_bpp << 8) |
-							 (depth_bpp << 16) |
-							 (depth_bpp << 28)) );
-			
-			DMAOUTREG( MACH64_DP_FRGD_CLR, clear_depth );
-			DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff );
-			DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
-						   MACH64_FRGD_MIX_S) );
-			DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
-						   MACH64_FRGD_SRC_FRGD_CLR |
-						   MACH64_MONO_SRC_ONE) );
-			
-			DMAOUTREG( MACH64_DST_OFF_PITCH,
-				   dev_priv->depth_offset_pitch );
-			DMAOUTREG( MACH64_DST_X_Y,
-				   (y << 16) | x );
-			DMAOUTREG( MACH64_DST_WIDTH_HEIGHT,
-				   (h << 16) | w );
+			DMAOUTREG(MACH64_Z_CNTL, 0);
+			DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
+
+			DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right);
+			DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom);
+
+			DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
+			DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
+				  (MACH64_DST_X_LEFT_TO_RIGHT |
+				   MACH64_DST_Y_TOP_TO_BOTTOM));
+
+			DMAOUTREG(MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) |
+							(depth_bpp << 4) |
+							(depth_bpp << 8) |
+							(depth_bpp << 16) |
+							(depth_bpp << 28)));
+
+			DMAOUTREG(MACH64_DP_FRGD_CLR, clear_depth);
+			DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff);
+			DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
+						  MACH64_FRGD_MIX_S));
+			DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
+						  MACH64_FRGD_SRC_FRGD_CLR |
+						  MACH64_MONO_SRC_ONE));
+
+			DMAOUTREG(MACH64_DST_OFF_PITCH,
+				  dev_priv->depth_offset_pitch);
+			DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
+			DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
 		}
 	}
 
-	DMAADVANCE( dev_priv, 1 );
+	DMAADVANCE(dev_priv, 1);
 
 	return 0;
 }
 
-static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev )
+static int mach64_dma_dispatch_swap(DRMFILE filp, drm_device_t * dev)
 {
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 	drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -345,9 +345,9 @@ static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev )
 	int i;
 	DMALOCALS;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	switch ( dev_priv->fb_bpp ) {
+	switch (dev_priv->fb_bpp) {
 	case 16:
 		fb_bpp = MACH64_DATATYPE_RGB565;
 		break;
@@ -357,59 +357,55 @@ static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev )
 		break;
 	}
 
-	if ( !nbox ) 
+	if (!nbox)
 		return 0;
 
-	DMAGETPTR( filp, dev_priv, 13 + nbox * 4 ); /* returns on failure to get buffer */
+	DMAGETPTR(filp, dev_priv, 13 + nbox * 4);	/* returns on failure to get buffer */
 
-	DMAOUTREG( MACH64_Z_CNTL, 0 );
-	DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
+	DMAOUTREG(MACH64_Z_CNTL, 0);
+	DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
 
-	DMAOUTREG( MACH64_SC_LEFT_RIGHT, 0 | ( 8191 << 16 ) ); /* no scissor */
-	DMAOUTREG( MACH64_SC_TOP_BOTTOM, 0 | ( 16383 << 16 ) );
+	DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16));	/* no scissor */
+	DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16));
 
-	DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 );
-	DMAOUTREG( MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT |
-					  MACH64_DST_Y_TOP_TO_BOTTOM) );
+	DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
+	DMAOUTREG(MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT |
+					 MACH64_DST_Y_TOP_TO_BOTTOM));
 
-	DMAOUTREG( MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
-					 (fb_bpp << 4) |
-					 (fb_bpp << 8) |
-					 (fb_bpp << 16) |
-					 (fb_bpp << 28)) );
+	DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
+					(fb_bpp << 4) |
+					(fb_bpp << 8) |
+					(fb_bpp << 16) | (fb_bpp << 28)));
 
-	DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff );
-	DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
-				   MACH64_FRGD_MIX_S) );
-	DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR |
-				   MACH64_FRGD_SRC_BLIT |
-				   MACH64_MONO_SRC_ONE) );
+	DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff);
+	DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S));
+	DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR |
+				  MACH64_FRGD_SRC_BLIT | MACH64_MONO_SRC_ONE));
 
-	DMAOUTREG( MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch );
-	DMAOUTREG( MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch );
+	DMAOUTREG(MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch);
+	DMAOUTREG(MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch);
 
-	for ( i = 0 ; i < nbox ; i++ ) {
+	for (i = 0; i < nbox; i++) {
 		int x = pbox[i].x1;
 		int y = pbox[i].y1;
 		int w = pbox[i].x2 - x;
 		int h = pbox[i].y2 - y;
 
-		DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
-			  pbox[i].x1, pbox[i].y1,
-			  pbox[i].x2, pbox[i].y2 );
+		DRM_DEBUG("dispatch swap %d,%d-%d,%d\n",
+			  pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2);
 
-		DMAOUTREG( MACH64_SRC_WIDTH1, w );
-		DMAOUTREG( MACH64_SRC_Y_X, (x << 16) | y );
-		DMAOUTREG( MACH64_DST_Y_X, (x << 16) | y );
-		DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, (h << 16) | w );
+		DMAOUTREG(MACH64_SRC_WIDTH1, w);
+		DMAOUTREG(MACH64_SRC_Y_X, (x << 16) | y);
+		DMAOUTREG(MACH64_DST_Y_X, (x << 16) | y);
+		DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
 
 	}
 
-	DMAADVANCE( dev_priv, 1 );
+	DMAADVANCE(dev_priv, 1);
 
 	if (dev_priv->driver_mode == MACH64_MODE_DMA_ASYNC) {
 		for (i = 0; i < MACH64_MAX_QUEUED_FRAMES - 1; i++) {
-			dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i+1];
+			dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i + 1];
 		}
 		dev_priv->frame_ofs[i] = GETRINGOFFSET();
 
@@ -419,26 +415,26 @@ static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev )
 	return 0;
 }
 
-static int mach64_do_get_frames_queued( drm_mach64_private_t *dev_priv )
+static int mach64_do_get_frames_queued(drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
 	drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	int i, start;
 	u32 head, tail, ofs;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
 	if (sarea_priv->frames_queued == 0)
 		return 0;
 
 	tail = ring->tail;
-	mach64_ring_tick( dev_priv, ring );
+	mach64_ring_tick(dev_priv, ring);
 	head = ring->head;
 
-	start = ( MACH64_MAX_QUEUED_FRAMES - 
-		  DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued) );
+	start = (MACH64_MAX_QUEUED_FRAMES -
+		 DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued));
 
-	if ( head == tail ) {
+	if (head == tail) {
 		sarea_priv->frames_queued = 0;
 		for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) {
 			dev_priv->frame_ofs[i] = ~0;
@@ -446,13 +442,14 @@ static int mach64_do_get_frames_queued( drm_mach64_private_t *dev_priv )
 		return 0;
 	}
 
-	for ( i = start; i < MACH64_MAX_QUEUED_FRAMES; i++ ) {
+	for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) {
 		ofs = dev_priv->frame_ofs[i];
-		DRM_DEBUG( "frame_ofs[%d] ofs: %d\n", i, ofs );
-		if ( ofs == ~0 ||
-		     ( head < tail && (ofs < head || ofs >= tail) ) ||
-		     ( head > tail && (ofs < head && ofs >= tail) ) ) {
-			sarea_priv->frames_queued = (MACH64_MAX_QUEUED_FRAMES - 1) - i;
+		DRM_DEBUG("frame_ofs[%d] ofs: %d\n", i, ofs);
+		if (ofs == ~0 ||
+		    (head < tail && (ofs < head || ofs >= tail)) ||
+		    (head > tail && (ofs < head && ofs >= tail))) {
+			sarea_priv->frames_queued =
+			    (MACH64_MAX_QUEUED_FRAMES - 1) - i;
 			dev_priv->frame_ofs[i] = ~0;
 		}
 	}
@@ -463,22 +460,23 @@ static int mach64_do_get_frames_queued( drm_mach64_private_t *dev_priv )
 /* Copy and verify a client submited buffer.
  * FIXME: Make an assembly optimized version
  */
-static __inline__ int copy_and_verify_from_user( u32 *to, const u32 *from, unsigned long bytes )
+static __inline__ int copy_and_verify_from_user(u32 * to, const u32 * from,
+						unsigned long bytes)
 {
-	unsigned long n = bytes; /* dwords remaining in buffer */
+	unsigned long n = bytes;	/* dwords remaining in buffer */
 
-	if ( DRM_VERIFYAREA_READ( from, n ) ) {
-		DRM_ERROR( "%s: verify_area\n", __FUNCTION__ );
+	if (DRM_VERIFYAREA_READ(from, n)) {
+		DRM_ERROR("%s: verify_area\n", __FUNCTION__);
 		return DRM_ERR(EFAULT);
 	}
 
 	n >>= 2;
 
-	while ( n > 1 ) {
+	while (n > 1) {
 		u32 data, reg, count;
 
-		if ( DRM_GET_USER_UNCHECKED( data, from++ ) ) {
-			DRM_ERROR( "%s: get_user\n", __FUNCTION__ );
+		if (DRM_GET_USER_UNCHECKED(data, from++)) {
+			DRM_ERROR("%s: get_user\n", __FUNCTION__);
 			return DRM_ERR(EFAULT);
 		}
 
@@ -486,30 +484,34 @@ static __inline__ int copy_and_verify_from_user( u32 *to, const u32 *from, unsig
 
 		reg = le32_to_cpu(data);
 		count = (reg >> 16) + 1;
-		if( count <= n ) {
+		if (count <= n) {
 			n -= count;
 			reg &= 0xffff;
 
 			/* This is an exact match of Mach64's Setup Engine registers,
 			 * excluding SETUP_CNTL (1_C1).
 			 */
-			if( (reg >= 0x0190 && reg <  0x01c1) || 
-			    (reg >= 0x01ca && reg <= 0x01cf) ) {
+			if ((reg >= 0x0190 && reg < 0x01c1) ||
+			    (reg >= 0x01ca && reg <= 0x01cf)) {
 				*to++ = data;
-				if ( DRM_COPY_FROM_USER_UNCHECKED( to, from, count << 2 ) ) {
-					DRM_ERROR( "%s: copy_from_user\n", __FUNCTION__ );
+				if (DRM_COPY_FROM_USER_UNCHECKED
+				    (to, from, count << 2)) {
+					DRM_ERROR("%s: copy_from_user\n",
+						  __FUNCTION__);
 					return DRM_ERR(EFAULT);
 				}
 				to += count;
 			} else {
-				DRM_ERROR( "%s: Got bad command: 0x%04x\n", __FUNCTION__, reg );
+				DRM_ERROR("%s: Got bad command: 0x%04x\n",
+					  __FUNCTION__, reg);
 				return DRM_ERR(EACCES);
 			}
 
 			from += count;
 		} else {
-			DRM_ERROR( "%s: Got bad command count(=%u) dwords remaining=%lu\n", 
-				   __FUNCTION__, count, n );
+			DRM_ERROR
+			    ("%s: Got bad command count(=%u) dwords remaining=%lu\n",
+			     __FUNCTION__, count, n);
 			return DRM_ERR(EINVAL);
 		}
 	}
@@ -517,13 +519,14 @@ static __inline__ int copy_and_verify_from_user( u32 *to, const u32 *from, unsig
 	if (n == 0)
 		return 0;
 	else {
-		DRM_ERROR( "%s: Bad buf->used(=%lu)\n", __FUNCTION__, bytes );
+		DRM_ERROR("%s: Bad buf->used(=%lu)\n", __FUNCTION__, bytes);
 		return DRM_ERR(EINVAL);
 	}
 }
 
-static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim, void *buf, 
-				       unsigned long used, int discard )
+static int mach64_dma_dispatch_vertex(DRMFILE filp, drm_device_t * dev,
+				      int prim, void *buf, unsigned long used,
+				      int discard)
 {
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 	drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -532,41 +535,45 @@ static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim
 	int verify_ret = 0;
 	DMALOCALS;
 
-	DRM_DEBUG( "%s: buf=%p used=%lu nbox=%d\n",
-		   __FUNCTION__, buf, used, sarea_priv->nbox );
+	DRM_DEBUG("%s: buf=%p used=%lu nbox=%d\n",
+		  __FUNCTION__, buf, used, sarea_priv->nbox);
 
-	if ( used ) {
+	if (used) {
 		int ret = 0;
 		int i = 0;
 
-		copy_buf = mach64_freelist_get( dev_priv );
+		copy_buf = mach64_freelist_get(dev_priv);
 		if (copy_buf == NULL) {
 			DRM_ERROR("%s: couldn't get buffer in DMAGETPTR\n",
-				   __FUNCTION__ );
+				  __FUNCTION__);
 			return DRM_ERR(EAGAIN);
 		}
 
-		if ( (verify_ret = 
-		      copy_and_verify_from_user( GETBUFPTR( copy_buf ), buf, used )) == 0 ) {
+		if ((verify_ret =
+		     copy_and_verify_from_user(GETBUFPTR(copy_buf), buf,
+					       used)) == 0) {
 
 			copy_buf->used = used;
 
-			DMASETPTR( copy_buf );
+			DMASETPTR(copy_buf);
 
-			if ( sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS ) {
-				ret = mach64_emit_state( filp, dev_priv );
-				if (ret < 0) return ret;
+			if (sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS) {
+				ret = mach64_emit_state(filp, dev_priv);
+				if (ret < 0)
+					return ret;
 			}
- 
+
 			do {
 				/* Emit the next cliprect */
-				if ( i < sarea_priv->nbox ) {
-					ret = mach64_emit_cliprect(filp, dev_priv, 
-								   &sarea_priv->boxes[i]);
-					if ( ret < 0 ) {
+				if (i < sarea_priv->nbox) {
+					ret =
+					    mach64_emit_cliprect(filp, dev_priv,
+								 &sarea_priv->
+								 boxes[i]);
+					if (ret < 0) {
 						/* failed to get buffer */
 						return ret;
-					} else if ( ret != 0 ) {
+					} else if (ret != 0) {
 						/* null intersection with scissor */
 						continue;
 					}
@@ -575,9 +582,9 @@ static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim
 					done = 1;
 
 				/* Add the buffer to the DMA queue */
-				DMAADVANCE( dev_priv, done );
+				DMAADVANCE(dev_priv, done);
 
-			} while ( ++i < sarea_priv->nbox );
+			} while (++i < sarea_priv->nbox);
 		}
 
 		if (copy_buf->pending && !done) {
@@ -590,10 +597,13 @@ static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim
 			drm_mach64_freelist_t *entry;
 #if MACH64_EXTRA_CHECKING
 			list_for_each(ptr, &dev_priv->pending) {
-				entry = list_entry(ptr, drm_mach64_freelist_t, list);
+				entry =
+				    list_entry(ptr, drm_mach64_freelist_t,
+					       list);
 				if (copy_buf == entry->buf) {
-					DRM_ERROR( "%s: Trying to release a pending buf\n",
-						   __FUNCTION__ );
+					DRM_ERROR
+					    ("%s: Trying to release a pending buf\n",
+					     __FUNCTION__);
 					return DRM_ERR(EFAULT);
 				}
 			}
@@ -615,9 +625,8 @@ static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim
 	return verify_ret;
 }
 
-
-static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev,
-				     drm_mach64_blit_t *blit )
+static int mach64_dma_dispatch_blit(DRMFILE filp, drm_device_t * dev,
+				    drm_mach64_blit_t * blit)
 {
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 	drm_device_dma_t *dma = dev->dma;
@@ -629,7 +638,7 @@ static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev,
 	 * even if the only legal values are powers of two.  Thus, we'll
 	 * use a shift instead.
 	 */
-	switch ( blit->format ) {
+	switch (blit->format) {
 	case MACH64_DATATYPE_ARGB8888:
 		dword_shift = 0;
 		break;
@@ -645,84 +654,80 @@ static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev,
 		dword_shift = 2;
 		break;
 	default:
-		DRM_ERROR( "invalid blit format %d\n", blit->format );
+		DRM_ERROR("invalid blit format %d\n", blit->format);
 		return DRM_ERR(EINVAL);
 	}
 
 	/* Dispatch the blit buffer.
 	 */
 	buf = dma->buflist[blit->idx];
-	
-	if ( buf->filp != filp ) {
-		DRM_ERROR( "process %d (filp %p) using buffer with filp %p\n",
-			   DRM_CURRENTPID, filp, buf->filp );
+
+	if (buf->filp != filp) {
+		DRM_ERROR("process %d (filp %p) using buffer with filp %p\n",
+			  DRM_CURRENTPID, filp, buf->filp);
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", blit->idx );
+	if (buf->pending) {
+		DRM_ERROR("sending pending buffer %d\n", blit->idx);
 		return DRM_ERR(EINVAL);
 	}
 
-	/* Set buf->used to the bytes of blit data based on the blit dimensions 
-	 * and verify the size.  When the setup is emitted to the buffer with 
-	 * the DMA* macros below, buf->used is incremented to include the bytes 
+	/* Set buf->used to the bytes of blit data based on the blit dimensions
+	 * and verify the size.  When the setup is emitted to the buffer with
+	 * the DMA* macros below, buf->used is incremented to include the bytes
 	 * used for setup as well as the blit data.
 	 */
-	dwords =  (blit->width * blit->height) >> dword_shift;
+	dwords = (blit->width * blit->height) >> dword_shift;
 	buf->used = dwords << 2;
-	if ( buf->used <= 0 || 
-	     buf->used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET ) {
-		DRM_ERROR( "Invalid blit size: %d bytes\n", buf->used );
+	if (buf->used <= 0 ||
+	    buf->used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET) {
+		DRM_ERROR("Invalid blit size: %d bytes\n", buf->used);
 		return DRM_ERR(EINVAL);
 	}
 
 	/* FIXME: Use a last buffer flag and reduce the state emitted for subsequent,
-	 * continuation buffers? 
+	 * continuation buffers?
 	 */
 
 	/* Blit via BM_HOSTDATA (gui-master) - like HOST_DATA[0-15], but doesn't require
-	 * a register command every 16 dwords.  State setup is added at the start of the 
+	 * a register command every 16 dwords.  State setup is added at the start of the
 	 * buffer -- the client leaves space for this based on MACH64_HOSTDATA_BLIT_OFFSET
 	 */
-	DMASETPTR( buf );
-
-	DMAOUTREG( MACH64_Z_CNTL, 0 );
-	DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
-
-	DMAOUTREG( MACH64_SC_LEFT_RIGHT, 0 | ( 8191 << 16 ) );	/* no scissor */
-	DMAOUTREG( MACH64_SC_TOP_BOTTOM, 0 | ( 16383 << 16 )  );
-
-	DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 );			/* disable */
-	DMAOUTREG( MACH64_GUI_TRAJ_CNTL, 
-		   MACH64_DST_X_LEFT_TO_RIGHT 
-		   | MACH64_DST_Y_TOP_TO_BOTTOM );
-
-	DMAOUTREG( MACH64_DP_PIX_WIDTH,
-		   ( blit->format << 0 )			/* dst pix width */
-		   | ( blit->format << 4 )			/* composite pix width */
-		   | ( blit->format << 8 )			/* src pix width */
-		   | ( blit->format << 16 )			/* host data pix width */
-		   | ( blit->format << 28 )			/* scaler/3D pix width */
-		   );
-
-	DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff );		/* enable all planes */
-	DMAOUTREG( MACH64_DP_MIX, 
-		   MACH64_BKGD_MIX_D 
-		   | MACH64_FRGD_MIX_S );
-	DMAOUTREG( MACH64_DP_SRC, 
-		   MACH64_BKGD_SRC_BKGD_CLR 
-		   | MACH64_FRGD_SRC_HOST 
-		   | MACH64_MONO_SRC_ONE );
-
-	DMAOUTREG( MACH64_DST_OFF_PITCH, (blit->pitch << 22) | (blit->offset >> 3) );
-	DMAOUTREG( MACH64_DST_X_Y, (blit->y << 16) | blit->x );
-	DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width );
-
-	DRM_DEBUG( "%s: %d bytes\n", __FUNCTION__, buf->used );
+	DMASETPTR(buf);
+
+	DMAOUTREG(MACH64_Z_CNTL, 0);
+	DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
+
+	DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16));	/* no scissor */
+	DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16));
+
+	DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);	/* disable */
+	DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
+		  MACH64_DST_X_LEFT_TO_RIGHT | MACH64_DST_Y_TOP_TO_BOTTOM);
+
+	DMAOUTREG(MACH64_DP_PIX_WIDTH, (blit->format << 0)	/* dst pix width */
+		  |(blit->format << 4)	/* composite pix width */
+		  |(blit->format << 8)	/* src pix width */
+		  |(blit->format << 16)	/* host data pix width */
+		  |(blit->format << 28)	/* scaler/3D pix width */
+	    );
+
+	DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff);	/* enable all planes */
+	DMAOUTREG(MACH64_DP_MIX, MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S);
+	DMAOUTREG(MACH64_DP_SRC,
+		  MACH64_BKGD_SRC_BKGD_CLR
+		  | MACH64_FRGD_SRC_HOST | MACH64_MONO_SRC_ONE);
+
+	DMAOUTREG(MACH64_DST_OFF_PITCH,
+		  (blit->pitch << 22) | (blit->offset >> 3));
+	DMAOUTREG(MACH64_DST_X_Y, (blit->y << 16) | blit->x);
+	DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width);
+
+	DRM_DEBUG("%s: %d bytes\n", __FUNCTION__, buf->used);
 
 	/* Add the buffer to the queue */
-	DMAADVANCEHOSTDATA( dev_priv );
+	DMAADVANCEHOSTDATA(dev_priv);
 
 	return 0;
 }
@@ -731,7 +736,7 @@ static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev,
  * IOCTL functions
  */
 
-int mach64_dma_clear( DRM_IOCTL_ARGS )
+int mach64_dma_clear(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mach64_private_t *dev_priv = dev->dev_private;
@@ -739,90 +744,88 @@ int mach64_dma_clear( DRM_IOCTL_ARGS )
 	drm_mach64_clear_t clear;
 	int ret;
 
-	DRM_DEBUG( "%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID  );
+	DRM_DEBUG("%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID);
+
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
-	
-	DRM_COPY_FROM_USER_IOCTL( clear, (drm_mach64_clear_t *)data,
-			     sizeof(clear) );
-	
-	if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS )
+	DRM_COPY_FROM_USER_IOCTL(clear, (drm_mach64_clear_t *) data,
+				 sizeof(clear));
+
+	if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
 
-	ret = mach64_dma_dispatch_clear( filp, dev, clear.flags,
-					 clear.x, clear.y, clear.w, clear.h,
-					 clear.clear_color, clear.clear_depth );
+	ret = mach64_dma_dispatch_clear(filp, dev, clear.flags,
+					clear.x, clear.y, clear.w, clear.h,
+					clear.clear_color, clear.clear_depth);
 
 	/* Make sure we restore the 3D state next time.
 	 */
-	sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
-			      MACH64_UPLOAD_MISC);
+	sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC);
 	return ret;
 }
 
-int mach64_dma_swap( DRM_IOCTL_ARGS )
+int mach64_dma_swap(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 	drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	int ret;
 
-	DRM_DEBUG( "%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID );
+	DRM_DEBUG("%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID);
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
-	
-	if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS )
+	LOCK_TEST_WITH_RETURN(dev, filp);
+
+	if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
 
-	ret = mach64_dma_dispatch_swap( filp, dev );
+	ret = mach64_dma_dispatch_swap(filp, dev);
 
 	/* Make sure we restore the 3D state next time.
 	 */
-	sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
-			      MACH64_UPLOAD_MISC);
+	sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC);
 	return ret;
 }
 
-int mach64_dma_vertex( DRM_IOCTL_ARGS )
+int mach64_dma_vertex(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 	drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mach64_vertex_t vertex;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( vertex, (drm_mach64_vertex_t *)data,
-			     sizeof(vertex) );
+	DRM_COPY_FROM_USER_IOCTL(vertex, (drm_mach64_vertex_t *) data,
+				 sizeof(vertex));
 
-	DRM_DEBUG( "%s: pid=%d buf=%p used=%lu discard=%d\n",
-		   __FUNCTION__, DRM_CURRENTPID,
-		   vertex.buf, vertex.used, vertex.discard );
+	DRM_DEBUG("%s: pid=%d buf=%p used=%lu discard=%d\n",
+		  __FUNCTION__, DRM_CURRENTPID,
+		  vertex.buf, vertex.used, vertex.discard);
 
-	if ( vertex.prim < 0 ||
-	     vertex.prim > MACH64_PRIM_POLYGON ) {
-		DRM_ERROR( "buffer prim %d\n", vertex.prim );
+	if (vertex.prim < 0 || vertex.prim > MACH64_PRIM_POLYGON) {
+		DRM_ERROR("buffer prim %d\n", vertex.prim);
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( vertex.used > MACH64_BUFFER_SIZE || (vertex.used & 3) != 0) {
-		DRM_ERROR( "Invalid vertex buffer size: %lu bytes\n", vertex.used );
+	if (vertex.used > MACH64_BUFFER_SIZE || (vertex.used & 3) != 0) {
+		DRM_ERROR("Invalid vertex buffer size: %lu bytes\n",
+			  vertex.used);
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS )
+	if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
 
-	return mach64_dma_dispatch_vertex( filp, dev, vertex.prim, vertex.buf, 
-					   vertex.used, vertex.discard );
+	return mach64_dma_dispatch_vertex(filp, dev, vertex.prim, vertex.buf,
+					  vertex.used, vertex.discard);
 }
 
-int mach64_dma_blit( DRM_IOCTL_ARGS )
+int mach64_dma_blit(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_device_dma_t *dma = dev->dma;
@@ -831,53 +834,52 @@ int mach64_dma_blit( DRM_IOCTL_ARGS )
 	drm_mach64_blit_t blit;
 	int ret;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( blit, (drm_mach64_blit_t *)data,
-			     sizeof(blit) );
+	DRM_COPY_FROM_USER_IOCTL(blit, (drm_mach64_blit_t *) data,
+				 sizeof(blit));
 
-	DRM_DEBUG( "%s: pid=%d index=%d\n",
-		   __FUNCTION__, DRM_CURRENTPID, blit.idx );
+	DRM_DEBUG("%s: pid=%d index=%d\n",
+		  __FUNCTION__, DRM_CURRENTPID, blit.idx);
 
-	if ( blit.idx < 0 || blit.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   blit.idx, dma->buf_count - 1 );
+	if (blit.idx < 0 || blit.idx >= dma->buf_count) {
+		DRM_ERROR("buffer index %d (of %d max)\n",
+			  blit.idx, dma->buf_count - 1);
 		return DRM_ERR(EINVAL);
 	}
 
-	ret = mach64_dma_dispatch_blit( filp, dev, &blit );
+	ret = mach64_dma_dispatch_blit(filp, dev, &blit);
 
 	/* Make sure we restore the 3D state next time.
 	 */
 	sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
-			      MACH64_UPLOAD_MISC | 
-			      MACH64_UPLOAD_CLIPRECTS);
+			      MACH64_UPLOAD_MISC | MACH64_UPLOAD_CLIPRECTS);
 
 	return ret;
 }
 
-int mach64_get_param( DRM_IOCTL_ARGS )
+int mach64_get_param(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mach64_private_t *dev_priv = dev->dev_private;
 	drm_mach64_getparam_t param;
 	int value;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( param, (drm_mach64_getparam_t *)data,
-	    sizeof(param) );
+	DRM_COPY_FROM_USER_IOCTL(param, (drm_mach64_getparam_t *) data,
+				 sizeof(param));
 
-	switch ( param.param ) {
+	switch (param.param) {
 	case MACH64_PARAM_FRAMES_QUEUED:
 		/* Needs lock since it calls mach64_ring_tick() */
-		LOCK_TEST_WITH_RETURN( dev, filp );
-		value = mach64_do_get_frames_queued( dev_priv );
+		LOCK_TEST_WITH_RETURN(dev, filp);
+		value = mach64_do_get_frames_queued(dev_priv);
 		break;
 	case MACH64_PARAM_IRQ_NR:
 		value = dev->irq;
@@ -886,8 +888,8 @@ int mach64_get_param( DRM_IOCTL_ARGS )
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
-		DRM_ERROR( "copy_to_user\n" );
+	if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
+		DRM_ERROR("copy_to_user\n");
 		return DRM_ERR(EFAULT);
 	}
 
diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c
index 896787be..57f4e1c3 100644
--- a/shared-core/mga_dma.c
+++ b/shared-core/mga_dma.c
@@ -41,57 +41,57 @@
 #define MGA_DEFAULT_USEC_TIMEOUT	10000
 #define MGA_FREELIST_DEBUG		0
 
-
 /* ================================================================
  * Engine control
  */
 
-int mga_do_wait_for_idle( drm_mga_private_t *dev_priv )
+int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
 {
 	u32 status = 0;
 	int i;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
-		if ( status == MGA_ENDPRDMASTS ) {
-			MGA_WRITE8( MGA_CRTC_INDEX, 0 );
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
+		if (status == MGA_ENDPRDMASTS) {
+			MGA_WRITE8(MGA_CRTC_INDEX, 0);
 			return 0;
 		}
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
 #if MGA_DMA_DEBUG
-	DRM_ERROR( "failed!\n" );
-	DRM_INFO( "   status=0x%08x\n", status );
+	DRM_ERROR("failed!\n");
+	DRM_INFO("   status=0x%08x\n", status);
 #endif
 	return DRM_ERR(EBUSY);
 }
 
-int mga_do_dma_idle( drm_mga_private_t *dev_priv )
+int mga_do_dma_idle(drm_mga_private_t * dev_priv)
 {
 	u32 status = 0;
 	int i;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		status = MGA_READ( MGA_STATUS ) & MGA_DMA_IDLE_MASK;
-		if ( status == MGA_ENDPRDMASTS ) return 0;
-		DRM_UDELAY( 1 );
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		status = MGA_READ(MGA_STATUS) & MGA_DMA_IDLE_MASK;
+		if (status == MGA_ENDPRDMASTS)
+			return 0;
+		DRM_UDELAY(1);
 	}
 
 #if MGA_DMA_DEBUG
-	DRM_ERROR( "failed! status=0x%08x\n", status );
+	DRM_ERROR("failed! status=0x%08x\n", status);
 #endif
 	return DRM_ERR(EBUSY);
 }
 
-int mga_do_dma_reset( drm_mga_private_t *dev_priv )
+int mga_do_dma_reset(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	/* The primary DMA stream should look like new right about now.
 	 */
@@ -110,16 +110,16 @@ int mga_do_dma_reset( drm_mga_private_t *dev_priv )
 	return 0;
 }
 
-int mga_do_engine_reset( drm_mga_private_t *dev_priv )
+int mga_do_engine_reset(drm_mga_private_t * dev_priv)
 {
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	/* Okay, so we've completely screwed up and locked the engine.
 	 * How about we clean up after ourselves?
 	 */
-	MGA_WRITE( MGA_RST, MGA_SOFTRESET );
-	DRM_UDELAY( 15 );				/* Wait at least 10 usecs */
-	MGA_WRITE( MGA_RST, 0 );
+	MGA_WRITE(MGA_RST, MGA_SOFTRESET);
+	DRM_UDELAY(15);		/* Wait at least 10 usecs */
+	MGA_WRITE(MGA_RST, 0);
 
 	/* Initialize the registers that get clobbered by the soft
 	 * reset.  Many of the core register values survive a reset,
@@ -129,47 +129,46 @@ int mga_do_engine_reset( drm_mga_private_t *dev_priv )
 	 * server should reset the engine state to known values.
 	 */
 #if 0
-	MGA_WRITE( MGA_PRIMPTR,
-		   virt_to_bus((void *)dev_priv->prim.status_page) |
-		   MGA_PRIMPTREN0 |
-		   MGA_PRIMPTREN1 );
+	MGA_WRITE(MGA_PRIMPTR,
+		  virt_to_bus((void *)dev_priv->prim.status_page) |
+		  MGA_PRIMPTREN0 | MGA_PRIMPTREN1);
 #endif
 
-	MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR );
-	MGA_WRITE( MGA_IEN,    MGA_SOFTRAPIEN );
+	MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR);
+	MGA_WRITE(MGA_IEN, MGA_SOFTRAPIEN);
 
 	/* The primary DMA stream should look like new right about now.
 	 */
-	mga_do_dma_reset( dev_priv );
+	mga_do_dma_reset(dev_priv);
 
 	/* This bad boy will never fail.
 	 */
 	return 0;
 }
 
-
 /* ================================================================
  * Primary DMA stream
  */
 
-void mga_do_dma_flush( drm_mga_private_t *dev_priv )
+void mga_do_dma_flush(drm_mga_private_t * dev_priv)
 {
 	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 	u32 head, tail;
 	u32 status = 0;
 	int i;
- 	DMA_LOCALS;
-	DRM_DEBUG( "\n" );
-
-        /* We need to wait so that we can do an safe flush */
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
-		if ( status == MGA_ENDPRDMASTS ) break;
-		DRM_UDELAY( 1 );
+	DMA_LOCALS;
+	DRM_DEBUG("\n");
+
+	/* We need to wait so that we can do an safe flush */
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
+		if (status == MGA_ENDPRDMASTS)
+			break;
+		DRM_UDELAY(1);
 	}
 
-	if ( primary->tail == primary->last_flush ) {
-		DRM_DEBUG( "   bailing out...\n" );
+	if (primary->tail == primary->last_flush) {
+		DRM_DEBUG("   bailing out...\n");
 		return;
 	}
 
@@ -179,48 +178,46 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
 	 * actually (partially?) reads the first of these commands.
 	 * See page 4-16 in the G400 manual, middle of the page or so.
 	 */
-	BEGIN_DMA( 1 );
+	BEGIN_DMA(1);
 
-	DMA_BLOCK( MGA_DMAPAD,  0x00000000,
-		   MGA_DMAPAD,  0x00000000,
-		   MGA_DMAPAD,  0x00000000,
-		   MGA_DMAPAD,	0x00000000 );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 
 	ADVANCE_DMA();
 
 	primary->last_flush = primary->tail;
 
-	head = MGA_READ( MGA_PRIMADDRESS );
+	head = MGA_READ(MGA_PRIMADDRESS);
 
-	if ( head <= tail ) {
+	if (head <= tail) {
 		primary->space = primary->size - primary->tail;
 	} else {
 		primary->space = head - tail;
 	}
 
-	DRM_DEBUG( "   head = 0x%06lx\n", head - dev_priv->primary->offset );
-	DRM_DEBUG( "   tail = 0x%06lx\n", tail - dev_priv->primary->offset );
-	DRM_DEBUG( "  space = 0x%06x\n", primary->space );
+	DRM_DEBUG("   head = 0x%06lx\n", head - dev_priv->primary->offset);
+	DRM_DEBUG("   tail = 0x%06lx\n", tail - dev_priv->primary->offset);
+	DRM_DEBUG("  space = 0x%06x\n", primary->space);
 
 	mga_flush_write_combine();
-	MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
+	MGA_WRITE(MGA_PRIMEND, tail | MGA_PAGPXFER);
 
-	DRM_DEBUG( "done.\n" );
+	DRM_DEBUG("done.\n");
 }
 
-void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
+void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
 {
 	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 	u32 head, tail;
 	DMA_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	BEGIN_DMA_WRAP();
 
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000 );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 
 	ADVANCE_DMA();
 
@@ -230,45 +227,43 @@ void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
 	primary->last_flush = 0;
 	primary->last_wrap++;
 
-	head = MGA_READ( MGA_PRIMADDRESS );
+	head = MGA_READ(MGA_PRIMADDRESS);
 
-	if ( head == dev_priv->primary->offset ) {
+	if (head == dev_priv->primary->offset) {
 		primary->space = primary->size;
 	} else {
 		primary->space = head - dev_priv->primary->offset;
 	}
 
-	DRM_DEBUG( "   head = 0x%06lx\n",
-		  head - dev_priv->primary->offset );
-	DRM_DEBUG( "   tail = 0x%06x\n", primary->tail );
-	DRM_DEBUG( "   wrap = %d\n", primary->last_wrap );
-	DRM_DEBUG( "  space = 0x%06x\n", primary->space );
+	DRM_DEBUG("   head = 0x%06lx\n", head - dev_priv->primary->offset);
+	DRM_DEBUG("   tail = 0x%06x\n", primary->tail);
+	DRM_DEBUG("   wrap = %d\n", primary->last_wrap);
+	DRM_DEBUG("  space = 0x%06x\n", primary->space);
 
 	mga_flush_write_combine();
-	MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
+	MGA_WRITE(MGA_PRIMEND, tail | MGA_PAGPXFER);
 
-	set_bit( 0, &primary->wrapped );
-	DRM_DEBUG( "done.\n" );
+	set_bit(0, &primary->wrapped);
+	DRM_DEBUG("done.\n");
 }
 
-void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
+void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
 {
 	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	u32 head = dev_priv->primary->offset;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	sarea_priv->last_wrap++;
-	DRM_DEBUG( "   wrap = %d\n", sarea_priv->last_wrap );
+	DRM_DEBUG("   wrap = %d\n", sarea_priv->last_wrap);
 
 	mga_flush_write_combine();
-	MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL );
+	MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
 
-	clear_bit( 0, &primary->wrapped );
-	DRM_DEBUG( "done.\n" );
+	clear_bit(0, &primary->wrapped);
+	DRM_DEBUG("done.\n");
 }
 
-
 /* ================================================================
  * Freelist management
  */
@@ -277,63 +272,61 @@ void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
 #define MGA_BUFFER_FREE		0
 
 #if MGA_FREELIST_DEBUG
-static void mga_freelist_print( drm_device_t *dev )
+static void mga_freelist_print(drm_device_t * dev)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_freelist_t *entry;
 
-	DRM_INFO( "\n" );
-	DRM_INFO( "current dispatch: last=0x%x done=0x%x\n",
-		  dev_priv->sarea_priv->last_dispatch,
-		  (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) -
-				 dev_priv->primary->offset) );
-	DRM_INFO( "current freelist:\n" );
-
-	for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) {
-		DRM_INFO( "   %p   idx=%2d  age=0x%x 0x%06lx\n",
-			  entry, entry->buf->idx, entry->age.head,
-			  entry->age.head - dev_priv->primary->offset );
+	DRM_INFO("\n");
+	DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
+		 dev_priv->sarea_priv->last_dispatch,
+		 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
+				dev_priv->primary->offset));
+	DRM_INFO("current freelist:\n");
+
+	for (entry = dev_priv->head->next; entry; entry = entry->next) {
+		DRM_INFO("   %p   idx=%2d  age=0x%x 0x%06lx\n",
+			 entry, entry->buf->idx, entry->age.head,
+			 entry->age.head - dev_priv->primary->offset);
 	}
-	DRM_INFO( "\n" );
+	DRM_INFO("\n");
 }
 #endif
 
-static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
+static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv)
 {
 	drm_device_dma_t *dma = dev->dma;
 	drm_buf_t *buf;
 	drm_mga_buf_priv_t *buf_priv;
 	drm_mga_freelist_t *entry;
 	int i;
-	DRM_DEBUG( "count=%d\n", dma->buf_count );
+	DRM_DEBUG("count=%d\n", dma->buf_count);
 
-	dev_priv->head = drm_alloc( sizeof(drm_mga_freelist_t),
-				     DRM_MEM_DRIVER );
-	if ( dev_priv->head == NULL )
+	dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
+	if (dev_priv->head == NULL)
 		return DRM_ERR(ENOMEM);
 
-	memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) );
-	SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 );
+	memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
+	SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
 
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+	for (i = 0; i < dma->buf_count; i++) {
 		buf = dma->buflist[i];
-	        buf_priv = buf->dev_private;
+		buf_priv = buf->dev_private;
 
-		entry = drm_alloc( sizeof(drm_mga_freelist_t),
-				    DRM_MEM_DRIVER );
-		if ( entry == NULL )
+		entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
+		if (entry == NULL)
 			return DRM_ERR(ENOMEM);
 
-		memset( entry, 0, sizeof(drm_mga_freelist_t) );
+		memset(entry, 0, sizeof(drm_mga_freelist_t));
 
 		entry->next = dev_priv->head->next;
 		entry->prev = dev_priv->head;
-		SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
+		SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
 		entry->buf = buf;
 
-		if ( dev_priv->head->next != NULL )
+		if (dev_priv->head->next != NULL)
 			dev_priv->head->next->prev = entry;
-		if ( entry->next == NULL )
+		if (entry->next == NULL)
 			dev_priv->tail = entry;
 
 		buf_priv->list_entry = entry;
@@ -346,17 +339,17 @@ static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
 	return 0;
 }
 
-static void mga_freelist_cleanup( drm_device_t *dev )
+static void mga_freelist_cleanup(drm_device_t * dev)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_freelist_t *entry;
 	drm_mga_freelist_t *next;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	entry = dev_priv->head;
-	while ( entry ) {
+	while (entry) {
 		next = entry->next;
-		drm_free( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER );
+		drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
 		entry = next;
 	}
 
@@ -366,71 +359,69 @@ static void mga_freelist_cleanup( drm_device_t *dev )
 #if 0
 /* FIXME: Still needed?
  */
-static void mga_freelist_reset( drm_device_t *dev )
+static void mga_freelist_reset(drm_device_t * dev)
 {
 	drm_device_dma_t *dma = dev->dma;
 	drm_buf_t *buf;
 	drm_mga_buf_priv_t *buf_priv;
 	int i;
 
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+	for (i = 0; i < dma->buf_count; i++) {
 		buf = dma->buflist[i];
-	        buf_priv = buf->dev_private;
-		SET_AGE( &buf_priv->list_entry->age,
-			 MGA_BUFFER_FREE, 0 );
+		buf_priv = buf->dev_private;
+		SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
 	}
 }
 #endif
 
-static drm_buf_t *mga_freelist_get( drm_device_t *dev )
+static drm_buf_t *mga_freelist_get(drm_device_t * dev)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_freelist_t *next;
 	drm_mga_freelist_t *prev;
 	drm_mga_freelist_t *tail = dev_priv->tail;
 	u32 head, wrap;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	head = MGA_READ( MGA_PRIMADDRESS );
+	head = MGA_READ(MGA_PRIMADDRESS);
 	wrap = dev_priv->sarea_priv->last_wrap;
 
-	DRM_DEBUG( "   tail=0x%06lx %d\n",
-		   tail->age.head ?
-		   tail->age.head - dev_priv->primary->offset : 0,
-		   tail->age.wrap );
-	DRM_DEBUG( "   head=0x%06lx %d\n",
-		   head - dev_priv->primary->offset, wrap );
+	DRM_DEBUG("   tail=0x%06lx %d\n",
+		  tail->age.head ?
+		  tail->age.head - dev_priv->primary->offset : 0,
+		  tail->age.wrap);
+	DRM_DEBUG("   head=0x%06lx %d\n",
+		  head - dev_priv->primary->offset, wrap);
 
-	if ( TEST_AGE( &tail->age, head, wrap ) ) {
+	if (TEST_AGE(&tail->age, head, wrap)) {
 		prev = dev_priv->tail->prev;
 		next = dev_priv->tail;
 		prev->next = NULL;
 		next->prev = next->next = NULL;
 		dev_priv->tail = prev;
-		SET_AGE( &next->age, MGA_BUFFER_USED, 0 );
+		SET_AGE(&next->age, MGA_BUFFER_USED, 0);
 		return next->buf;
 	}
 
-	DRM_DEBUG( "returning NULL!\n" );
+	DRM_DEBUG("returning NULL!\n");
 	return NULL;
 }
 
-int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
+int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 	drm_mga_freelist_t *head, *entry, *prev;
 
-	DRM_DEBUG( "age=0x%06lx wrap=%d\n",
-		   buf_priv->list_entry->age.head -
-		   dev_priv->primary->offset,
-		   buf_priv->list_entry->age.wrap );
+	DRM_DEBUG("age=0x%06lx wrap=%d\n",
+		  buf_priv->list_entry->age.head -
+		  dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
 
 	entry = buf_priv->list_entry;
 	head = dev_priv->head;
 
-	if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) {
-		SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
+	if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
+		SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
 		prev = dev_priv->tail;
 		prev->next = entry;
 		entry->prev = prev;
@@ -446,43 +437,42 @@ int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
 	return 0;
 }
 
-
 /* ================================================================
  * DMA initialization, cleanup
  */
 
-static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
+static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init)
 {
 	drm_mga_private_t *dev_priv;
 	int ret;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	dev_priv = drm_alloc( sizeof(drm_mga_private_t), DRM_MEM_DRIVER );
-	if ( !dev_priv )
+	dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
+	if (!dev_priv)
 		return DRM_ERR(ENOMEM);
 
-	memset( dev_priv, 0, sizeof(drm_mga_private_t) );
+	memset(dev_priv, 0, sizeof(drm_mga_private_t));
 
 	dev_priv->chipset = init->chipset;
 
 	dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
 
-	if ( init->sgram ) {
+	if (init->sgram) {
 		dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
 	} else {
 		dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
 	}
-	dev_priv->maccess	= init->maccess;
+	dev_priv->maccess = init->maccess;
 
-	dev_priv->fb_cpp	= init->fb_cpp;
-	dev_priv->front_offset	= init->front_offset;
-	dev_priv->front_pitch	= init->front_pitch;
-	dev_priv->back_offset	= init->back_offset;
-	dev_priv->back_pitch	= init->back_pitch;
+	dev_priv->fb_cpp = init->fb_cpp;
+	dev_priv->front_offset = init->front_offset;
+	dev_priv->front_pitch = init->front_pitch;
+	dev_priv->back_offset = init->back_offset;
+	dev_priv->back_pitch = init->back_pitch;
 
-	dev_priv->depth_cpp	= init->depth_cpp;
-	dev_priv->depth_offset	= init->depth_offset;
-	dev_priv->depth_pitch	= init->depth_pitch;
+	dev_priv->depth_cpp = init->depth_cpp;
+	dev_priv->depth_offset = init->depth_offset;
+	dev_priv->depth_pitch = init->depth_pitch;
 
 	/* FIXME: Need to support AGP textures...
 	 */
@@ -491,108 +481,104 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
 
 	DRM_GETSAREA();
 
-	if(!dev_priv->sarea) {
-		DRM_ERROR( "failed to find sarea!\n" );
+	if (!dev_priv->sarea) {
+		DRM_ERROR("failed to find sarea!\n");
 		/* Assign dev_private so we can do cleanup. */
 		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
+		mga_do_cleanup_dma(dev);
 		return DRM_ERR(EINVAL);
 	}
 
 	dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
-	if(!dev_priv->mmio) {
-		DRM_ERROR( "failed to find mmio region!\n" );
+	if (!dev_priv->mmio) {
+		DRM_ERROR("failed to find mmio region!\n");
 		/* Assign dev_private so we can do cleanup. */
 		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
+		mga_do_cleanup_dma(dev);
 		return DRM_ERR(EINVAL);
 	}
 	dev_priv->status = drm_core_findmap(dev, init->status_offset);
-	if(!dev_priv->status) {
-		DRM_ERROR( "failed to find status page!\n" );
+	if (!dev_priv->status) {
+		DRM_ERROR("failed to find status page!\n");
 		/* Assign dev_private so we can do cleanup. */
 		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
+		mga_do_cleanup_dma(dev);
 		return DRM_ERR(EINVAL);
 	}
 	dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
-	if(!dev_priv->warp) {
-		DRM_ERROR( "failed to find warp microcode region!\n" );
+	if (!dev_priv->warp) {
+		DRM_ERROR("failed to find warp microcode region!\n");
 		/* Assign dev_private so we can do cleanup. */
 		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
+		mga_do_cleanup_dma(dev);
 		return DRM_ERR(EINVAL);
 	}
 	dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
-	if(!dev_priv->primary) {
-		DRM_ERROR( "failed to find primary dma region!\n" );
+	if (!dev_priv->primary) {
+		DRM_ERROR("failed to find primary dma region!\n");
 		/* Assign dev_private so we can do cleanup. */
 		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
+		mga_do_cleanup_dma(dev);
 		return DRM_ERR(EINVAL);
 	}
 	dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
-	if(!dev->agp_buffer_map) {
-		DRM_ERROR( "failed to find dma buffer region!\n" );
+	if (!dev->agp_buffer_map) {
+		DRM_ERROR("failed to find dma buffer region!\n");
 		/* Assign dev_private so we can do cleanup. */
 		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
+		mga_do_cleanup_dma(dev);
 		return DRM_ERR(EINVAL);
 	}
 
 	dev_priv->sarea_priv =
-		(drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle +
-				    init->sarea_priv_offset);
+	    (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
+				 init->sarea_priv_offset);
 
-	drm_core_ioremap( dev_priv->warp, dev );
-	drm_core_ioremap( dev_priv->primary, dev );
-	drm_core_ioremap( dev->agp_buffer_map, dev );
+	drm_core_ioremap(dev_priv->warp, dev);
+	drm_core_ioremap(dev_priv->primary, dev);
+	drm_core_ioremap(dev->agp_buffer_map, dev);
 
-	if(!dev_priv->warp->handle ||
-	   !dev_priv->primary->handle ||
-	   !dev->agp_buffer_map->handle ) {
-		DRM_ERROR( "failed to ioremap agp regions!\n" );
+	if (!dev_priv->warp->handle ||
+	    !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
+		DRM_ERROR("failed to ioremap agp regions!\n");
 		/* Assign dev_private so we can do cleanup. */
 		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
+		mga_do_cleanup_dma(dev);
 		return DRM_ERR(ENOMEM);
 	}
 
-	ret = mga_warp_install_microcode( dev_priv );
-	if ( ret < 0 ) {
-		DRM_ERROR( "failed to install WARP ucode!\n" );
+	ret = mga_warp_install_microcode(dev_priv);
+	if (ret < 0) {
+		DRM_ERROR("failed to install WARP ucode!\n");
 		/* Assign dev_private so we can do cleanup. */
 		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
+		mga_do_cleanup_dma(dev);
 		return ret;
 	}
 
-	ret = mga_warp_init( dev_priv );
-	if ( ret < 0 ) {
-		DRM_ERROR( "failed to init WARP engine!\n" );
+	ret = mga_warp_init(dev_priv);
+	if (ret < 0) {
+		DRM_ERROR("failed to init WARP engine!\n");
 		/* Assign dev_private so we can do cleanup. */
 		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
+		mga_do_cleanup_dma(dev);
 		return ret;
 	}
 
-	dev_priv->prim.status = (u32 *)dev_priv->status->handle;
+	dev_priv->prim.status = (u32 *) dev_priv->status->handle;
 
-	mga_do_wait_for_idle( dev_priv );
+	mga_do_wait_for_idle(dev_priv);
 
 	/* Init the primary DMA registers.
 	 */
-	MGA_WRITE( MGA_PRIMADDRESS,
-		   dev_priv->primary->offset | MGA_DMA_GENERAL );
+	MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
 #if 0
-	MGA_WRITE( MGA_PRIMPTR,
-		   virt_to_bus((void *)dev_priv->prim.status) |
-		   MGA_PRIMPTREN0 |	/* Soft trap, SECEND, SETUPEND */
-		   MGA_PRIMPTREN1 );	/* DWGSYNC */
+	MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 |	/* Soft trap, SECEND, SETUPEND */
+		  MGA_PRIMPTREN1);	/* DWGSYNC */
 #endif
 
-	dev_priv->prim.start = (u8 *)dev_priv->primary->handle;
-	dev_priv->prim.end = ((u8 *)dev_priv->primary->handle
+	dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
+	dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
 			      + dev_priv->primary->size);
 	dev_priv->prim.size = dev_priv->primary->size;
 
@@ -612,11 +598,11 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
 	dev_priv->sarea_priv->last_frame.head = 0;
 	dev_priv->sarea_priv->last_frame.wrap = 0;
 
-	if ( mga_freelist_init( dev, dev_priv ) < 0 ) {
-		DRM_ERROR( "could not initialize freelist\n" );
+	if (mga_freelist_init(dev, dev_priv) < 0) {
+		DRM_ERROR("could not initialize freelist\n");
 		/* Assign dev_private so we can do cleanup. */
 		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
+		mga_do_cleanup_dma(dev);
 		return DRM_ERR(ENOMEM);
 	}
 
@@ -625,131 +611,132 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
 	return 0;
 }
 
-int mga_do_cleanup_dma( drm_device_t *dev )
+int mga_do_cleanup_dma(drm_device_t * dev)
 {
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	/* Make sure interrupts are disabled here because the uninstall ioctl
 	 * may not have been called from userspace and after dev_private
 	 * is freed, it's too late.
 	 */
-	if ( dev->irq_enabled ) drm_irq_uninstall(dev);
+	if (dev->irq_enabled)
+		drm_irq_uninstall(dev);
 
-	if ( dev->dev_private ) {
+	if (dev->dev_private) {
 		drm_mga_private_t *dev_priv = dev->dev_private;
 
-		if ( dev_priv->warp != NULL )
-			drm_core_ioremapfree( dev_priv->warp, dev );
-		if ( dev_priv->primary != NULL )
-			drm_core_ioremapfree( dev_priv->primary, dev );
-		if ( dev->agp_buffer_map != NULL ) {
-			drm_core_ioremapfree( dev->agp_buffer_map, dev );
+		if (dev_priv->warp != NULL)
+			drm_core_ioremapfree(dev_priv->warp, dev);
+		if (dev_priv->primary != NULL)
+			drm_core_ioremapfree(dev_priv->primary, dev);
+		if (dev->agp_buffer_map != NULL) {
+			drm_core_ioremapfree(dev->agp_buffer_map, dev);
 			dev->agp_buffer_map = NULL;
 		}
 
-		if ( dev_priv->head != NULL ) {
-			mga_freelist_cleanup( dev );
+		if (dev_priv->head != NULL) {
+			mga_freelist_cleanup(dev);
 		}
 
-		drm_free( dev->dev_private, sizeof(drm_mga_private_t),
-			   DRM_MEM_DRIVER );
+		drm_free(dev->dev_private, sizeof(drm_mga_private_t),
+			 DRM_MEM_DRIVER);
 		dev->dev_private = NULL;
 	}
 
 	return 0;
 }
 
-int mga_dma_init( DRM_IOCTL_ARGS )
+int mga_dma_init(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mga_init_t init;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( init, (drm_mga_init_t __user *)data, sizeof(init) );
+	DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data,
+				 sizeof(init));
 
-	switch ( init.func ) {
+	switch (init.func) {
 	case MGA_INIT_DMA:
-		return mga_do_init_dma( dev, &init );
+		return mga_do_init_dma(dev, &init);
 	case MGA_CLEANUP_DMA:
-		return mga_do_cleanup_dma( dev );
+		return mga_do_cleanup_dma(dev);
 	}
 
 	return DRM_ERR(EINVAL);
 }
 
-
 /* ================================================================
  * Primary DMA stream management
  */
 
-int mga_dma_flush( DRM_IOCTL_ARGS )
+int mga_dma_flush(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
-	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
 	drm_lock_t lock;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t __user *)data, sizeof(lock) );
+	DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data,
+				 sizeof(lock));
 
-	DRM_DEBUG( "%s%s%s\n",
-		   (lock.flags & _DRM_LOCK_FLUSH) ?	"flush, " : "",
-		   (lock.flags & _DRM_LOCK_FLUSH_ALL) ?	"flush all, " : "",
-		   (lock.flags & _DRM_LOCK_QUIESCENT) ?	"idle, " : "" );
+	DRM_DEBUG("%s%s%s\n",
+		  (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
+		  (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
+		  (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
 
-	WRAP_WAIT_WITH_RETURN( dev_priv );
+	WRAP_WAIT_WITH_RETURN(dev_priv);
 
-	if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) {
-		mga_do_dma_flush( dev_priv );
+	if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
+		mga_do_dma_flush(dev_priv);
 	}
 
-	if ( lock.flags & _DRM_LOCK_QUIESCENT ) {
+	if (lock.flags & _DRM_LOCK_QUIESCENT) {
 #if MGA_DMA_DEBUG
-		int ret = mga_do_wait_for_idle( dev_priv );
-		if ( ret < 0 )
-			DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ );
+		int ret = mga_do_wait_for_idle(dev_priv);
+		if (ret < 0)
+			DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
 		return ret;
 #else
-		return mga_do_wait_for_idle( dev_priv );
+		return mga_do_wait_for_idle(dev_priv);
 #endif
 	} else {
 		return 0;
 	}
 }
 
-int mga_dma_reset( DRM_IOCTL_ARGS )
+int mga_dma_reset(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
-	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	return mga_do_dma_reset( dev_priv );
+	return mga_do_dma_reset(dev_priv);
 }
 
-
 /* ================================================================
  * DMA buffer management
  */
 
-static int mga_dma_get_buffers( DRMFILE filp,
-				drm_device_t *dev, drm_dma_t *d )
+static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
 {
 	drm_buf_t *buf;
 	int i;
 
-	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
-		buf = mga_freelist_get( dev );
-		if ( !buf ) return DRM_ERR(EAGAIN);
+	for (i = d->granted_count; i < d->request_count; i++) {
+		buf = mga_freelist_get(dev);
+		if (!buf)
+			return DRM_ERR(EAGAIN);
 
 		buf->filp = filp;
 
-		if ( DRM_COPY_TO_USER( &d->request_indices[i],
-				   &buf->idx, sizeof(buf->idx) ) )
+		if (DRM_COPY_TO_USER(&d->request_indices[i],
+				     &buf->idx, sizeof(buf->idx)))
 			return DRM_ERR(EFAULT);
-		if ( DRM_COPY_TO_USER( &d->request_sizes[i],
-				   &buf->total, sizeof(buf->total) ) )
+		if (DRM_COPY_TO_USER(&d->request_sizes[i],
+				     &buf->total, sizeof(buf->total)))
 			return DRM_ERR(EFAULT);
 
 		d->granted_count++;
@@ -757,55 +744,55 @@ static int mga_dma_get_buffers( DRMFILE filp,
 	return 0;
 }
 
-int mga_dma_buffers( DRM_IOCTL_ARGS )
+int mga_dma_buffers(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_device_dma_t *dma = dev->dma;
-	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
 	drm_dma_t __user *argp = (void __user *)data;
 	drm_dma_t d;
 	int ret = 0;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
+	DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
 
 	/* Please don't send us buffers.
 	 */
-	if ( d.send_count != 0 ) {
-		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
-			   DRM_CURRENTPID, d.send_count );
+	if (d.send_count != 0) {
+		DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
+			  DRM_CURRENTPID, d.send_count);
 		return DRM_ERR(EINVAL);
 	}
 
 	/* We'll send you buffers.
 	 */
-	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
-		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
-			   DRM_CURRENTPID, d.request_count, dma->buf_count );
+	if (d.request_count < 0 || d.request_count > dma->buf_count) {
+		DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
+			  DRM_CURRENTPID, d.request_count, dma->buf_count);
 		return DRM_ERR(EINVAL);
 	}
 
-	WRAP_TEST_WITH_RETURN( dev_priv );
+	WRAP_TEST_WITH_RETURN(dev_priv);
 
 	d.granted_count = 0;
 
-	if ( d.request_count ) {
-		ret = mga_dma_get_buffers( filp, dev, &d );
+	if (d.request_count) {
+		ret = mga_dma_get_buffers(filp, dev, &d);
 	}
 
-	DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
+	DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
 
 	return ret;
 }
 
-void mga_driver_pretakedown(drm_device_t *dev)
+void mga_driver_pretakedown(drm_device_t * dev)
 {
-	mga_do_cleanup_dma( dev );
+	mga_do_cleanup_dma(dev);
 }
 
-int mga_driver_dma_quiescent(drm_device_t *dev)
+int mga_driver_dma_quiescent(drm_device_t * dev)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
-	return mga_do_wait_for_idle( dev_priv );
+	return mga_do_wait_for_idle(dev_priv);
 }
diff --git a/shared-core/mga_drm.h b/shared-core/mga_drm.h
index 521d4451..40f06c36 100644
--- a/shared-core/mga_drm.h
+++ b/shared-core/mga_drm.h
@@ -44,10 +44,10 @@
 
 /* WARP pipe flags
  */
-#define MGA_F			0x1		/* fog */
-#define MGA_A			0x2		/* alpha */
-#define MGA_S			0x4		/* specular */
-#define MGA_T2			0x8		/* multitexture */
+#define MGA_F			0x1	/* fog */
+#define MGA_A			0x2	/* alpha */
+#define MGA_S			0x4	/* specular */
+#define MGA_T2			0x8	/* multitexture */
 
 #define MGA_WARP_TGZ		0
 #define MGA_WARP_TGZF		(MGA_F)
@@ -66,15 +66,14 @@
 #define MGA_WARP_T2GZSA		(MGA_T2|MGA_S|MGA_A)
 #define MGA_WARP_T2GZSAF	(MGA_T2|MGA_S|MGA_F|MGA_A)
 
-#define MGA_MAX_G200_PIPES	8		/* no multitex */
+#define MGA_MAX_G200_PIPES	8	/* no multitex */
 #define MGA_MAX_G400_PIPES	16
 #define MGA_MAX_WARP_PIPES	MGA_MAX_G400_PIPES
-#define MGA_WARP_UCODE_SIZE	32768		/* in bytes */
+#define MGA_WARP_UCODE_SIZE	32768	/* in bytes */
 
 #define MGA_CARD_TYPE_G200	1
 #define MGA_CARD_TYPE_G400	2
 
-
 #define MGA_FRONT		0x1
 #define MGA_BACK		0x2
 #define MGA_DEPTH		0x4
@@ -85,14 +84,14 @@
 #define MGA_UPLOAD_TEX0		0x2
 #define MGA_UPLOAD_TEX1		0x4
 #define MGA_UPLOAD_PIPE		0x8
-#define MGA_UPLOAD_TEX0IMAGE	0x10 /* handled client-side */
-#define MGA_UPLOAD_TEX1IMAGE	0x20 /* handled client-side */
+#define MGA_UPLOAD_TEX0IMAGE	0x10	/* handled client-side */
+#define MGA_UPLOAD_TEX1IMAGE	0x20	/* handled client-side */
 #define MGA_UPLOAD_2D		0x40
-#define MGA_WAIT_AGE		0x80 /* handled client-side */
-#define MGA_UPLOAD_CLIPRECTS	0x100 /* handled client-side */
+#define MGA_WAIT_AGE		0x80	/* handled client-side */
+#define MGA_UPLOAD_CLIPRECTS	0x100	/* handled client-side */
 #if 0
-#define MGA_DMA_FLUSH		0x200 /* set when someone gets the lock
-					 quiescent */
+#define MGA_DMA_FLUSH		0x200	/* set when someone gets the lock
+					   quiescent */
 #endif
 
 /* 32 buffers of 64k each, total 2 meg.
@@ -119,8 +118,7 @@
 
 #define  DRM_MGA_IDLE_RETRY          2048
 
-#endif /* __MGA_SAREA_DEFINES__ */
-
+#endif				/* __MGA_SAREA_DEFINES__ */
 
 /* Setup registers for 3D context
  */
@@ -164,25 +162,25 @@ typedef struct {
 /* General aging mechanism
  */
 typedef struct {
-	unsigned int head;		/* Position of head pointer          */
-	unsigned int wrap;		/* Primary DMA wrap count            */
+	unsigned int head;	/* Position of head pointer          */
+	unsigned int wrap;	/* Primary DMA wrap count            */
 } drm_mga_age_t;
 
 typedef struct _drm_mga_sarea {
 	/* The channel for communication of state information to the kernel
 	 * on firing a vertex dma buffer.
 	 */
-   	drm_mga_context_regs_t context_state;
-   	drm_mga_server_regs_t server_state;
-   	drm_mga_texture_regs_t tex_state[2];
-   	unsigned int warp_pipe;
-   	unsigned int dirty;
-   	unsigned int vertsize;
+	drm_mga_context_regs_t context_state;
+	drm_mga_server_regs_t server_state;
+	drm_mga_texture_regs_t tex_state[2];
+	unsigned int warp_pipe;
+	unsigned int dirty;
+	unsigned int vertsize;
 
 	/* The current cliprects, or a subset thereof.
 	 */
-   	drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
-   	unsigned int nbox;
+	drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
+	unsigned int nbox;
 
 	/* Information about the most recently used 3d drawable.  The
 	 * client fills in the req_* fields, the server fills in the
@@ -191,18 +189,18 @@ typedef struct _drm_mga_sarea {
 	 * The client clears the exported_drawable field before
 	 * clobbering the boxes data.
 	 */
-        unsigned int req_drawable;	 /* the X drawable id */
-	unsigned int req_draw_buffer;	 /* MGA_FRONT or MGA_BACK */
+	unsigned int req_drawable;	/* the X drawable id */
+	unsigned int req_draw_buffer;	/* MGA_FRONT or MGA_BACK */
 
-        unsigned int exported_drawable;
+	unsigned int exported_drawable;
 	unsigned int exported_index;
-        unsigned int exported_stamp;
-        unsigned int exported_buffers;
-        unsigned int exported_nfront;
-        unsigned int exported_nback;
+	unsigned int exported_stamp;
+	unsigned int exported_buffers;
+	unsigned int exported_nfront;
+	unsigned int exported_nback;
 	int exported_back_x, exported_front_x, exported_w;
 	int exported_back_y, exported_front_y, exported_h;
-   	drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
+	drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
 
 	/* Counters for aging textures and for client-side throttling.
 	 */
@@ -210,21 +208,20 @@ typedef struct _drm_mga_sarea {
 	unsigned int last_wrap;
 
 	drm_mga_age_t last_frame;
-        unsigned int last_enqueue;	/* last time a buffer was enqueued */
+	unsigned int last_enqueue;	/* last time a buffer was enqueued */
 	unsigned int last_dispatch;	/* age of the most recently dispatched buffer */
-	unsigned int last_quiescent;     /*  */
+	unsigned int last_quiescent;	/*  */
 
 	/* LRU lists for texture memory in agp space and on the card.
 	 */
-	drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1];
+	drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
 	unsigned int texAge[MGA_NR_TEX_HEAPS];
 
 	/* Mechanism to validate card state.
 	 */
-   	int ctxOwner;
+	int ctxOwner;
 } drm_mga_sarea_t;
 
-
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (xf86drmMga.h)
  */
@@ -255,33 +252,33 @@ typedef struct _drm_mga_sarea {
 #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
 
 typedef struct _drm_mga_warp_index {
-   	int installed;
-   	unsigned long phys_addr;
-   	int size;
+	int installed;
+	unsigned long phys_addr;
+	int size;
 } drm_mga_warp_index_t;
 
 typedef struct drm_mga_init {
-   	enum {
-	   	MGA_INIT_DMA    = 0x01,
-	       	MGA_CLEANUP_DMA = 0x02
+	enum {
+		MGA_INIT_DMA = 0x01,
+		MGA_CLEANUP_DMA = 0x02
 	} func;
 
-   	unsigned long sarea_priv_offset;
+	unsigned long sarea_priv_offset;
 
 	int chipset;
-   	int sgram;
+	int sgram;
 
 	unsigned int maccess;
 
-   	unsigned int fb_cpp;
+	unsigned int fb_cpp;
 	unsigned int front_offset, front_pitch;
-   	unsigned int back_offset, back_pitch;
+	unsigned int back_offset, back_pitch;
 
-   	unsigned int depth_cpp;
-   	unsigned int depth_offset, depth_pitch;
+	unsigned int depth_cpp;
+	unsigned int depth_offset, depth_pitch;
 
-   	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
-   	unsigned int texture_size[MGA_NR_TEX_HEAPS];
+	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
+	unsigned int texture_size[MGA_NR_TEX_HEAPS];
 
 	unsigned long fb_offset;
 	unsigned long mmio_offset;
@@ -293,7 +290,7 @@ typedef struct drm_mga_init {
 
 typedef struct drm_mga_fullscreen {
 	enum {
-		MGA_INIT_FULLSCREEN    = 0x01,
+		MGA_INIT_FULLSCREEN = 0x01,
 		MGA_CLEANUP_FULLSCREEN = 0x02
 	} func;
 } drm_mga_fullscreen_t;
@@ -307,16 +304,16 @@ typedef struct drm_mga_clear {
 } drm_mga_clear_t;
 
 typedef struct drm_mga_vertex {
-   	int idx;			/* buffer to queue */
-	int used;			/* bytes in use */
-	int discard;			/* client finished with buffer?  */
+	int idx;		/* buffer to queue */
+	int used;		/* bytes in use */
+	int discard;		/* client finished with buffer?  */
 } drm_mga_vertex_t;
 
 typedef struct drm_mga_indices {
-   	int idx;			/* buffer to queue */
+	int idx;		/* buffer to queue */
 	unsigned int start;
 	unsigned int end;
-	int discard;			/* client finished with buffer?  */
+	int discard;		/* client finished with buffer?  */
 } drm_mga_indices_t;
 
 typedef struct drm_mga_iload {
@@ -332,12 +329,12 @@ typedef struct _drm_mga_blit {
 	int src_pitch, dst_pitch;
 	int delta_sx, delta_sy;
 	int delta_dx, delta_dy;
-	int height, ydir;		/* flip image vertically */
+	int height, ydir;	/* flip image vertically */
 	int source_pitch, dest_pitch;
 } drm_mga_blit_t;
 
 /* 3.1: An ioctl to get parameters that aren't available to the 3d
- * client any other way.  
+ * client any other way.
  */
 #define MGA_PARAM_IRQ_NR            1
 
diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h
index 3d8e9aef..a00fb421 100644
--- a/shared-core/mga_drv.h
+++ b/shared-core/mga_drv.h
@@ -62,14 +62,14 @@ typedef struct drm_mga_primary_buffer {
 } drm_mga_primary_buffer_t;
 
 typedef struct drm_mga_freelist {
-   	struct drm_mga_freelist *next;
-   	struct drm_mga_freelist *prev;
+	struct drm_mga_freelist *next;
+	struct drm_mga_freelist *prev;
 	drm_mga_age_t age;
-   	drm_buf_t *buf;
+	drm_buf_t *buf;
 } drm_mga_freelist_t;
 
 typedef struct {
-   	drm_mga_freelist_t *list_entry;
+	drm_mga_freelist_t *list_entry;
 	int discard;
 	int dispatched;
 } drm_mga_buf_priv_t;
@@ -78,8 +78,8 @@ typedef struct drm_mga_private {
 	drm_mga_primary_buffer_t prim;
 	drm_mga_sarea_t *sarea_priv;
 
-   	drm_mga_freelist_t *head;
-   	drm_mga_freelist_t *tail;
+	drm_mga_freelist_t *head;
+	drm_mga_freelist_t *tail;
 
 	unsigned int warp_pipe;
 	unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
@@ -113,43 +113,43 @@ typedef struct drm_mga_private {
 } drm_mga_private_t;
 
 				/* mga_dma.c */
-extern int mga_dma_init( DRM_IOCTL_ARGS );
-extern int mga_dma_flush( DRM_IOCTL_ARGS );
-extern int mga_dma_reset( DRM_IOCTL_ARGS );
-extern int mga_dma_buffers( DRM_IOCTL_ARGS );
-extern void mga_driver_pretakedown(drm_device_t *dev);
-extern int mga_driver_dma_quiescent(drm_device_t *dev);
+extern int mga_dma_init(DRM_IOCTL_ARGS);
+extern int mga_dma_flush(DRM_IOCTL_ARGS);
+extern int mga_dma_reset(DRM_IOCTL_ARGS);
+extern int mga_dma_buffers(DRM_IOCTL_ARGS);
+extern void mga_driver_pretakedown(drm_device_t * dev);
+extern int mga_driver_dma_quiescent(drm_device_t * dev);
 
-extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
-extern int mga_do_dma_idle( drm_mga_private_t *dev_priv );
-extern int mga_do_dma_reset( drm_mga_private_t *dev_priv );
-extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
-extern int mga_do_cleanup_dma( drm_device_t *dev );
+extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv);
+extern int mga_do_dma_idle(drm_mga_private_t * dev_priv);
+extern int mga_do_dma_reset(drm_mga_private_t * dev_priv);
+extern int mga_do_engine_reset(drm_mga_private_t * dev_priv);
+extern int mga_do_cleanup_dma(drm_device_t * dev);
 
-extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
-extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
-extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
+extern void mga_do_dma_flush(drm_mga_private_t * dev_priv);
+extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv);
+extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv);
 
-extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
+extern int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf);
 
 				/* mga_state.c */
-extern int  mga_dma_clear( DRM_IOCTL_ARGS );
-extern int  mga_dma_swap( DRM_IOCTL_ARGS );
-extern int  mga_dma_vertex( DRM_IOCTL_ARGS );
-extern int  mga_dma_indices( DRM_IOCTL_ARGS );
-extern int  mga_dma_iload( DRM_IOCTL_ARGS );
-extern int  mga_dma_blit( DRM_IOCTL_ARGS );
-extern int  mga_getparam( DRM_IOCTL_ARGS );
+extern int mga_dma_clear(DRM_IOCTL_ARGS);
+extern int mga_dma_swap(DRM_IOCTL_ARGS);
+extern int mga_dma_vertex(DRM_IOCTL_ARGS);
+extern int mga_dma_indices(DRM_IOCTL_ARGS);
+extern int mga_dma_iload(DRM_IOCTL_ARGS);
+extern int mga_dma_blit(DRM_IOCTL_ARGS);
+extern int mga_getparam(DRM_IOCTL_ARGS);
 
 				/* mga_warp.c */
-extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
-extern int mga_warp_init( drm_mga_private_t *dev_priv );
+extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv);
+extern int mga_warp_init(drm_mga_private_t * dev_priv);
 
-extern int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
-extern irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS );
-extern void mga_driver_irq_preinstall( drm_device_t *dev );
-extern void mga_driver_irq_postinstall( drm_device_t *dev );
-extern void mga_driver_irq_uninstall( drm_device_t *dev );
+extern int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence);
+extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS);
+extern void mga_driver_irq_preinstall(drm_device_t * dev);
+extern void mga_driver_irq_postinstall(drm_device_t * dev);
+extern void mga_driver_irq_uninstall(drm_device_t * dev);
 
 #define mga_flush_write_combine()	DRM_WRITEMEMORYBARRIER()
 
@@ -165,7 +165,7 @@ extern void mga_driver_irq_uninstall( drm_device_t *dev );
 #define MGA_WRITE( reg, val )	do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
 #define MGA_WRITE8( reg, val )  do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
 
-static inline u32 _MGA_READ(u32 *addr)
+static inline u32 _MGA_READ(u32 * addr)
 {
 	DRM_MEMORYBARRIER();
 	return *(volatile u32 *)addr;
@@ -187,8 +187,6 @@ static inline u32 _MGA_READ(u32 *addr)
 #define DMAREG1(r)	(u8)(((r - DWGREG1) >> 2) | 0x80)
 #define DMAREG(r)	(ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
 
-
-
 /* ================================================================
  * Helper macross...
  */
@@ -230,7 +228,6 @@ do {									\
 	}								\
 } while (0)
 
-
 /* ================================================================
  * Primary DMA command stream
  */
@@ -315,7 +312,6 @@ do {									\
 	write += DMA_BLOCK_SIZE;					\
 } while (0)
 
-
 /* Buffer aging via primary DMA stream head pointer.
  */
 
@@ -342,7 +338,6 @@ do {									\
 	}								\
 } while (0)
 
-
 #define MGA_ENGINE_IDLE_MASK		(MGA_SOFTRAPEN |		\
 					 MGA_DWGENGSTS |		\
 					 MGA_ENDPRDMASTS)
@@ -351,8 +346,6 @@ do {									\
 
 #define MGA_DMA_DEBUG			0
 
-
-
 /* A reduced set of the mga registers.
  */
 #define MGA_CRTC_INDEX			0x1fd4
@@ -607,7 +600,6 @@ do {									\
 #	define MGA_G400_WR_MAGIC		(1 << 6)
 #	define MGA_G400_WR56_MAGIC		0x46480000	/* 12800.0f */
 
-
 #define MGA_ILOAD_ALIGN		64
 #define MGA_ILOAD_MASK		(MGA_ILOAD_ALIGN - 1)
 
@@ -642,10 +634,10 @@ do {									\
 
 /* Simple idle test.
  */
-static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv )
+static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv)
 {
-	u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
-	return ( status == MGA_ENDPRDMASTS );
+	u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
+	return (status == MGA_ENDPRDMASTS);
 }
 
 #endif
diff --git a/shared-core/mga_irq.c b/shared-core/mga_irq.c
index bc0b6b5d..704652d3 100644
--- a/shared-core/mga_irq.c
+++ b/shared-core/mga_irq.c
@@ -1,7 +1,7 @@
 /* mga_irq.c -- IRQ handling for radeon -*- linux-c -*-
  *
  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
- * 
+ *
  * The Weather Channel (TM) funded Tungsten Graphics to develop the
  * initial release of the Radeon 8500 driver under the XFree86 license.
  * This notice must be preserved.
@@ -35,68 +35,67 @@
 #include "mga_drm.h"
 #include "mga_drv.h"
 
-irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS )
+irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS)
 {
 	drm_device_t *dev = (drm_device_t *) arg;
-	drm_mga_private_t *dev_priv = 
-	   (drm_mga_private_t *)dev->dev_private;
+	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
 	int status;
 
-	status = MGA_READ( MGA_STATUS );
-	
+	status = MGA_READ(MGA_STATUS);
+
 	/* VBLANK interrupt */
-	if ( status & MGA_VLINEPEN ) {
-		MGA_WRITE( MGA_ICLEAR, MGA_VLINEICLR );
+	if (status & MGA_VLINEPEN) {
+		MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR);
 		atomic_inc(&dev->vbl_received);
 		DRM_WAKEUP(&dev->vbl_queue);
-		drm_vbl_send_signals( dev );
+		drm_vbl_send_signals(dev);
 		return IRQ_HANDLED;
 	}
 	return IRQ_NONE;
 }
 
-int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
+int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
 {
 	unsigned int cur_vblank;
 	int ret = 0;
 
 	/* Assume that the user has missed the current sequence number
 	 * by about a day rather than she wants to wait for years
-	 * using vertical blanks... 
+	 * using vertical blanks...
 	 */
-	DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, 
-		     ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
-			 - *sequence ) <= (1<<23) ) );
+	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
+		    (((cur_vblank = atomic_read(&dev->vbl_received))
+		      - *sequence) <= (1 << 23)));
 
 	*sequence = cur_vblank;
 
 	return ret;
 }
 
-void mga_driver_irq_preinstall( drm_device_t *dev ) {
-  	drm_mga_private_t *dev_priv = 
-	   (drm_mga_private_t *)dev->dev_private;
+void mga_driver_irq_preinstall(drm_device_t * dev)
+{
+	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
 
 	/* Disable *all* interrupts */
-      	MGA_WRITE( MGA_IEN, 0 );
+	MGA_WRITE(MGA_IEN, 0);
 	/* Clear bits if they're already high */
-   	MGA_WRITE( MGA_ICLEAR, ~0 );
+	MGA_WRITE(MGA_ICLEAR, ~0);
 }
 
-void mga_driver_irq_postinstall( drm_device_t *dev ) {
-  	drm_mga_private_t *dev_priv = 
-	   (drm_mga_private_t *)dev->dev_private;
+void mga_driver_irq_postinstall(drm_device_t * dev)
+{
+	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
 
 	/* Turn on VBL interrupt */
-   	MGA_WRITE( MGA_IEN, MGA_VLINEIEN );
+	MGA_WRITE(MGA_IEN, MGA_VLINEIEN);
 }
 
-void mga_driver_irq_uninstall( drm_device_t *dev ) {
-  	drm_mga_private_t *dev_priv = 
-	   (drm_mga_private_t *)dev->dev_private;
+void mga_driver_irq_uninstall(drm_device_t * dev)
+{
+	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
 	if (!dev_priv)
 		return;
 
 	/* Disable *all* interrupts */
-	MGA_WRITE( MGA_IEN, 0 );
+	MGA_WRITE(MGA_IEN, 0);
 }
diff --git a/shared-core/mga_state.c b/shared-core/mga_state.c
index f676e974..59d87a23 100644
--- a/shared-core/mga_state.c
+++ b/shared-core/mga_state.c
@@ -37,126 +37,114 @@
 #include "mga_drm.h"
 #include "mga_drv.h"
 
-
 /* ================================================================
  * DMA hardware state programming functions
  */
 
-static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
-				drm_clip_rect_t *box )
+static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
+			       drm_clip_rect_t * box)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 	unsigned int pitch = dev_priv->front_pitch;
 	DMA_LOCALS;
 
-	BEGIN_DMA( 2 );
+	BEGIN_DMA(2);
 
 	/* Force reset of DWGCTL on G400 (eliminates clip disable bit).
 	 */
-	if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
-		DMA_BLOCK( MGA_DWGCTL,		ctx->dwgctl,
-			   MGA_LEN + MGA_EXEC,	0x80000000,
-			   MGA_DWGCTL,		ctx->dwgctl,
-			   MGA_LEN + MGA_EXEC,	0x80000000 );
+	if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
+		DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
+			  MGA_LEN + MGA_EXEC, 0x80000000,
+			  MGA_DWGCTL, ctx->dwgctl,
+			  MGA_LEN + MGA_EXEC, 0x80000000);
 	}
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_CXBNDRY,	(box->x2 << 16) | box->x1,
-		   MGA_YTOP,	box->y1 * pitch,
-		   MGA_YBOT,	box->y2 * pitch );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_CXBNDRY, (box->x2 << 16) | box->x1,
+		  MGA_YTOP, box->y1 * pitch, MGA_YBOT, box->y2 * pitch);
 
 	ADVANCE_DMA();
 }
 
-static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv )
+static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 	DMA_LOCALS;
 
-	BEGIN_DMA( 3 );
+	BEGIN_DMA(3);
 
-	DMA_BLOCK( MGA_DSTORG,		ctx->dstorg,
-		   MGA_MACCESS,		ctx->maccess,
-		   MGA_PLNWT,		ctx->plnwt,
-		   MGA_DWGCTL,		ctx->dwgctl );
+	DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
+		  MGA_MACCESS, ctx->maccess,
+		  MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
 
-	DMA_BLOCK( MGA_ALPHACTRL,	ctx->alphactrl,
-		   MGA_FOGCOL,		ctx->fogcolor,
-		   MGA_WFLAG,		ctx->wflag,
-		   MGA_ZORG,		dev_priv->depth_offset );
+	DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
+		  MGA_FOGCOL, ctx->fogcolor,
+		  MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
 
-	DMA_BLOCK( MGA_FCOL,		ctx->fcol,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000 );
+	DMA_BLOCK(MGA_FCOL, ctx->fcol,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 
 	ADVANCE_DMA();
 }
 
-static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv )
+static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 	DMA_LOCALS;
 
-	BEGIN_DMA( 4 );
+	BEGIN_DMA(4);
 
-	DMA_BLOCK( MGA_DSTORG,		ctx->dstorg,
-		   MGA_MACCESS,		ctx->maccess,
-		   MGA_PLNWT,		ctx->plnwt,
-		   MGA_DWGCTL,		ctx->dwgctl );
+	DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
+		  MGA_MACCESS, ctx->maccess,
+		  MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
 
-	DMA_BLOCK( MGA_ALPHACTRL,	ctx->alphactrl,
-		   MGA_FOGCOL,		ctx->fogcolor,
-		   MGA_WFLAG,		ctx->wflag,
-		   MGA_ZORG,		dev_priv->depth_offset );
+	DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
+		  MGA_FOGCOL, ctx->fogcolor,
+		  MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
 
-	DMA_BLOCK( MGA_WFLAG1,		ctx->wflag,
-		   MGA_TDUALSTAGE0,	ctx->tdualstage0,
-		   MGA_TDUALSTAGE1,	ctx->tdualstage1,
-		   MGA_FCOL,		ctx->fcol );
+	DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
+		  MGA_TDUALSTAGE0, ctx->tdualstage0,
+		  MGA_TDUALSTAGE1, ctx->tdualstage1, MGA_FCOL, ctx->fcol);
 
-	DMA_BLOCK( MGA_STENCIL,		ctx->stencil,
-		   MGA_STENCILCTL,	ctx->stencilctl,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000 );
+	DMA_BLOCK(MGA_STENCIL, ctx->stencil,
+		  MGA_STENCILCTL, ctx->stencilctl,
+		  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 
 	ADVANCE_DMA();
 }
 
-static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv )
+static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
 	DMA_LOCALS;
 
-	BEGIN_DMA( 4 );
+	BEGIN_DMA(4);
 
-	DMA_BLOCK( MGA_TEXCTL2,		tex->texctl2,
-		   MGA_TEXCTL,		tex->texctl,
-		   MGA_TEXFILTER,	tex->texfilter,
-		   MGA_TEXBORDERCOL,	tex->texbordercol );
+	DMA_BLOCK(MGA_TEXCTL2, tex->texctl2,
+		  MGA_TEXCTL, tex->texctl,
+		  MGA_TEXFILTER, tex->texfilter,
+		  MGA_TEXBORDERCOL, tex->texbordercol);
 
-	DMA_BLOCK( MGA_TEXORG,		tex->texorg,
-		   MGA_TEXORG1,		tex->texorg1,
-		   MGA_TEXORG2,		tex->texorg2,
-		   MGA_TEXORG3,		tex->texorg3 );
+	DMA_BLOCK(MGA_TEXORG, tex->texorg,
+		  MGA_TEXORG1, tex->texorg1,
+		  MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3);
 
-	DMA_BLOCK( MGA_TEXORG4,		tex->texorg4,
-		   MGA_TEXWIDTH,	tex->texwidth,
-		   MGA_TEXHEIGHT,	tex->texheight,
-		   MGA_WR24,		tex->texwidth );
+	DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
+		  MGA_TEXWIDTH, tex->texwidth,
+		  MGA_TEXHEIGHT, tex->texheight, MGA_WR24, tex->texwidth);
 
-	DMA_BLOCK( MGA_WR34,		tex->texheight,
-		   MGA_TEXTRANS,	0x0000ffff,
-		   MGA_TEXTRANSHIGH,	0x0000ffff,
-		   MGA_DMAPAD,		0x00000000 );
+	DMA_BLOCK(MGA_WR34, tex->texheight,
+		  MGA_TEXTRANS, 0x0000ffff,
+		  MGA_TEXTRANSHIGH, 0x0000ffff, MGA_DMAPAD, 0x00000000);
 
 	ADVANCE_DMA();
 }
 
-static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
+static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
@@ -165,42 +153,38 @@ static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
 /*  	printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
 /*  	       tex->texctl, tex->texctl2); */
 
-	BEGIN_DMA( 6 );
+	BEGIN_DMA(6);
 
-	DMA_BLOCK( MGA_TEXCTL2,		tex->texctl2 | MGA_G400_TC2_MAGIC,
-		   MGA_TEXCTL,		tex->texctl,
-		   MGA_TEXFILTER,	tex->texfilter,
-		   MGA_TEXBORDERCOL,	tex->texbordercol );
+	DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
+		  MGA_TEXCTL, tex->texctl,
+		  MGA_TEXFILTER, tex->texfilter,
+		  MGA_TEXBORDERCOL, tex->texbordercol);
 
-	DMA_BLOCK( MGA_TEXORG,		tex->texorg,
-		   MGA_TEXORG1,		tex->texorg1,
-		   MGA_TEXORG2,		tex->texorg2,
-		   MGA_TEXORG3,		tex->texorg3 );
+	DMA_BLOCK(MGA_TEXORG, tex->texorg,
+		  MGA_TEXORG1, tex->texorg1,
+		  MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3);
 
-	DMA_BLOCK( MGA_TEXORG4,		tex->texorg4,
-		   MGA_TEXWIDTH,	tex->texwidth,
-		   MGA_TEXHEIGHT,	tex->texheight,
-		   MGA_WR49,		0x00000000 );
+	DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
+		  MGA_TEXWIDTH, tex->texwidth,
+		  MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000);
 
-	DMA_BLOCK( MGA_WR57,		0x00000000,
-		   MGA_WR53,		0x00000000,
-		   MGA_WR61,		0x00000000,
-		   MGA_WR52,		MGA_G400_WR_MAGIC );
+	DMA_BLOCK(MGA_WR57, 0x00000000,
+		  MGA_WR53, 0x00000000,
+		  MGA_WR61, 0x00000000, MGA_WR52, MGA_G400_WR_MAGIC);
 
-	DMA_BLOCK( MGA_WR60,		MGA_G400_WR_MAGIC,
-		   MGA_WR54,		tex->texwidth | MGA_G400_WR_MAGIC,
-		   MGA_WR62,		tex->texheight | MGA_G400_WR_MAGIC,
-		   MGA_DMAPAD,		0x00000000 );
+	DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC,
+		  MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
+		  MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
+		  MGA_DMAPAD, 0x00000000);
 
-	DMA_BLOCK( MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_TEXTRANS,	0x0000ffff,
-		   MGA_TEXTRANSHIGH,	0x0000ffff );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_TEXTRANS, 0x0000ffff, MGA_TEXTRANSHIGH, 0x0000ffff);
 
 	ADVANCE_DMA();
 }
 
-static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
+static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
@@ -209,69 +193,64 @@ static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
 /*  	printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg,  */
 /*  	       tex->texctl, tex->texctl2); */
 
-	BEGIN_DMA( 5 );
+	BEGIN_DMA(5);
 
-	DMA_BLOCK( MGA_TEXCTL2,		(tex->texctl2 |
-					 MGA_MAP1_ENABLE |
-					 MGA_G400_TC2_MAGIC),
-		   MGA_TEXCTL,		tex->texctl,
-		   MGA_TEXFILTER,	tex->texfilter,
-		   MGA_TEXBORDERCOL,	tex->texbordercol );
+	DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
+				MGA_MAP1_ENABLE |
+				MGA_G400_TC2_MAGIC),
+		  MGA_TEXCTL, tex->texctl,
+		  MGA_TEXFILTER, tex->texfilter,
+		  MGA_TEXBORDERCOL, tex->texbordercol);
 
-	DMA_BLOCK( MGA_TEXORG,		tex->texorg,
-		   MGA_TEXORG1,		tex->texorg1,
-		   MGA_TEXORG2,		tex->texorg2,
-		   MGA_TEXORG3,		tex->texorg3 );
+	DMA_BLOCK(MGA_TEXORG, tex->texorg,
+		  MGA_TEXORG1, tex->texorg1,
+		  MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3);
 
-	DMA_BLOCK( MGA_TEXORG4,		tex->texorg4,
-		   MGA_TEXWIDTH,	tex->texwidth,
-		   MGA_TEXHEIGHT,	tex->texheight,
-		   MGA_WR49,		0x00000000 );
+	DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
+		  MGA_TEXWIDTH, tex->texwidth,
+		  MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000);
 
-	DMA_BLOCK( MGA_WR57,		0x00000000,
-		   MGA_WR53,		0x00000000,
-		   MGA_WR61,		0x00000000,
-		   MGA_WR52,		tex->texwidth | MGA_G400_WR_MAGIC );
+	DMA_BLOCK(MGA_WR57, 0x00000000,
+		  MGA_WR53, 0x00000000,
+		  MGA_WR61, 0x00000000,
+		  MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC);
 
-	DMA_BLOCK( MGA_WR60,		tex->texheight | MGA_G400_WR_MAGIC,
-		   MGA_TEXTRANS,	0x0000ffff,
-		   MGA_TEXTRANSHIGH,	0x0000ffff,
-		   MGA_TEXCTL2,		tex->texctl2 | MGA_G400_TC2_MAGIC );
+	DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
+		  MGA_TEXTRANS, 0x0000ffff,
+		  MGA_TEXTRANSHIGH, 0x0000ffff,
+		  MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC);
 
 	ADVANCE_DMA();
 }
 
-static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
+static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	unsigned int pipe = sarea_priv->warp_pipe;
 	DMA_LOCALS;
 
-	BEGIN_DMA( 3 );
+	BEGIN_DMA(3);
 
-	DMA_BLOCK( MGA_WIADDR,	MGA_WMODE_SUSPEND,
-		   MGA_WVRTXSZ,	0x00000007,
-		   MGA_WFLAG,	0x00000000,
-		   MGA_WR24,	0x00000000 );
+	DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND,
+		  MGA_WVRTXSZ, 0x00000007,
+		  MGA_WFLAG, 0x00000000, MGA_WR24, 0x00000000);
 
-	DMA_BLOCK( MGA_WR25,	0x00000100,
-		   MGA_WR34,	0x00000000,
-		   MGA_WR42,	0x0000ffff,
-		   MGA_WR60,	0x0000ffff );
+	DMA_BLOCK(MGA_WR25, 0x00000100,
+		  MGA_WR34, 0x00000000,
+		  MGA_WR42, 0x0000ffff, MGA_WR60, 0x0000ffff);
 
 	/* Padding required to to hardware bug.
 	 */
-	DMA_BLOCK( MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_WIADDR,	(dev_priv->warp_pipe_phys[pipe] |
-				 MGA_WMODE_START |
-				 MGA_WAGP_ENABLE) );
+	DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
+		  MGA_DMAPAD, 0xffffffff,
+		  MGA_DMAPAD, 0xffffffff,
+		  MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
+			       MGA_WMODE_START | MGA_WAGP_ENABLE));
 
 	ADVANCE_DMA();
 }
 
-static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
+static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	unsigned int pipe = sarea_priv->warp_pipe;
@@ -279,145 +258,139 @@ static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
 
 /*  	printk("mga_g400_emit_pipe %x\n", pipe); */
 
-	BEGIN_DMA( 10 );
+	BEGIN_DMA(10);
 
-	DMA_BLOCK( MGA_WIADDR2,	MGA_WMODE_SUSPEND,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000 );
+	DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 
-	if ( pipe & MGA_T2 ) {
-		DMA_BLOCK( MGA_WVRTXSZ,		0x00001e09,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000 );
+	if (pipe & MGA_T2) {
+		DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
+			  MGA_DMAPAD, 0x00000000,
+			  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 
-		DMA_BLOCK( MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x1e000000 );
+		DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
+			  MGA_WACCEPTSEQ, 0x00000000,
+			  MGA_WACCEPTSEQ, 0x00000000,
+			  MGA_WACCEPTSEQ, 0x1e000000);
 	} else {
-		if ( dev_priv->warp_pipe & MGA_T2 ) {
+		if (dev_priv->warp_pipe & MGA_T2) {
 			/* Flush the WARP pipe */
-			DMA_BLOCK( MGA_YDST,		0x00000000,
-				   MGA_FXLEFT,		0x00000000,
-				   MGA_FXRIGHT,		0x00000001,
-				   MGA_DWGCTL,		MGA_DWGCTL_FLUSH );
-
-			DMA_BLOCK( MGA_LEN + MGA_EXEC,	0x00000001,
-				   MGA_DWGSYNC,		0x00007000,
-				   MGA_TEXCTL2,		MGA_G400_TC2_MAGIC,
-				   MGA_LEN + MGA_EXEC,	0x00000000 );
-
-			DMA_BLOCK( MGA_TEXCTL2,		(MGA_DUALTEX |
-							 MGA_G400_TC2_MAGIC),
-				   MGA_LEN + MGA_EXEC,	0x00000000,
-				   MGA_TEXCTL2,		MGA_G400_TC2_MAGIC,
-				   MGA_DMAPAD,		0x00000000 );
+			DMA_BLOCK(MGA_YDST, 0x00000000,
+				  MGA_FXLEFT, 0x00000000,
+				  MGA_FXRIGHT, 0x00000001,
+				  MGA_DWGCTL, MGA_DWGCTL_FLUSH);
+
+			DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001,
+				  MGA_DWGSYNC, 0x00007000,
+				  MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
+				  MGA_LEN + MGA_EXEC, 0x00000000);
+
+			DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX |
+						MGA_G400_TC2_MAGIC),
+				  MGA_LEN + MGA_EXEC, 0x00000000,
+				  MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
+				  MGA_DMAPAD, 0x00000000);
 		}
 
-		DMA_BLOCK( MGA_WVRTXSZ,		0x00001807,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000 );
+		DMA_BLOCK(MGA_WVRTXSZ, 0x00001807,
+			  MGA_DMAPAD, 0x00000000,
+			  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 
-		DMA_BLOCK( MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x18000000 );
+		DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
+			  MGA_WACCEPTSEQ, 0x00000000,
+			  MGA_WACCEPTSEQ, 0x00000000,
+			  MGA_WACCEPTSEQ, 0x18000000);
 	}
 
-	DMA_BLOCK( MGA_WFLAG,	0x00000000,
-		   MGA_WFLAG1,	0x00000000,
-		   MGA_WR56,	MGA_G400_WR56_MAGIC,
-		   MGA_DMAPAD,	0x00000000 );
+	DMA_BLOCK(MGA_WFLAG, 0x00000000,
+		  MGA_WFLAG1, 0x00000000,
+		  MGA_WR56, MGA_G400_WR56_MAGIC, MGA_DMAPAD, 0x00000000);
 
-	DMA_BLOCK( MGA_WR49,	0x00000000,		/* tex0              */
-		   MGA_WR57,	0x00000000,		/* tex0              */
-		   MGA_WR53,	0x00000000,		/* tex1              */
-		   MGA_WR61,	0x00000000 );		/* tex1              */
+	DMA_BLOCK(MGA_WR49, 0x00000000,	/* tex0              */
+		  MGA_WR57, 0x00000000,	/* tex0              */
+		  MGA_WR53, 0x00000000,	/* tex1              */
+		  MGA_WR61, 0x00000000);	/* tex1              */
 
-	DMA_BLOCK( MGA_WR54,	MGA_G400_WR_MAGIC,	/* tex0 width        */
-		   MGA_WR62,	MGA_G400_WR_MAGIC,	/* tex0 height       */
-		   MGA_WR52,	MGA_G400_WR_MAGIC,	/* tex1 width        */
-		   MGA_WR60,	MGA_G400_WR_MAGIC );	/* tex1 height       */
+	DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC,	/* tex0 width        */
+		  MGA_WR62, MGA_G400_WR_MAGIC,	/* tex0 height       */
+		  MGA_WR52, MGA_G400_WR_MAGIC,	/* tex1 width        */
+		  MGA_WR60, MGA_G400_WR_MAGIC);	/* tex1 height       */
 
 	/* Padding required to to hardware bug */
-	DMA_BLOCK( MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_WIADDR2,	(dev_priv->warp_pipe_phys[pipe] |
-				 MGA_WMODE_START |
-				 MGA_WAGP_ENABLE) );
+	DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
+		  MGA_DMAPAD, 0xffffffff,
+		  MGA_DMAPAD, 0xffffffff,
+		  MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
+				MGA_WMODE_START | MGA_WAGP_ENABLE));
 
 	ADVANCE_DMA();
 }
 
-static void mga_g200_emit_state( drm_mga_private_t *dev_priv )
+static void mga_g200_emit_state(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	unsigned int dirty = sarea_priv->dirty;
 
-	if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
-		mga_g200_emit_pipe( dev_priv );
+	if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
+		mga_g200_emit_pipe(dev_priv);
 		dev_priv->warp_pipe = sarea_priv->warp_pipe;
 	}
 
-	if ( dirty & MGA_UPLOAD_CONTEXT ) {
-		mga_g200_emit_context( dev_priv );
+	if (dirty & MGA_UPLOAD_CONTEXT) {
+		mga_g200_emit_context(dev_priv);
 		sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
 	}
 
-	if ( dirty & MGA_UPLOAD_TEX0 ) {
-		mga_g200_emit_tex0( dev_priv );
+	if (dirty & MGA_UPLOAD_TEX0) {
+		mga_g200_emit_tex0(dev_priv);
 		sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
 	}
 }
 
-static void mga_g400_emit_state( drm_mga_private_t *dev_priv )
+static void mga_g400_emit_state(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	unsigned int dirty = sarea_priv->dirty;
 	int multitex = sarea_priv->warp_pipe & MGA_T2;
 
-	if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
-		mga_g400_emit_pipe( dev_priv );
+	if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
+		mga_g400_emit_pipe(dev_priv);
 		dev_priv->warp_pipe = sarea_priv->warp_pipe;
 	}
 
-	if ( dirty & MGA_UPLOAD_CONTEXT ) {
-		mga_g400_emit_context( dev_priv );
+	if (dirty & MGA_UPLOAD_CONTEXT) {
+		mga_g400_emit_context(dev_priv);
 		sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
 	}
 
-	if ( dirty & MGA_UPLOAD_TEX0 ) {
-		mga_g400_emit_tex0( dev_priv );
+	if (dirty & MGA_UPLOAD_TEX0) {
+		mga_g400_emit_tex0(dev_priv);
 		sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
 	}
 
-	if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) {
-		mga_g400_emit_tex1( dev_priv );
+	if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
+		mga_g400_emit_tex1(dev_priv);
 		sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
 	}
 }
 
-
 /* ================================================================
  * SAREA state verification
  */
 
 /* Disallow all write destinations except the front and backbuffer.
  */
-static int mga_verify_context( drm_mga_private_t *dev_priv )
+static int mga_verify_context(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 
-	if ( ctx->dstorg != dev_priv->front_offset &&
-	     ctx->dstorg != dev_priv->back_offset ) {
-		DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n",
-			   ctx->dstorg, dev_priv->front_offset,
-			   dev_priv->back_offset );
+	if (ctx->dstorg != dev_priv->front_offset &&
+	    ctx->dstorg != dev_priv->back_offset) {
+		DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
+			  ctx->dstorg, dev_priv->front_offset,
+			  dev_priv->back_offset);
 		ctx->dstorg = 0;
 		return DRM_ERR(EINVAL);
 	}
@@ -427,7 +400,7 @@ static int mga_verify_context( drm_mga_private_t *dev_priv )
 
 /* Disallow texture reads from PCI space.
  */
-static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
+static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
@@ -435,9 +408,8 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
 
 	org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
 
-	if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) {
-		DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n",
-			   tex->texorg, unit );
+	if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
+		DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
 		tex->texorg = 0;
 		return DRM_ERR(EINVAL);
 	}
@@ -445,73 +417,70 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
 	return 0;
 }
 
-static int mga_verify_state( drm_mga_private_t *dev_priv )
+static int mga_verify_state(drm_mga_private_t * dev_priv)
 {
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	unsigned int dirty = sarea_priv->dirty;
 	int ret = 0;
 
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
+	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 
-	if ( dirty & MGA_UPLOAD_CONTEXT )
-		ret |= mga_verify_context( dev_priv );
+	if (dirty & MGA_UPLOAD_CONTEXT)
+		ret |= mga_verify_context(dev_priv);
 
-	if ( dirty & MGA_UPLOAD_TEX0 )
-		ret |= mga_verify_tex( dev_priv, 0 );
+	if (dirty & MGA_UPLOAD_TEX0)
+		ret |= mga_verify_tex(dev_priv, 0);
 
-	if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
-		if ( dirty & MGA_UPLOAD_TEX1 )
-			ret |= mga_verify_tex( dev_priv, 1 );
+	if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
+		if (dirty & MGA_UPLOAD_TEX1)
+			ret |= mga_verify_tex(dev_priv, 1);
 
-		if ( dirty & MGA_UPLOAD_PIPE )
-			ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES );
+		if (dirty & MGA_UPLOAD_PIPE)
+			ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES);
 	} else {
-		if ( dirty & MGA_UPLOAD_PIPE )
-			ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES );
+		if (dirty & MGA_UPLOAD_PIPE)
+			ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES);
 	}
 
-	return ( ret == 0 );
+	return (ret == 0);
 }
 
-static int mga_verify_iload( drm_mga_private_t *dev_priv,
-			     unsigned int dstorg, unsigned int length )
+static int mga_verify_iload(drm_mga_private_t * dev_priv,
+			    unsigned int dstorg, unsigned int length)
 {
-	if ( dstorg < dev_priv->texture_offset ||
-	     dstorg + length > (dev_priv->texture_offset +
-				dev_priv->texture_size) ) {
-		DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg );
+	if (dstorg < dev_priv->texture_offset ||
+	    dstorg + length > (dev_priv->texture_offset +
+			       dev_priv->texture_size)) {
+		DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( length & MGA_ILOAD_MASK ) {
-		DRM_ERROR( "*** bad iload length: 0x%x\n",
-			   length & MGA_ILOAD_MASK );
+	if (length & MGA_ILOAD_MASK) {
+		DRM_ERROR("*** bad iload length: 0x%x\n",
+			  length & MGA_ILOAD_MASK);
 		return DRM_ERR(EINVAL);
 	}
 
 	return 0;
 }
 
-static int mga_verify_blit( drm_mga_private_t *dev_priv,
-			    unsigned int srcorg, unsigned int dstorg )
+static int mga_verify_blit(drm_mga_private_t * dev_priv,
+			   unsigned int srcorg, unsigned int dstorg)
 {
-	if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
-	     (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) {
-		DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n",
-			   srcorg, dstorg );
+	if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
+	    (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
+		DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
 		return DRM_ERR(EINVAL);
 	}
 	return 0;
 }
 
-
 /* ================================================================
  *
  */
 
-static void mga_dma_dispatch_clear( drm_device_t *dev,
-				    drm_mga_clear_t *clear )
+static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -520,92 +489,86 @@ static void mga_dma_dispatch_clear( drm_device_t *dev,
 	int nbox = sarea_priv->nbox;
 	int i;
 	DMA_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	BEGIN_DMA( 1 );
+	BEGIN_DMA(1);
 
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
 
 	ADVANCE_DMA();
 
-	for ( i = 0 ; i < nbox ; i++ ) {
+	for (i = 0; i < nbox; i++) {
 		drm_clip_rect_t *box = &pbox[i];
 		u32 height = box->y2 - box->y1;
 
-		DRM_DEBUG( "   from=%d,%d to=%d,%d\n",
-			   box->x1, box->y1, box->x2, box->y2 );
+		DRM_DEBUG("   from=%d,%d to=%d,%d\n",
+			  box->x1, box->y1, box->x2, box->y2);
 
-		if ( clear->flags & MGA_FRONT ) {
-			BEGIN_DMA( 2 );
+		if (clear->flags & MGA_FRONT) {
+			BEGIN_DMA(2);
 
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_PLNWT,	clear->color_mask,
-				   MGA_YDSTLEN, (box->y1 << 16) | height,
-				   MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
+			DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+				  MGA_PLNWT, clear->color_mask,
+				  MGA_YDSTLEN, (box->y1 << 16) | height,
+				  MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_FCOL,	clear->clear_color,
-				   MGA_DSTORG,	dev_priv->front_offset,
-				   MGA_DWGCTL + MGA_EXEC,
-						dev_priv->clear_cmd );
+			DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+				  MGA_FCOL, clear->clear_color,
+				  MGA_DSTORG, dev_priv->front_offset,
+				  MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 
 			ADVANCE_DMA();
 		}
 
+		if (clear->flags & MGA_BACK) {
+			BEGIN_DMA(2);
 
-		if ( clear->flags & MGA_BACK ) {
-			BEGIN_DMA( 2 );
+			DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+				  MGA_PLNWT, clear->color_mask,
+				  MGA_YDSTLEN, (box->y1 << 16) | height,
+				  MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_PLNWT,	clear->color_mask,
-				   MGA_YDSTLEN, (box->y1 << 16) | height,
-				   MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_FCOL,	clear->clear_color,
-				   MGA_DSTORG,	dev_priv->back_offset,
-				   MGA_DWGCTL + MGA_EXEC,
-						dev_priv->clear_cmd );
+			DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+				  MGA_FCOL, clear->clear_color,
+				  MGA_DSTORG, dev_priv->back_offset,
+				  MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 
 			ADVANCE_DMA();
 		}
 
-		if ( clear->flags & MGA_DEPTH ) {
-			BEGIN_DMA( 2 );
+		if (clear->flags & MGA_DEPTH) {
+			BEGIN_DMA(2);
 
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_PLNWT,	clear->depth_mask,
-				   MGA_YDSTLEN, (box->y1 << 16) | height,
-				   MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
+			DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+				  MGA_PLNWT, clear->depth_mask,
+				  MGA_YDSTLEN, (box->y1 << 16) | height,
+				  MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_FCOL,	clear->clear_depth,
-				   MGA_DSTORG,	dev_priv->depth_offset,
-				   MGA_DWGCTL + MGA_EXEC,
-						dev_priv->clear_cmd );
+			DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+				  MGA_FCOL, clear->clear_depth,
+				  MGA_DSTORG, dev_priv->depth_offset,
+				  MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 
 			ADVANCE_DMA();
 		}
 
 	}
 
-	BEGIN_DMA( 1 );
+	BEGIN_DMA(1);
 
 	/* Force reset of DWGCTL */
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	ctx->plnwt,
-		   MGA_DWGCTL,	ctx->dwgctl );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
 
 	ADVANCE_DMA();
 
 	FLUSH_DMA();
 }
 
-static void mga_dma_dispatch_swap( drm_device_t *dev )
+static void mga_dma_dispatch_swap(drm_device_t * dev)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -614,56 +577,52 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
 	int nbox = sarea_priv->nbox;
 	int i;
 	DMA_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	sarea_priv->last_frame.head = dev_priv->prim.tail;
 	sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
 
-	BEGIN_DMA( 4 + nbox );
+	BEGIN_DMA(4 + nbox);
 
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
 
-	DMA_BLOCK( MGA_DSTORG,	dev_priv->front_offset,
-		   MGA_MACCESS,	dev_priv->maccess,
-		   MGA_SRCORG,	dev_priv->back_offset,
-		   MGA_AR5,	dev_priv->front_pitch );
+	DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset,
+		  MGA_MACCESS, dev_priv->maccess,
+		  MGA_SRCORG, dev_priv->back_offset,
+		  MGA_AR5, dev_priv->front_pitch);
 
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	0xffffffff,
-		   MGA_DWGCTL,	MGA_DWGCTL_COPY );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_PLNWT, 0xffffffff, MGA_DWGCTL, MGA_DWGCTL_COPY);
 
-	for ( i = 0 ; i < nbox ; i++ ) {
+	for (i = 0; i < nbox; i++) {
 		drm_clip_rect_t *box = &pbox[i];
 		u32 height = box->y2 - box->y1;
 		u32 start = box->y1 * dev_priv->front_pitch;
 
-		DRM_DEBUG( "   from=%d,%d to=%d,%d\n",
-			   box->x1, box->y1, box->x2, box->y2 );
+		DRM_DEBUG("   from=%d,%d to=%d,%d\n",
+			  box->x1, box->y1, box->x2, box->y2);
 
-		DMA_BLOCK( MGA_AR0,	start + box->x2 - 1,
-			   MGA_AR3,	start + box->x1,
-			   MGA_FXBNDRY,	((box->x2 - 1) << 16) | box->x1,
-			   MGA_YDSTLEN + MGA_EXEC,
-					(box->y1 << 16) | height );
+		DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
+			  MGA_AR3, start + box->x1,
+			  MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
+			  MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height);
 	}
 
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	ctx->plnwt,
-		   MGA_SRCORG,	dev_priv->front_offset,
-		   MGA_DWGCTL,	ctx->dwgctl );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_PLNWT, ctx->plnwt,
+		  MGA_SRCORG, dev_priv->front_offset, MGA_DWGCTL, ctx->dwgctl);
 
 	ADVANCE_DMA();
 
 	FLUSH_DMA();
 
-	DRM_DEBUG( "%s... done.\n", __FUNCTION__ );
+	DRM_DEBUG("%s... done.\n", __FUNCTION__);
 }
 
-static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
+static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
@@ -672,46 +631,46 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
 	u32 length = (u32) buf->used;
 	int i = 0;
 	DMA_LOCALS;
-	DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used );
+	DRM_DEBUG("vertex: buf=%d used=%d\n", buf->idx, buf->used);
 
-	if ( buf->used ) {
+	if (buf->used) {
 		buf_priv->dispatched = 1;
 
-		MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
+		MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
 
 		do {
-			if ( i < sarea_priv->nbox ) {
-				mga_emit_clip_rect( dev_priv,
-						    &sarea_priv->boxes[i] );
+			if (i < sarea_priv->nbox) {
+				mga_emit_clip_rect(dev_priv,
+						   &sarea_priv->boxes[i]);
 			}
 
-			BEGIN_DMA( 1 );
+			BEGIN_DMA(1);
 
-			DMA_BLOCK( MGA_DMAPAD,		0x00000000,
-				   MGA_DMAPAD,		0x00000000,
-				   MGA_SECADDRESS,	(address |
-							 MGA_DMA_VERTEX),
-				   MGA_SECEND,		((address + length) |
-							 MGA_PAGPXFER) );
+			DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+				  MGA_DMAPAD, 0x00000000,
+				  MGA_SECADDRESS, (address |
+						   MGA_DMA_VERTEX),
+				  MGA_SECEND, ((address + length) |
+					       MGA_PAGPXFER));
 
 			ADVANCE_DMA();
-		} while ( ++i < sarea_priv->nbox );
+		} while (++i < sarea_priv->nbox);
 	}
 
-	if ( buf_priv->discard ) {
-		AGE_BUFFER( buf_priv );
+	if (buf_priv->discard) {
+		AGE_BUFFER(buf_priv);
 		buf->pending = 0;
 		buf->used = 0;
 		buf_priv->dispatched = 0;
 
-		mga_freelist_put( dev, buf );
+		mga_freelist_put(dev, buf);
 	}
 
 	FLUSH_DMA();
 }
 
-static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
-				      unsigned int start, unsigned int end )
+static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf,
+				     unsigned int start, unsigned int end)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
@@ -719,38 +678,38 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
 	u32 address = (u32) buf->bus_address;
 	int i = 0;
 	DMA_LOCALS;
-	DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end );
+	DRM_DEBUG("indices: buf=%d start=%d end=%d\n", buf->idx, start, end);
 
-	if ( start != end ) {
+	if (start != end) {
 		buf_priv->dispatched = 1;
 
-		MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
+		MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
 
 		do {
-			if ( i < sarea_priv->nbox ) {
-				mga_emit_clip_rect( dev_priv,
-						    &sarea_priv->boxes[i] );
+			if (i < sarea_priv->nbox) {
+				mga_emit_clip_rect(dev_priv,
+						   &sarea_priv->boxes[i]);
 			}
 
-			BEGIN_DMA( 1 );
+			BEGIN_DMA(1);
 
-			DMA_BLOCK( MGA_DMAPAD,		0x00000000,
-				   MGA_DMAPAD,		0x00000000,
-				   MGA_SETUPADDRESS,	address + start,
-				   MGA_SETUPEND,	((address + end) |
-							 MGA_PAGPXFER) );
+			DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+				  MGA_DMAPAD, 0x00000000,
+				  MGA_SETUPADDRESS, address + start,
+				  MGA_SETUPEND, ((address + end) |
+						 MGA_PAGPXFER));
 
 			ADVANCE_DMA();
-		} while ( ++i < sarea_priv->nbox );
+		} while (++i < sarea_priv->nbox);
 	}
 
-	if ( buf_priv->discard ) {
-		AGE_BUFFER( buf_priv );
+	if (buf_priv->discard) {
+		AGE_BUFFER(buf_priv);
 		buf->pending = 0;
 		buf->used = 0;
 		buf_priv->dispatched = 0;
 
-		mga_freelist_put( dev, buf );
+		mga_freelist_put(dev, buf);
 	}
 
 	FLUSH_DMA();
@@ -759,8 +718,8 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
 /* This copies a 64 byte aligned agp region to the frambuffer with a
  * standard blit, the ioctl needs to do checking.
  */
-static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf,
-				    unsigned int dstorg, unsigned int length )
+static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf,
+				   unsigned int dstorg, unsigned int length)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
@@ -768,52 +727,45 @@ static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf,
 	u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
 	u32 y2;
 	DMA_LOCALS;
-	DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used );
+	DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
 
 	y2 = length / 64;
 
-	BEGIN_DMA( 5 );
+	BEGIN_DMA(5);
 
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
 
-	DMA_BLOCK( MGA_DSTORG,	dstorg,
-		   MGA_MACCESS,	0x00000000,
-		   MGA_SRCORG,	srcorg,
-		   MGA_AR5,	64 );
+	DMA_BLOCK(MGA_DSTORG, dstorg,
+		  MGA_MACCESS, 0x00000000, MGA_SRCORG, srcorg, MGA_AR5, 64);
 
-	DMA_BLOCK( MGA_PITCH,	64,
-		   MGA_PLNWT,	0xffffffff,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGCTL,	MGA_DWGCTL_COPY );
+	DMA_BLOCK(MGA_PITCH, 64,
+		  MGA_PLNWT, 0xffffffff,
+		  MGA_DMAPAD, 0x00000000, MGA_DWGCTL, MGA_DWGCTL_COPY);
 
-	DMA_BLOCK( MGA_AR0,	63,
-		   MGA_AR3,	0,
-		   MGA_FXBNDRY,	(63 << 16) | 0,
-		   MGA_YDSTLEN + MGA_EXEC, y2 );
+	DMA_BLOCK(MGA_AR0, 63,
+		  MGA_AR3, 0,
+		  MGA_FXBNDRY, (63 << 16) | 0, MGA_YDSTLEN + MGA_EXEC, y2);
 
-	DMA_BLOCK( MGA_PLNWT,	ctx->plnwt,
-		   MGA_SRCORG,	dev_priv->front_offset,
-		   MGA_PITCH,	dev_priv->front_pitch,
-		   MGA_DWGSYNC,	0x00007000 );
+	DMA_BLOCK(MGA_PLNWT, ctx->plnwt,
+		  MGA_SRCORG, dev_priv->front_offset,
+		  MGA_PITCH, dev_priv->front_pitch, MGA_DWGSYNC, 0x00007000);
 
 	ADVANCE_DMA();
 
-	AGE_BUFFER( buf_priv );
+	AGE_BUFFER(buf_priv);
 
 	buf->pending = 0;
 	buf->used = 0;
 	buf_priv->dispatched = 0;
 
-	mga_freelist_put( dev, buf );
+	mga_freelist_put(dev, buf);
 
 	FLUSH_DMA();
 }
 
-static void mga_dma_dispatch_blit( drm_device_t *dev,
-				   drm_mga_blit_t *blit )
+static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit)
 {
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -822,26 +774,24 @@ static void mga_dma_dispatch_blit( drm_device_t *dev,
 	int nbox = sarea_priv->nbox;
 	u32 scandir = 0, i;
 	DMA_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	BEGIN_DMA( 4 + nbox );
+	BEGIN_DMA(4 + nbox);
 
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_DMAPAD, 0x00000000,
+		  MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
 
-	DMA_BLOCK( MGA_DWGCTL,	MGA_DWGCTL_COPY,
-		   MGA_PLNWT,	blit->planemask,
-		   MGA_SRCORG,	blit->srcorg,
-		   MGA_DSTORG,	blit->dstorg );
+	DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY,
+		  MGA_PLNWT, blit->planemask,
+		  MGA_SRCORG, blit->srcorg, MGA_DSTORG, blit->dstorg);
 
-	DMA_BLOCK( MGA_SGN,	scandir,
-		   MGA_MACCESS,	dev_priv->maccess,
-		   MGA_AR5,	blit->ydir * blit->src_pitch,
-		   MGA_PITCH,	blit->dst_pitch );
+	DMA_BLOCK(MGA_SGN, scandir,
+		  MGA_MACCESS, dev_priv->maccess,
+		  MGA_AR5, blit->ydir * blit->src_pitch,
+		  MGA_PITCH, blit->dst_pitch);
 
-	for ( i = 0 ; i < nbox ; i++ ) {
+	for (i = 0; i < nbox; i++) {
 		int srcx = pbox[i].x1 + blit->delta_sx;
 		int srcy = pbox[i].y1 + blit->delta_sy;
 		int dstx = pbox[i].x1 + blit->delta_dx;
@@ -850,52 +800,51 @@ static void mga_dma_dispatch_blit( drm_device_t *dev,
 		int w = pbox[i].x2 - pbox[i].x1 - 1;
 		int start;
 
-		if ( blit->ydir == -1 ) {
+		if (blit->ydir == -1) {
 			srcy = blit->height - srcy - 1;
 		}
 
 		start = srcy * blit->src_pitch + srcx;
 
-		DMA_BLOCK( MGA_AR0,	start + w,
-			   MGA_AR3,	start,
-			   MGA_FXBNDRY,	((dstx + w) << 16) | (dstx & 0xffff),
-			   MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h );
+		DMA_BLOCK(MGA_AR0, start + w,
+			  MGA_AR3, start,
+			  MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
+			  MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h);
 	}
 
 	/* Do something to flush AGP?
 	 */
 
 	/* Force reset of DWGCTL */
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	ctx->plnwt,
-		   MGA_PITCH,	dev_priv->front_pitch,
-		   MGA_DWGCTL,	ctx->dwgctl );
+	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
+		  MGA_PLNWT, ctx->plnwt,
+		  MGA_PITCH, dev_priv->front_pitch, MGA_DWGCTL, ctx->dwgctl);
 
 	ADVANCE_DMA();
 }
 
-
 /* ================================================================
  *
  */
 
-int mga_dma_clear( DRM_IOCTL_ARGS )
+int mga_dma_clear(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_clear_t clear;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t __user *)data, sizeof(clear) );
+	DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data,
+				 sizeof(clear));
 
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
+	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 
-	WRAP_TEST_WITH_RETURN( dev_priv );
+	WRAP_TEST_WITH_RETURN(dev_priv);
 
-	mga_dma_dispatch_clear( dev, &clear );
+	mga_dma_dispatch_clear(dev, &clear);
 
 	/* Make sure we restore the 3D state next time.
 	 */
@@ -904,20 +853,20 @@ int mga_dma_clear( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-int mga_dma_swap( DRM_IOCTL_ARGS )
+int mga_dma_swap(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
+	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 
-	WRAP_TEST_WITH_RETURN( dev_priv );
+	WRAP_TEST_WITH_RETURN(dev_priv);
 
-	mga_dma_dispatch_swap( dev );
+	mga_dma_dispatch_swap(dev);
 
 	/* Make sure we restore the 3D state next time.
 	 */
@@ -926,7 +875,7 @@ int mga_dma_swap( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-int mga_dma_vertex( DRM_IOCTL_ARGS )
+int mga_dma_vertex(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mga_private_t *dev_priv = dev->dev_private;
@@ -935,37 +884,38 @@ int mga_dma_vertex( DRM_IOCTL_ARGS )
 	drm_mga_buf_priv_t *buf_priv;
 	drm_mga_vertex_t vertex;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( vertex,
-			     (drm_mga_vertex_t __user *)data,
-			     sizeof(vertex) );
+	DRM_COPY_FROM_USER_IOCTL(vertex,
+				 (drm_mga_vertex_t __user *) data,
+				 sizeof(vertex));
 
-        if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL);
+	if (vertex.idx < 0 || vertex.idx > dma->buf_count)
+		return DRM_ERR(EINVAL);
 	buf = dma->buflist[vertex.idx];
 	buf_priv = buf->dev_private;
 
 	buf->used = vertex.used;
 	buf_priv->discard = vertex.discard;
 
-	if ( !mga_verify_state( dev_priv ) ) {
-		if ( vertex.discard ) {
-			if ( buf_priv->dispatched == 1 )
-				AGE_BUFFER( buf_priv );
+	if (!mga_verify_state(dev_priv)) {
+		if (vertex.discard) {
+			if (buf_priv->dispatched == 1)
+				AGE_BUFFER(buf_priv);
 			buf_priv->dispatched = 0;
-			mga_freelist_put( dev, buf );
+			mga_freelist_put(dev, buf);
 		}
 		return DRM_ERR(EINVAL);
 	}
 
-	WRAP_TEST_WITH_RETURN( dev_priv );
+	WRAP_TEST_WITH_RETURN(dev_priv);
 
-	mga_dma_dispatch_vertex( dev, buf );
+	mga_dma_dispatch_vertex(dev, buf);
 
 	return 0;
 }
 
-int mga_dma_indices( DRM_IOCTL_ARGS )
+int mga_dma_indices(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mga_private_t *dev_priv = dev->dev_private;
@@ -974,37 +924,38 @@ int mga_dma_indices( DRM_IOCTL_ARGS )
 	drm_mga_buf_priv_t *buf_priv;
 	drm_mga_indices_t indices;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( indices,
-			     (drm_mga_indices_t __user *)data,
-			     sizeof(indices) );
+	DRM_COPY_FROM_USER_IOCTL(indices,
+				 (drm_mga_indices_t __user *) data,
+				 sizeof(indices));
 
-        if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL);
+	if (indices.idx < 0 || indices.idx > dma->buf_count)
+		return DRM_ERR(EINVAL);
 
 	buf = dma->buflist[indices.idx];
 	buf_priv = buf->dev_private;
 
 	buf_priv->discard = indices.discard;
 
-	if ( !mga_verify_state( dev_priv ) ) {
-		if ( indices.discard ) {
-			if ( buf_priv->dispatched == 1 )
-				AGE_BUFFER( buf_priv );
+	if (!mga_verify_state(dev_priv)) {
+		if (indices.discard) {
+			if (buf_priv->dispatched == 1)
+				AGE_BUFFER(buf_priv);
 			buf_priv->dispatched = 0;
-			mga_freelist_put( dev, buf );
+			mga_freelist_put(dev, buf);
 		}
 		return DRM_ERR(EINVAL);
 	}
 
-	WRAP_TEST_WITH_RETURN( dev_priv );
+	WRAP_TEST_WITH_RETURN(dev_priv);
 
-	mga_dma_dispatch_indices( dev, buf, indices.start, indices.end );
+	mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);
 
 	return 0;
 }
 
-int mga_dma_iload( DRM_IOCTL_ARGS )
+int mga_dma_iload(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_device_dma_t *dma = dev->dma;
@@ -1012,32 +963,34 @@ int mga_dma_iload( DRM_IOCTL_ARGS )
 	drm_buf_t *buf;
 	drm_mga_buf_priv_t *buf_priv;
 	drm_mga_iload_t iload;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t __user *)data, sizeof(iload) );
+	DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data,
+				 sizeof(iload));
 
 #if 0
-	if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {
-		if ( MGA_DMA_DEBUG )
-			DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ );
+	if (mga_do_wait_for_idle(dev_priv) < 0) {
+		if (MGA_DMA_DEBUG)
+			DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
 		return DRM_ERR(EBUSY);
 	}
 #endif
-        if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL);
+	if (iload.idx < 0 || iload.idx > dma->buf_count)
+		return DRM_ERR(EINVAL);
 
 	buf = dma->buflist[iload.idx];
 	buf_priv = buf->dev_private;
 
-	if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) {
-		mga_freelist_put( dev, buf );
+	if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) {
+		mga_freelist_put(dev, buf);
 		return DRM_ERR(EINVAL);
 	}
 
-	WRAP_TEST_WITH_RETURN( dev_priv );
+	WRAP_TEST_WITH_RETURN(dev_priv);
 
-	mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length );
+	mga_dma_dispatch_iload(dev, buf, iload.dstorg, iload.length);
 
 	/* Make sure we restore the 3D state next time.
 	 */
@@ -1046,27 +999,28 @@ int mga_dma_iload( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-int mga_dma_blit( DRM_IOCTL_ARGS )
+int mga_dma_blit(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_mga_blit_t blit;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t __user *)data, sizeof(blit) );
+	DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data,
+				 sizeof(blit));
 
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
+	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 
-	if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) )
+	if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg))
 		return DRM_ERR(EINVAL);
 
-	WRAP_TEST_WITH_RETURN( dev_priv );
+	WRAP_TEST_WITH_RETURN(dev_priv);
 
-	mga_dma_dispatch_blit( dev, &blit );
+	mga_dma_dispatch_blit(dev, &blit);
 
 	/* Make sure we restore the 3D state next time.
 	 */
@@ -1075,24 +1029,24 @@ int mga_dma_blit( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-int mga_getparam( DRM_IOCTL_ARGS )
+int mga_getparam(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_mga_private_t *dev_priv = dev->dev_private;
 	drm_mga_getparam_t param;
 	int value;
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t __user *)data,
-			     sizeof(param) );
+	DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data,
+				 sizeof(param));
 
-	DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
+	DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
 
-	switch( param.param ) {
+	switch (param.param) {
 	case MGA_PARAM_IRQ_NR:
 		value = dev->irq;
 		break;
@@ -1100,10 +1054,10 @@ int mga_getparam( DRM_IOCTL_ARGS )
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
-		DRM_ERROR( "copy_to_user\n" );
+	if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
+		DRM_ERROR("copy_to_user\n");
 		return DRM_ERR(EFAULT);
 	}
-	
+
 	return 0;
 }
diff --git a/shared-core/mga_ucode.h b/shared-core/mga_ucode.h
index fa0f82ec..b611e274 100644
--- a/shared-core/mga_ucode.h
+++ b/shared-core/mga_ucode.h
@@ -40,11606 +40,11606 @@
 
 static unsigned char warp_g200_tgz[] = {
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
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-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
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-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
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-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
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-0x40, 0x40, 0xD8, 0xEC,
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+	0x40, 0x40, 0xD8, 0xEC,
 
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-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
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+	0x89, 0x04,
+	0x01, 0x04,
+	0x09, 0x04,
 
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC0, 0xEC,
+	0x11, 0x04,
+	0x00, 0xE0,
 
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
+	0x41, 0xCC, 0x41, 0xCD,
+	0x49, 0xCC, 0x49, 0xCD,
 
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
+	0xD1, 0x41, 0xC0, 0xEC,
+	0x51, 0xCC, 0x51, 0xCD,
 
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-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
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+	0x10, 0x04,
+	0x08, 0x04,
+	0x00, 0xE0,
 
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
+	0x00, 0xCC, 0xC0, 0xCD,
+	0xD1, 0x49, 0xC0, 0xEC,
 
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
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+	0x8B, 0x3F, 0x20, 0xE9,
 
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
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+	0x49, 0x3C, 0x49, 0xAD,
 
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
+	0x10, 0xCC, 0x10, 0xCD,
+	0x08, 0xCC, 0x08, 0xCD,
 
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
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+	0x1F, 0xF0, 0x41, 0xCD,
 
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
+	0x51, 0x3C, 0x51, 0xAD,
+	0x00, 0x98, 0x80, 0xE9,
 
-0x72, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
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+	0x24, 0x1F, 0x20, 0xE9,
 
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
+	0x15, 0x41, 0x49, 0xBD,
+	0x1D, 0x41, 0x51, 0xBD,
 
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
+	0x2E, 0x41, 0x2A, 0xB8,
+	0x34, 0x53, 0xA0, 0xE8,
 
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
+	0x15, 0x30,
+	0x1D, 0x30,
+	0x58, 0xE3,
+	0x00, 0xE0,
 
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0xB5, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
+	0x24, 0x43, 0xA0, 0xE8,
+	0x2C, 0x4B, 0xA0, 0xE8,
 
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
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+	0x09, 0xE3,
+	0x00, 0xE0,
+	0x1D, 0x72,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0x97, 0x57, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
+	0x6C, 0x64, 0xC8, 0xEC,
+	0x98, 0xE1,
+	0xB5, 0x05,
 
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
+	0xBD, 0x05,
+	0x2E, 0x30,
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-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
+	0x33, 0xC0, 0xA0, 0xE8,
+	0x74, 0x64, 0xC8, 0xEC,
 
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
+	0x40, 0x3C, 0x40, 0xAD,
+	0x32, 0x6A,
+	0x2A, 0x30,
 
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
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+	0x33, 0x6A,
+	0x00, 0xE0,
+	0x28, 0x73,
 
-0x1C, 0x72,
-0x83, 0xE2,
-0x60, 0x80, 0x15, 0xEA,
+	0x1C, 0x72,
+	0x83, 0xE2,
+	0x60, 0x80, 0x15, 0xEA,
 
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
+	0xB8, 0x3D, 0x28, 0xDF,
+	0x30, 0x35, 0x20, 0xDF,
 
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
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+	0x00, 0xE0,
+	0xCC, 0xE2,
+	0x64, 0x72,
 
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
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+	0x2D, 0x42, 0x4A, 0xBF,
 
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
+	0x30, 0x2E, 0x30, 0xDF,
+	0x38, 0x2E, 0x38, 0xDF,
 
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
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+	0x1E, 0x15, 0x45, 0xE9,
 
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
+	0x2B, 0x49, 0x51, 0xBD,
+	0x00, 0xE0,
+	0x1F, 0x73,
 
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
+	0x38, 0x38, 0x40, 0xAF,
+	0x30, 0x30, 0x40, 0xAF,
 
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
+	0x24, 0x1F, 0x24, 0xDF,
+	0x1D, 0x32, 0x20, 0xE9,
 
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
+	0x2C, 0x1F, 0x2C, 0xDF,
+	0x1A, 0x33, 0x20, 0xE9,
 
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
+	0xB0, 0x10,
+	0x08, 0xE3,
+	0x40, 0x10,
+	0xB8, 0x10,
 
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
+	0x26, 0xF0, 0x30, 0xCD,
+	0x2F, 0xF0, 0x38, 0xCD,
 
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
+	0x2B, 0x80, 0x20, 0xE9,
+	0x2A, 0x80, 0x20, 0xE9,
 
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
+	0xA6, 0x20,
+	0x88, 0xE2,
+	0x00, 0xE0,
+	0xAF, 0x20,
 
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
+	0x28, 0x2A, 0x26, 0xAF,
+	0x20, 0x2A, 0xC0, 0xAF,
 
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
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+	0x46, 0x24, 0x46, 0xDF,
 
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
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+	0x20, 0x38, 0x80, 0xBF,
 
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
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+	0x4E, 0x2C, 0x4E, 0xDF,
 
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
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+	0x56, 0x34, 0x56, 0xDF,
 
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
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+	0x20, 0x1D, 0x20, 0xDF,
 
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
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+	0x00, 0xE0,
+	0x1D, 0x05,
 
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
+	0x04, 0x80, 0x10, 0xEA,
+	0x89, 0xE2,
+	0x2B, 0x30,
 
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
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+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
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+	0x00, 0x80, 0x00, 0xE8,
 
-0xA0, 0x68,
-0xBF, 0x25,
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+	0xA0, 0x68,
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-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
+	0x20, 0xC0, 0x20, 0xAF,
+	0x28, 0x05,
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-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
+	0x00, 0xE0,
+	0x2A, 0x10,
+	0x16, 0xC0, 0x20, 0xE9,
 
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
+	0x04, 0x80, 0x10, 0xEA,
+	0x8C, 0xE2,
+	0x95, 0x05,
 
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
+	0x28, 0xC1, 0x28, 0xAD,
+	0x1F, 0xC1, 0x15, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
+	0xA8, 0x67,
+	0x9F, 0x6B,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
+	0x28, 0xC0, 0x28, 0xAD,
+	0x1D, 0x25,
+	0x20, 0x05,
 
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
+	0x28, 0x32, 0x80, 0xAD,
+	0x40, 0x2A, 0x40, 0xBD,
 
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
+	0x1C, 0x80, 0x20, 0xE9,
+	0x20, 0x33, 0x20, 0xAD,
 
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
+	0x20, 0x73,
+	0x00, 0xE0,
+	0xB6, 0x49, 0x51, 0xBB,
 
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
+	0x26, 0x2F, 0xB0, 0xE8,
+	0x19, 0x20, 0x20, 0xE9,
 
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
+	0x35, 0x20, 0x35, 0xDF,
+	0x3D, 0x20, 0x3D, 0xDF,
 
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
+	0x15, 0x20, 0x15, 0xDF,
+	0x1D, 0x20, 0x1D, 0xDF,
 
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
+	0x26, 0xD0, 0x26, 0xCD,
+	0x29, 0x49, 0x2A, 0xB8,
 
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
+	0x26, 0x40, 0x80, 0xBD,
+	0x3B, 0x48, 0x50, 0xBD,
 
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
+	0x3E, 0x54, 0x57, 0x9F,
+	0x00, 0xE0,
+	0x82, 0xE1,
 
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x1E, 0xAF, 0x59, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
+	0x26, 0x30,
+	0x29, 0x30,
+	0x48, 0x3C, 0x48, 0xAD,
 
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
+	0x2B, 0x72,
+	0xC2, 0xE1,
+	0x2C, 0xC0, 0x44, 0xC2,
 
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
+	0x05, 0x24, 0x34, 0xBF,
+	0x0D, 0x24, 0x2C, 0xBF,
 
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
+	0x2D, 0x46, 0x4E, 0xBF,
+	0x25, 0x46, 0x56, 0xBF,
 
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
+	0x20, 0x1D, 0x6F, 0x8F,
+	0x32, 0x3E, 0x5F, 0xE9,
 
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
+	0x3E, 0x50, 0x56, 0x9F,
+	0x00, 0xE0,
+	0x3B, 0x30,
 
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
+	0x1E, 0x8F, 0x51, 0x9F,
+	0x33, 0x1E, 0x5F, 0xE9,
 
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
+	0x05, 0x44, 0x54, 0xB2,
+	0x0D, 0x44, 0x4C, 0xB2,
 
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
+	0x19, 0xC0, 0xB0, 0xE8,
+	0x34, 0xC0, 0x44, 0xC4,
 
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
+	0x33, 0x73,
+	0x00, 0xE0,
+	0x3E, 0x62, 0x57, 0x9F,
 
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
+	0x1E, 0xAF, 0x59, 0x9F,
+	0x00, 0xE0,
+	0x0D, 0x20,
 
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
+	0x84, 0x3E, 0x58, 0xE9,
+	0x28, 0x1D, 0x6F, 0x8F,
 
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
+	0x05, 0x20,
+	0x00, 0xE0,
+	0x85, 0x1E, 0x58, 0xE9,
 
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
+	0x9B, 0x3B, 0x33, 0xDF,
+	0x20, 0x20, 0x42, 0xAF,
 
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
+	0x30, 0x42, 0x56, 0x9F,
+	0x80, 0x3E, 0x57, 0xE9,
 
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
+	0x3F, 0x8F, 0x51, 0x9F,
+	0x30, 0x80, 0x5F, 0xE9,
 
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
+	0x28, 0x28, 0x24, 0xAF,
+	0x81, 0x1E, 0x57, 0xE9,
 
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
+	0x05, 0x47, 0x57, 0xBF,
+	0x0D, 0x47, 0x4F, 0xBF,
 
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
+	0x88, 0x80, 0x58, 0xE9,
+	0x1B, 0x29, 0x1B, 0xDF,
 
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
+	0x30, 0x1D, 0x6F, 0x8F,
+	0x3A, 0x30, 0x4F, 0xE9,
 
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
+	0x1C, 0x30, 0x26, 0xDF,
+	0x09, 0xE3,
+	0x3B, 0x05,
 
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
+	0x3E, 0x50, 0x56, 0x9F,
+	0x3B, 0x3F, 0x4F, 0xE9,
 
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
+	0x1E, 0x8F, 0x51, 0x9F,
+	0x00, 0xE0,
+	0xAC, 0x20,
 
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
+	0x2D, 0x44, 0x4C, 0xB4,
+	0x2C, 0x1C, 0xC0, 0xAF,
 
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
+	0x25, 0x44, 0x54, 0xB4,
+	0x00, 0xE0,
+	0xC8, 0x30,
 
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
+	0x30, 0x46, 0x30, 0xAF,
+	0x1B, 0x1B, 0x48, 0xAF,
 
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
+	0x00, 0xE0,
+	0x25, 0x20,
+	0x38, 0x2C, 0x4F, 0xE9,
 
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
+	0x86, 0x80, 0x57, 0xE9,
+	0x38, 0x1D, 0x6F, 0x8F,
 
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
+	0x28, 0x74,
+	0x00, 0xE0,
+	0x0D, 0x44, 0x4C, 0xB0,
 
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
+	0x05, 0x44, 0x54, 0xB0,
+	0x2D, 0x20,
+	0x9B, 0x10,
 
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
+	0x82, 0x3E, 0x57, 0xE9,
+	0x32, 0xF0, 0x1B, 0xCD,
 
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
+	0x1E, 0xBD, 0x59, 0x9F,
+	0x83, 0x1E, 0x57, 0xE9,
 
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
+	0x38, 0x47, 0x38, 0xAF,
+	0x34, 0x20,
+	0x2A, 0x30,
 
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
+	0x00, 0xE0,
+	0x0D, 0x20,
+	0x32, 0x20,
+	0x05, 0x20,
 
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
+	0x87, 0x80, 0x57, 0xE9,
+	0x1F, 0x54, 0x57, 0x9F,
 
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
+	0x17, 0x42, 0x56, 0x9F,
+	0x00, 0xE0,
+	0x3B, 0x6A,
 
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
+	0x3F, 0x8F, 0x51, 0x9F,
+	0x37, 0x1E, 0x4F, 0xE9,
 
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
+	0x37, 0x32, 0x2A, 0xAF,
+	0x00, 0xE0,
+	0x32, 0x00,
 
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
+	0x00, 0x80, 0x00, 0xE8,
+	0x27, 0xC0, 0x44, 0xC0,
 
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
+	0x36, 0x1F, 0x4F, 0xE9,
+	0x1F, 0x1F, 0x26, 0xDF,
 
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
+	0x37, 0x1B, 0x37, 0xBF,
+	0x17, 0x26, 0x17, 0xDF,
 
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
+	0x3E, 0x17, 0x4F, 0xE9,
+	0x3F, 0x3F, 0x4F, 0xE9,
 
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
+	0x34, 0x1F, 0x34, 0xAF,
+	0x2B, 0x05,
+	0xA7, 0x20,
 
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
+	0x33, 0x2B, 0x37, 0xDF,
+	0x27, 0x17, 0xC0, 0xAF,
 
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x34, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x03, 0x80, 0x0A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
+	0x03, 0x80, 0x0A, 0xEA,
+	0x17, 0xC1, 0x2B, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0x68,
+	0x97, 0x25,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x33, 0xC0, 0x33, 0xAF,
-0x3C, 0x27, 0x4F, 0xE9,
+	0x33, 0xC0, 0x33, 0xAF,
+	0x3C, 0x27, 0x4F, 0xE9,
 
-0x57, 0x39, 0x20, 0xE9,
-0x28, 0x19, 0x60, 0xEC,
+	0x57, 0x39, 0x20, 0xE9,
+	0x28, 0x19, 0x60, 0xEC,
 
-0x2B, 0x32, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
+	0x2B, 0x32, 0x20, 0xE9,
+	0x1D, 0x3B, 0x20, 0xE9,
 
-0xB3, 0x05,
-0x00, 0xE0,
-0x16, 0x28, 0x20, 0xE9,
+	0xB3, 0x05,
+	0x00, 0xE0,
+	0x16, 0x28, 0x20, 0xE9,
 
-0x23, 0x3B, 0x33, 0xAD,
-0x1E, 0x2B, 0x20, 0xE9,
+	0x23, 0x3B, 0x33, 0xAD,
+	0x1E, 0x2B, 0x20, 0xE9,
 
-0x1C, 0x80, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
+	0x1C, 0x80, 0x20, 0xE9,
+	0x57, 0x36, 0x20, 0xE9,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x90, 0xE2,
+	0x00, 0xE0,
 
-0x85, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
+	0x85, 0xFF, 0x20, 0xEA,
+	0x19, 0xC8, 0xC1, 0xCD,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x9F, 0x41, 0x49, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
+	0x25, 0x41, 0x49, 0xBD,
+	0x2D, 0x41, 0x51, 0xBD,
 
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x0D, 0x80, 0x07, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0x35, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
+	0x00, 0x80, 0x00, 0xE8,
+	0x25, 0x30,
+	0x2D, 0x30,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0xA7, 0x5B, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x84, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x84, 0xFF, 0x0A, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC8, 0xEC,
+	0x42, 0xE1,
+	0x00, 0xE0,
 
-0x82, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x82, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0xC8, 0x40, 0xC0, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x7F, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x7F, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
 };
 
 static unsigned char warp_g200_tgza[] = {
 
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x98, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
+	0x81, 0x04,
+	0x89, 0x04,
+	0x01, 0x04,
+	0x09, 0x04,
 
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC0, 0xEC,
+	0x11, 0x04,
+	0x00, 0xE0,
 
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
+	0x41, 0xCC, 0x41, 0xCD,
+	0x49, 0xCC, 0x49, 0xCD,
 
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
+	0xD1, 0x41, 0xC0, 0xEC,
+	0x51, 0xCC, 0x51, 0xCD,
 
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
+	0x80, 0x04,
+	0x10, 0x04,
+	0x08, 0x04,
+	0x00, 0xE0,
 
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
+	0x00, 0xCC, 0xC0, 0xCD,
+	0xD1, 0x49, 0xC0, 0xEC,
 
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
+	0x8A, 0x1F, 0x20, 0xE9,
+	0x8B, 0x3F, 0x20, 0xE9,
 
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
+	0x41, 0x3C, 0x41, 0xAD,
+	0x49, 0x3C, 0x49, 0xAD,
 
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
+	0x10, 0xCC, 0x10, 0xCD,
+	0x08, 0xCC, 0x08, 0xCD,
 
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
+	0xB9, 0x41, 0x49, 0xBB,
+	0x1F, 0xF0, 0x41, 0xCD,
 
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
+	0x51, 0x3C, 0x51, 0xAD,
+	0x00, 0x98, 0x80, 0xE9,
 
-0x7D, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
+	0x7D, 0x80, 0x07, 0xEA,
+	0x24, 0x1F, 0x20, 0xE9,
 
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
+	0x15, 0x41, 0x49, 0xBD,
+	0x1D, 0x41, 0x51, 0xBD,
 
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
+	0x2E, 0x41, 0x2A, 0xB8,
+	0x34, 0x53, 0xA0, 0xE8,
 
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
+	0x15, 0x30,
+	0x1D, 0x30,
+	0x58, 0xE3,
+	0x00, 0xE0,
 
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0xB5, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
+	0x24, 0x43, 0xA0, 0xE8,
+	0x2C, 0x4B, 0xA0, 0xE8,
 
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
+	0x15, 0x72,
+	0x09, 0xE3,
+	0x00, 0xE0,
+	0x1D, 0x72,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0x97, 0x57, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
+	0x6C, 0x64, 0xC8, 0xEC,
+	0x98, 0xE1,
+	0xB5, 0x05,
 
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
+	0xBD, 0x05,
+	0x2E, 0x30,
+	0x32, 0xC0, 0xA0, 0xE8,
 
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
+	0x33, 0xC0, 0xA0, 0xE8,
+	0x74, 0x64, 0xC8, 0xEC,
 
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
+	0x40, 0x3C, 0x40, 0xAD,
+	0x32, 0x6A,
+	0x2A, 0x30,
 
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
+	0x20, 0x73,
+	0x33, 0x6A,
+	0x00, 0xE0,
+	0x28, 0x73,
 
-0x1C, 0x72,
-0x83, 0xE2,
-0x6B, 0x80, 0x15, 0xEA,
+	0x1C, 0x72,
+	0x83, 0xE2,
+	0x6B, 0x80, 0x15, 0xEA,
 
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
+	0xB8, 0x3D, 0x28, 0xDF,
+	0x30, 0x35, 0x20, 0xDF,
 
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
+	0x40, 0x30,
+	0x00, 0xE0,
+	0xCC, 0xE2,
+	0x64, 0x72,
 
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
+	0x25, 0x42, 0x52, 0xBF,
+	0x2D, 0x42, 0x4A, 0xBF,
 
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
+	0x30, 0x2E, 0x30, 0xDF,
+	0x38, 0x2E, 0x38, 0xDF,
 
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
+	0x18, 0x1D, 0x45, 0xE9,
+	0x1E, 0x15, 0x45, 0xE9,
 
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
+	0x2B, 0x49, 0x51, 0xBD,
+	0x00, 0xE0,
+	0x1F, 0x73,
 
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
+	0x38, 0x38, 0x40, 0xAF,
+	0x30, 0x30, 0x40, 0xAF,
 
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
+	0x24, 0x1F, 0x24, 0xDF,
+	0x1D, 0x32, 0x20, 0xE9,
 
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
+	0x2C, 0x1F, 0x2C, 0xDF,
+	0x1A, 0x33, 0x20, 0xE9,
 
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
+	0xB0, 0x10,
+	0x08, 0xE3,
+	0x40, 0x10,
+	0xB8, 0x10,
 
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
+	0x26, 0xF0, 0x30, 0xCD,
+	0x2F, 0xF0, 0x38, 0xCD,
 
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
+	0x2B, 0x80, 0x20, 0xE9,
+	0x2A, 0x80, 0x20, 0xE9,
 
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
+	0xA6, 0x20,
+	0x88, 0xE2,
+	0x00, 0xE0,
+	0xAF, 0x20,
 
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
+	0x28, 0x2A, 0x26, 0xAF,
+	0x20, 0x2A, 0xC0, 0xAF,
 
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
+	0x34, 0x1F, 0x34, 0xDF,
+	0x46, 0x24, 0x46, 0xDF,
 
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
+	0x28, 0x30, 0x80, 0xBF,
+	0x20, 0x38, 0x80, 0xBF,
 
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
+	0x47, 0x24, 0x47, 0xDF,
+	0x4E, 0x2C, 0x4E, 0xDF,
 
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
+	0x4F, 0x2C, 0x4F, 0xDF,
+	0x56, 0x34, 0x56, 0xDF,
 
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
+	0x28, 0x15, 0x28, 0xDF,
+	0x20, 0x1D, 0x20, 0xDF,
 
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
+	0x57, 0x34, 0x57, 0xDF,
+	0x00, 0xE0,
+	0x1D, 0x05,
 
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
+	0x04, 0x80, 0x10, 0xEA,
+	0x89, 0xE2,
+	0x2B, 0x30,
 
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x3F, 0xC1, 0x1D, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
+	0xA0, 0x68,
+	0xBF, 0x25,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
+	0x20, 0xC0, 0x20, 0xAF,
+	0x28, 0x05,
+	0x97, 0x74,
 
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
+	0x00, 0xE0,
+	0x2A, 0x10,
+	0x16, 0xC0, 0x20, 0xE9,
 
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
+	0x04, 0x80, 0x10, 0xEA,
+	0x8C, 0xE2,
+	0x95, 0x05,
 
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
+	0x28, 0xC1, 0x28, 0xAD,
+	0x1F, 0xC1, 0x15, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
+	0xA8, 0x67,
+	0x9F, 0x6B,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
+	0x28, 0xC0, 0x28, 0xAD,
+	0x1D, 0x25,
+	0x20, 0x05,
 
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
+	0x28, 0x32, 0x80, 0xAD,
+	0x40, 0x2A, 0x40, 0xBD,
 
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
+	0x1C, 0x80, 0x20, 0xE9,
+	0x20, 0x33, 0x20, 0xAD,
 
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
+	0x20, 0x73,
+	0x00, 0xE0,
+	0xB6, 0x49, 0x51, 0xBB,
 
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
+	0x26, 0x2F, 0xB0, 0xE8,
+	0x19, 0x20, 0x20, 0xE9,
 
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
+	0x35, 0x20, 0x35, 0xDF,
+	0x3D, 0x20, 0x3D, 0xDF,
 
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
+	0x15, 0x20, 0x15, 0xDF,
+	0x1D, 0x20, 0x1D, 0xDF,
 
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
+	0x26, 0xD0, 0x26, 0xCD,
+	0x29, 0x49, 0x2A, 0xB8,
 
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
+	0x26, 0x40, 0x80, 0xBD,
+	0x3B, 0x48, 0x50, 0xBD,
 
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
+	0x3E, 0x54, 0x57, 0x9F,
+	0x00, 0xE0,
+	0x82, 0xE1,
 
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x1E, 0xAF, 0x59, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
+	0x26, 0x30,
+	0x29, 0x30,
+	0x48, 0x3C, 0x48, 0xAD,
 
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
+	0x2B, 0x72,
+	0xC2, 0xE1,
+	0x2C, 0xC0, 0x44, 0xC2,
 
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
+	0x05, 0x24, 0x34, 0xBF,
+	0x0D, 0x24, 0x2C, 0xBF,
 
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
+	0x2D, 0x46, 0x4E, 0xBF,
+	0x25, 0x46, 0x56, 0xBF,
 
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
+	0x20, 0x1D, 0x6F, 0x8F,
+	0x32, 0x3E, 0x5F, 0xE9,
 
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
+	0x3E, 0x50, 0x56, 0x9F,
+	0x00, 0xE0,
+	0x3B, 0x30,
 
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
+	0x1E, 0x8F, 0x51, 0x9F,
+	0x33, 0x1E, 0x5F, 0xE9,
 
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
+	0x05, 0x44, 0x54, 0xB2,
+	0x0D, 0x44, 0x4C, 0xB2,
 
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
+	0x19, 0xC0, 0xB0, 0xE8,
+	0x34, 0xC0, 0x44, 0xC4,
 
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
+	0x33, 0x73,
+	0x00, 0xE0,
+	0x3E, 0x62, 0x57, 0x9F,
 
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
+	0x1E, 0xAF, 0x59, 0x9F,
+	0x00, 0xE0,
+	0x0D, 0x20,
 
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
+	0x84, 0x3E, 0x58, 0xE9,
+	0x28, 0x1D, 0x6F, 0x8F,
 
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
+	0x05, 0x20,
+	0x00, 0xE0,
+	0x85, 0x1E, 0x58, 0xE9,
 
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
+	0x9B, 0x3B, 0x33, 0xDF,
+	0x20, 0x20, 0x42, 0xAF,
 
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
+	0x30, 0x42, 0x56, 0x9F,
+	0x80, 0x3E, 0x57, 0xE9,
 
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
+	0x3F, 0x8F, 0x51, 0x9F,
+	0x30, 0x80, 0x5F, 0xE9,
 
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
+	0x28, 0x28, 0x24, 0xAF,
+	0x81, 0x1E, 0x57, 0xE9,
 
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
+	0x05, 0x47, 0x57, 0xBF,
+	0x0D, 0x47, 0x4F, 0xBF,
 
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
+	0x88, 0x80, 0x58, 0xE9,
+	0x1B, 0x29, 0x1B, 0xDF,
 
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
+	0x30, 0x1D, 0x6F, 0x8F,
+	0x3A, 0x30, 0x4F, 0xE9,
 
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
+	0x1C, 0x30, 0x26, 0xDF,
+	0x09, 0xE3,
+	0x3B, 0x05,
 
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
+	0x3E, 0x50, 0x56, 0x9F,
+	0x3B, 0x3F, 0x4F, 0xE9,
 
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
+	0x1E, 0x8F, 0x51, 0x9F,
+	0x00, 0xE0,
+	0xAC, 0x20,
 
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
+	0x2D, 0x44, 0x4C, 0xB4,
+	0x2C, 0x1C, 0xC0, 0xAF,
 
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
+	0x25, 0x44, 0x54, 0xB4,
+	0x00, 0xE0,
+	0xC8, 0x30,
 
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
+	0x30, 0x46, 0x30, 0xAF,
+	0x1B, 0x1B, 0x48, 0xAF,
 
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
+	0x00, 0xE0,
+	0x25, 0x20,
+	0x38, 0x2C, 0x4F, 0xE9,
 
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
+	0x86, 0x80, 0x57, 0xE9,
+	0x38, 0x1D, 0x6F, 0x8F,
 
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
+	0x28, 0x74,
+	0x00, 0xE0,
+	0x0D, 0x44, 0x4C, 0xB0,
 
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
+	0x05, 0x44, 0x54, 0xB0,
+	0x2D, 0x20,
+	0x9B, 0x10,
 
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
+	0x82, 0x3E, 0x57, 0xE9,
+	0x32, 0xF0, 0x1B, 0xCD,
 
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
+	0x1E, 0xBD, 0x59, 0x9F,
+	0x83, 0x1E, 0x57, 0xE9,
 
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
+	0x38, 0x47, 0x38, 0xAF,
+	0x34, 0x20,
+	0x2A, 0x30,
 
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
+	0x00, 0xE0,
+	0x0D, 0x20,
+	0x32, 0x20,
+	0x05, 0x20,
 
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
+	0x87, 0x80, 0x57, 0xE9,
+	0x1F, 0x54, 0x57, 0x9F,
 
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
+	0x17, 0x42, 0x56, 0x9F,
+	0x00, 0xE0,
+	0x3B, 0x6A,
 
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
+	0x3F, 0x8F, 0x51, 0x9F,
+	0x37, 0x1E, 0x4F, 0xE9,
 
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
+	0x37, 0x32, 0x2A, 0xAF,
+	0x00, 0xE0,
+	0x32, 0x00,
 
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
+	0x00, 0x80, 0x00, 0xE8,
+	0x27, 0xC0, 0x44, 0xC0,
 
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
+	0x36, 0x1F, 0x4F, 0xE9,
+	0x1F, 0x1F, 0x26, 0xDF,
 
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
+	0x37, 0x1B, 0x37, 0xBF,
+	0x17, 0x26, 0x17, 0xDF,
 
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
+	0x3E, 0x17, 0x4F, 0xE9,
+	0x3F, 0x3F, 0x4F, 0xE9,
 
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
+	0x34, 0x1F, 0x34, 0xAF,
+	0x2B, 0x05,
+	0xA7, 0x20,
 
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
+	0x33, 0x2B, 0x37, 0xDF,
+	0x27, 0x17, 0xC0, 0xAF,
 
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x34, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x2D, 0x44, 0x4C, 0xB6,
-0x25, 0x44, 0x54, 0xB6,
+	0x2D, 0x44, 0x4C, 0xB6,
+	0x25, 0x44, 0x54, 0xB6,
 
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
+	0x03, 0x80, 0x2A, 0xEA,
+	0x17, 0xC1, 0x2B, 0xBD,
 
-0x2D, 0x20,
-0x25, 0x20,
-0x07, 0xC0, 0x44, 0xC6,
+	0x2D, 0x20,
+	0x25, 0x20,
+	0x07, 0xC0, 0x44, 0xC6,
 
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0x68,
+	0x97, 0x25,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x33, 0xC0, 0x33, 0xAF,
-0x3C, 0x27, 0x4F, 0xE9,
+	0x33, 0xC0, 0x33, 0xAF,
+	0x3C, 0x27, 0x4F, 0xE9,
 
-0x1F, 0x62, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x62, 0x57, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x3F, 0x3D, 0x5D, 0x9F,
-0x00, 0xE0,
-0x07, 0x20,
+	0x3F, 0x3D, 0x5D, 0x9F,
+	0x00, 0xE0,
+	0x07, 0x20,
 
-0x00, 0x80, 0x00, 0xE8,
-0x28, 0x19, 0x60, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
+	0x28, 0x19, 0x60, 0xEC,
 
-0xB3, 0x05,
-0x00, 0xE0,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0x05,
+	0x00, 0xE0,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x23, 0x3B, 0x33, 0xAD,
-0x00, 0x80, 0x00, 0xE8,
+	0x23, 0x3B, 0x33, 0xAD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x1F, 0x26, 0x1F, 0xDF,
-0x9D, 0x1F, 0x4F, 0xE9,
+	0x1F, 0x26, 0x1F, 0xDF,
+	0x9D, 0x1F, 0x4F, 0xE9,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x9E, 0x3F, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0x9E, 0x3F, 0x4F, 0xE9,
 
-0x07, 0x07, 0x1F, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
+	0x07, 0x07, 0x1F, 0xAF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x9C, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0x57, 0x39, 0x20, 0xE9,
 
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
+	0x16, 0x28, 0x20, 0xE9,
+	0x1D, 0x3B, 0x20, 0xE9,
 
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
+	0x1E, 0x2B, 0x20, 0xE9,
+	0x2B, 0x32, 0x20, 0xE9,
 
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
+	0x1C, 0x23, 0x20, 0xE9,
+	0x57, 0x36, 0x20, 0xE9,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x90, 0xE2,
+	0x00, 0xE0,
 
-0x7A, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
+	0x7A, 0xFF, 0x20, 0xEA,
+	0x19, 0xC8, 0xC1, 0xCD,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x9F, 0x41, 0x49, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
+	0x25, 0x41, 0x49, 0xBD,
+	0x2D, 0x41, 0x51, 0xBD,
 
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x0D, 0x80, 0x07, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0x35, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
+	0x00, 0x80, 0x00, 0xE8,
+	0x25, 0x30,
+	0x2D, 0x30,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0xA7, 0x5B, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x79, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x79, 0xFF, 0x0A, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC8, 0xEC,
+	0x42, 0xE1,
+	0x00, 0xE0,
 
-0x77, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x77, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0xC8, 0x40, 0xC0, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x74, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x74, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
 };
 
 static unsigned char warp_g200_tgzaf[] = {
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x98, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
+	0x81, 0x04,
+	0x89, 0x04,
+	0x01, 0x04,
+	0x09, 0x04,
 
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC0, 0xEC,
+	0x11, 0x04,
+	0x00, 0xE0,
 
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
+	0x41, 0xCC, 0x41, 0xCD,
+	0x49, 0xCC, 0x49, 0xCD,
 
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
+	0xD1, 0x41, 0xC0, 0xEC,
+	0x51, 0xCC, 0x51, 0xCD,
 
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
+	0x80, 0x04,
+	0x10, 0x04,
+	0x08, 0x04,
+	0x00, 0xE0,
 
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
+	0x00, 0xCC, 0xC0, 0xCD,
+	0xD1, 0x49, 0xC0, 0xEC,
 
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
+	0x8A, 0x1F, 0x20, 0xE9,
+	0x8B, 0x3F, 0x20, 0xE9,
 
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
+	0x41, 0x3C, 0x41, 0xAD,
+	0x49, 0x3C, 0x49, 0xAD,
 
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
+	0x10, 0xCC, 0x10, 0xCD,
+	0x08, 0xCC, 0x08, 0xCD,
 
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
+	0xB9, 0x41, 0x49, 0xBB,
+	0x1F, 0xF0, 0x41, 0xCD,
 
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
+	0x51, 0x3C, 0x51, 0xAD,
+	0x00, 0x98, 0x80, 0xE9,
 
-0x83, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
+	0x83, 0x80, 0x07, 0xEA,
+	0x24, 0x1F, 0x20, 0xE9,
 
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
+	0x21, 0x45, 0x80, 0xE8,
+	0x1A, 0x4D, 0x80, 0xE8,
 
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x55, 0x80, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
+	0x15, 0x41, 0x49, 0xBD,
+	0x1D, 0x41, 0x51, 0xBD,
 
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
+	0x2E, 0x41, 0x2A, 0xB8,
+	0x34, 0x53, 0xA0, 0xE8,
 
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
+	0x15, 0x30,
+	0x1D, 0x30,
+	0x58, 0xE3,
+	0x00, 0xE0,
 
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0xB5, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
+	0x24, 0x43, 0xA0, 0xE8,
+	0x2C, 0x4B, 0xA0, 0xE8,
 
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
+	0x15, 0x72,
+	0x09, 0xE3,
+	0x00, 0xE0,
+	0x1D, 0x72,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0x97, 0x57, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
+	0x6C, 0x64, 0xC8, 0xEC,
+	0x98, 0xE1,
+	0xB5, 0x05,
 
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
+	0xBD, 0x05,
+	0x2E, 0x30,
+	0x32, 0xC0, 0xA0, 0xE8,
 
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
+	0x33, 0xC0, 0xA0, 0xE8,
+	0x74, 0x64, 0xC8, 0xEC,
 
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
+	0x40, 0x3C, 0x40, 0xAD,
+	0x32, 0x6A,
+	0x2A, 0x30,
 
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
+	0x20, 0x73,
+	0x33, 0x6A,
+	0x00, 0xE0,
+	0x28, 0x73,
 
-0x1C, 0x72,
-0x83, 0xE2,
-0x6F, 0x80, 0x15, 0xEA,
+	0x1C, 0x72,
+	0x83, 0xE2,
+	0x6F, 0x80, 0x15, 0xEA,
 
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
+	0xB8, 0x3D, 0x28, 0xDF,
+	0x30, 0x35, 0x20, 0xDF,
 
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
+	0x40, 0x30,
+	0x00, 0xE0,
+	0xCC, 0xE2,
+	0x64, 0x72,
 
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
+	0x25, 0x42, 0x52, 0xBF,
+	0x2D, 0x42, 0x4A, 0xBF,
 
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
+	0x30, 0x2E, 0x30, 0xDF,
+	0x38, 0x2E, 0x38, 0xDF,
 
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
+	0x18, 0x1D, 0x45, 0xE9,
+	0x1E, 0x15, 0x45, 0xE9,
 
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
+	0x2B, 0x49, 0x51, 0xBD,
+	0x00, 0xE0,
+	0x1F, 0x73,
 
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
+	0x38, 0x38, 0x40, 0xAF,
+	0x30, 0x30, 0x40, 0xAF,
 
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
+	0x24, 0x1F, 0x24, 0xDF,
+	0x1D, 0x32, 0x20, 0xE9,
 
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
+	0x2C, 0x1F, 0x2C, 0xDF,
+	0x1A, 0x33, 0x20, 0xE9,
 
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
+	0xB0, 0x10,
+	0x08, 0xE3,
+	0x40, 0x10,
+	0xB8, 0x10,
 
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
+	0x26, 0xF0, 0x30, 0xCD,
+	0x2F, 0xF0, 0x38, 0xCD,
 
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
+	0x2B, 0x80, 0x20, 0xE9,
+	0x2A, 0x80, 0x20, 0xE9,
 
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
+	0xA6, 0x20,
+	0x88, 0xE2,
+	0x00, 0xE0,
+	0xAF, 0x20,
 
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
+	0x28, 0x2A, 0x26, 0xAF,
+	0x20, 0x2A, 0xC0, 0xAF,
 
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
+	0x34, 0x1F, 0x34, 0xDF,
+	0x46, 0x24, 0x46, 0xDF,
 
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
+	0x28, 0x30, 0x80, 0xBF,
+	0x20, 0x38, 0x80, 0xBF,
 
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
+	0x47, 0x24, 0x47, 0xDF,
+	0x4E, 0x2C, 0x4E, 0xDF,
 
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
+	0x4F, 0x2C, 0x4F, 0xDF,
+	0x56, 0x34, 0x56, 0xDF,
 
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
+	0x28, 0x15, 0x28, 0xDF,
+	0x20, 0x1D, 0x20, 0xDF,
 
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
+	0x57, 0x34, 0x57, 0xDF,
+	0x00, 0xE0,
+	0x1D, 0x05,
 
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
+	0x04, 0x80, 0x10, 0xEA,
+	0x89, 0xE2,
+	0x2B, 0x30,
 
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x3F, 0xC1, 0x1D, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
+	0xA0, 0x68,
+	0xBF, 0x25,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
+	0x20, 0xC0, 0x20, 0xAF,
+	0x28, 0x05,
+	0x97, 0x74,
 
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
+	0x00, 0xE0,
+	0x2A, 0x10,
+	0x16, 0xC0, 0x20, 0xE9,
 
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
+	0x04, 0x80, 0x10, 0xEA,
+	0x8C, 0xE2,
+	0x95, 0x05,
 
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
+	0x28, 0xC1, 0x28, 0xAD,
+	0x1F, 0xC1, 0x15, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
+	0xA8, 0x67,
+	0x9F, 0x6B,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
+	0x28, 0xC0, 0x28, 0xAD,
+	0x1D, 0x25,
+	0x20, 0x05,
 
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
+	0x28, 0x32, 0x80, 0xAD,
+	0x40, 0x2A, 0x40, 0xBD,
 
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
+	0x1C, 0x80, 0x20, 0xE9,
+	0x20, 0x33, 0x20, 0xAD,
 
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
+	0x20, 0x73,
+	0x00, 0xE0,
+	0xB6, 0x49, 0x51, 0xBB,
 
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
+	0x26, 0x2F, 0xB0, 0xE8,
+	0x19, 0x20, 0x20, 0xE9,
 
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
+	0x35, 0x20, 0x35, 0xDF,
+	0x3D, 0x20, 0x3D, 0xDF,
 
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
+	0x15, 0x20, 0x15, 0xDF,
+	0x1D, 0x20, 0x1D, 0xDF,
 
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
+	0x26, 0xD0, 0x26, 0xCD,
+	0x29, 0x49, 0x2A, 0xB8,
 
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
+	0x26, 0x40, 0x80, 0xBD,
+	0x3B, 0x48, 0x50, 0xBD,
 
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
+	0x3E, 0x54, 0x57, 0x9F,
+	0x00, 0xE0,
+	0x82, 0xE1,
 
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x1E, 0xAF, 0x59, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
+	0x26, 0x30,
+	0x29, 0x30,
+	0x48, 0x3C, 0x48, 0xAD,
 
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
+	0x2B, 0x72,
+	0xC2, 0xE1,
+	0x2C, 0xC0, 0x44, 0xC2,
 
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
+	0x05, 0x24, 0x34, 0xBF,
+	0x0D, 0x24, 0x2C, 0xBF,
 
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
+	0x2D, 0x46, 0x4E, 0xBF,
+	0x25, 0x46, 0x56, 0xBF,
 
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
+	0x20, 0x1D, 0x6F, 0x8F,
+	0x32, 0x3E, 0x5F, 0xE9,
 
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
+	0x3E, 0x50, 0x56, 0x9F,
+	0x00, 0xE0,
+	0x3B, 0x30,
 
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
+	0x1E, 0x8F, 0x51, 0x9F,
+	0x33, 0x1E, 0x5F, 0xE9,
 
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
+	0x05, 0x44, 0x54, 0xB2,
+	0x0D, 0x44, 0x4C, 0xB2,
 
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
+	0x19, 0xC0, 0xB0, 0xE8,
+	0x34, 0xC0, 0x44, 0xC4,
 
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
+	0x33, 0x73,
+	0x00, 0xE0,
+	0x3E, 0x62, 0x57, 0x9F,
 
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
+	0x1E, 0xAF, 0x59, 0x9F,
+	0x00, 0xE0,
+	0x0D, 0x20,
 
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
+	0x84, 0x3E, 0x58, 0xE9,
+	0x28, 0x1D, 0x6F, 0x8F,
 
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
+	0x05, 0x20,
+	0x00, 0xE0,
+	0x85, 0x1E, 0x58, 0xE9,
 
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
+	0x9B, 0x3B, 0x33, 0xDF,
+	0x20, 0x20, 0x42, 0xAF,
 
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
+	0x30, 0x42, 0x56, 0x9F,
+	0x80, 0x3E, 0x57, 0xE9,
 
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
+	0x3F, 0x8F, 0x51, 0x9F,
+	0x30, 0x80, 0x5F, 0xE9,
 
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
+	0x28, 0x28, 0x24, 0xAF,
+	0x81, 0x1E, 0x57, 0xE9,
 
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
+	0x05, 0x47, 0x57, 0xBF,
+	0x0D, 0x47, 0x4F, 0xBF,
 
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
+	0x88, 0x80, 0x58, 0xE9,
+	0x1B, 0x29, 0x1B, 0xDF,
 
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
+	0x30, 0x1D, 0x6F, 0x8F,
+	0x3A, 0x30, 0x4F, 0xE9,
 
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
+	0x1C, 0x30, 0x26, 0xDF,
+	0x09, 0xE3,
+	0x3B, 0x05,
 
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
+	0x3E, 0x50, 0x56, 0x9F,
+	0x3B, 0x3F, 0x4F, 0xE9,
 
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
+	0x1E, 0x8F, 0x51, 0x9F,
+	0x00, 0xE0,
+	0xAC, 0x20,
 
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
+	0x2D, 0x44, 0x4C, 0xB4,
+	0x2C, 0x1C, 0xC0, 0xAF,
 
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
+	0x25, 0x44, 0x54, 0xB4,
+	0x00, 0xE0,
+	0xC8, 0x30,
 
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
+	0x30, 0x46, 0x30, 0xAF,
+	0x1B, 0x1B, 0x48, 0xAF,
 
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
+	0x00, 0xE0,
+	0x25, 0x20,
+	0x38, 0x2C, 0x4F, 0xE9,
 
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
+	0x86, 0x80, 0x57, 0xE9,
+	0x38, 0x1D, 0x6F, 0x8F,
 
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
+	0x28, 0x74,
+	0x00, 0xE0,
+	0x0D, 0x44, 0x4C, 0xB0,
 
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
+	0x05, 0x44, 0x54, 0xB0,
+	0x2D, 0x20,
+	0x9B, 0x10,
 
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
+	0x82, 0x3E, 0x57, 0xE9,
+	0x32, 0xF0, 0x1B, 0xCD,
 
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
+	0x1E, 0xBD, 0x59, 0x9F,
+	0x83, 0x1E, 0x57, 0xE9,
 
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
+	0x38, 0x47, 0x38, 0xAF,
+	0x34, 0x20,
+	0x2A, 0x30,
 
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
+	0x00, 0xE0,
+	0x0D, 0x20,
+	0x32, 0x20,
+	0x05, 0x20,
 
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
+	0x87, 0x80, 0x57, 0xE9,
+	0x1F, 0x54, 0x57, 0x9F,
 
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
+	0x17, 0x42, 0x56, 0x9F,
+	0x00, 0xE0,
+	0x3B, 0x6A,
 
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
+	0x3F, 0x8F, 0x51, 0x9F,
+	0x37, 0x1E, 0x4F, 0xE9,
 
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
+	0x37, 0x32, 0x2A, 0xAF,
+	0x00, 0xE0,
+	0x32, 0x00,
 
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
+	0x00, 0x80, 0x00, 0xE8,
+	0x27, 0xC0, 0x44, 0xC0,
 
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
+	0x36, 0x1F, 0x4F, 0xE9,
+	0x1F, 0x1F, 0x26, 0xDF,
 
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
+	0x37, 0x1B, 0x37, 0xBF,
+	0x17, 0x26, 0x17, 0xDF,
 
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
+	0x3E, 0x17, 0x4F, 0xE9,
+	0x3F, 0x3F, 0x4F, 0xE9,
 
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
+	0x34, 0x1F, 0x34, 0xAF,
+	0x2B, 0x05,
+	0xA7, 0x20,
 
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
+	0x33, 0x2B, 0x37, 0xDF,
+	0x27, 0x17, 0xC0, 0xAF,
 
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x34, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x0D, 0x21, 0x1A, 0xB6,
-0x05, 0x21, 0x31, 0xB6,
+	0x0D, 0x21, 0x1A, 0xB6,
+	0x05, 0x21, 0x31, 0xB6,
 
-0x2D, 0x44, 0x4C, 0xB6,
-0x25, 0x44, 0x54, 0xB6,
+	0x2D, 0x44, 0x4C, 0xB6,
+	0x25, 0x44, 0x54, 0xB6,
 
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
+	0x03, 0x80, 0x2A, 0xEA,
+	0x17, 0xC1, 0x2B, 0xBD,
 
-0x0D, 0x20,
-0x05, 0x20,
-0x2F, 0xC0, 0x21, 0xC6,
+	0x0D, 0x20,
+	0x05, 0x20,
+	0x2F, 0xC0, 0x21, 0xC6,
 
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0x68,
+	0x97, 0x25,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x33, 0xC0, 0x33, 0xAF,
-0x3C, 0x27, 0x4F, 0xE9,
+	0x33, 0xC0, 0x33, 0xAF,
+	0x3C, 0x27, 0x4F, 0xE9,
 
-0x00, 0xE0,
-0x25, 0x20,
-0x07, 0xC0, 0x44, 0xC6,
+	0x00, 0xE0,
+	0x25, 0x20,
+	0x07, 0xC0, 0x44, 0xC6,
 
-0x17, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x2D, 0x20,
+	0x17, 0x50, 0x56, 0x9F,
+	0x00, 0xE0,
+	0x2D, 0x20,
 
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0xE0,
-0x2F, 0x20,
+	0x37, 0x0F, 0x5C, 0x9F,
+	0x00, 0xE0,
+	0x2F, 0x20,
 
-0x1F, 0x62, 0x57, 0x9F,
-0x00, 0xE0,
-0x07, 0x20,
+	0x1F, 0x62, 0x57, 0x9F,
+	0x00, 0xE0,
+	0x07, 0x20,
 
-0x3F, 0x3D, 0x5D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x3F, 0x3D, 0x5D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x28, 0x19, 0x60, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
+	0x28, 0x19, 0x60, 0xEC,
 
-0xB3, 0x05,
-0x00, 0xE0,
-0x17, 0x26, 0x17, 0xDF,
+	0xB3, 0x05,
+	0x00, 0xE0,
+	0x17, 0x26, 0x17, 0xDF,
 
-0x23, 0x3B, 0x33, 0xAD,
-0x35, 0x17, 0x4F, 0xE9,
+	0x23, 0x3B, 0x33, 0xAD,
+	0x35, 0x17, 0x4F, 0xE9,
 
-0x1F, 0x26, 0x1F, 0xDF,
-0x9D, 0x1F, 0x4F, 0xE9,
+	0x1F, 0x26, 0x1F, 0xDF,
+	0x9D, 0x1F, 0x4F, 0xE9,
 
-0x9E, 0x3F, 0x4F, 0xE9,
-0x39, 0x37, 0x4F, 0xE9,
+	0x9E, 0x3F, 0x4F, 0xE9,
+	0x39, 0x37, 0x4F, 0xE9,
 
-0x2F, 0x2F, 0x17, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
+	0x2F, 0x2F, 0x17, 0xAF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x07, 0x07, 0x1F, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
+	0x07, 0x07, 0x1F, 0xAF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x31, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x9C, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0x57, 0x39, 0x20, 0xE9,
 
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
+	0x16, 0x28, 0x20, 0xE9,
+	0x1D, 0x3B, 0x20, 0xE9,
 
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
+	0x1E, 0x2B, 0x20, 0xE9,
+	0x2B, 0x32, 0x20, 0xE9,
 
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
+	0x1C, 0x23, 0x20, 0xE9,
+	0x57, 0x36, 0x20, 0xE9,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x90, 0xE2,
+	0x00, 0xE0,
 
-0x74, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
+	0x74, 0xFF, 0x20, 0xEA,
+	0x19, 0xC8, 0xC1, 0xCD,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x9F, 0x41, 0x49, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
+	0x25, 0x41, 0x49, 0xBD,
+	0x2D, 0x41, 0x51, 0xBD,
 
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x0D, 0x80, 0x07, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0x35, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
+	0x00, 0x80, 0x00, 0xE8,
+	0x25, 0x30,
+	0x2D, 0x30,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0xA7, 0x5B, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x73, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x73, 0xFF, 0x0A, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC8, 0xEC,
+	0x42, 0xE1,
+	0x00, 0xE0,
 
-0x71, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x71, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0xC8, 0x40, 0xC0, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x6E, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x6E, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
 };
 
 static unsigned char warp_g200_tgzf[] = {
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x98, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
+	0x81, 0x04,
+	0x89, 0x04,
+	0x01, 0x04,
+	0x09, 0x04,
 
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC0, 0xEC,
+	0x11, 0x04,
+	0x00, 0xE0,
 
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
+	0x41, 0xCC, 0x41, 0xCD,
+	0x49, 0xCC, 0x49, 0xCD,
 
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
+	0xD1, 0x41, 0xC0, 0xEC,
+	0x51, 0xCC, 0x51, 0xCD,
 
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
+	0x80, 0x04,
+	0x10, 0x04,
+	0x08, 0x04,
+	0x00, 0xE0,
 
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
+	0x00, 0xCC, 0xC0, 0xCD,
+	0xD1, 0x49, 0xC0, 0xEC,
 
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
+	0x8A, 0x1F, 0x20, 0xE9,
+	0x8B, 0x3F, 0x20, 0xE9,
 
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
+	0x41, 0x3C, 0x41, 0xAD,
+	0x49, 0x3C, 0x49, 0xAD,
 
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
+	0x10, 0xCC, 0x10, 0xCD,
+	0x08, 0xCC, 0x08, 0xCD,
 
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
+	0xB9, 0x41, 0x49, 0xBB,
+	0x1F, 0xF0, 0x41, 0xCD,
 
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
+	0x51, 0x3C, 0x51, 0xAD,
+	0x00, 0x98, 0x80, 0xE9,
 
-0x7F, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
+	0x7F, 0x80, 0x07, 0xEA,
+	0x24, 0x1F, 0x20, 0xE9,
 
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
+	0x21, 0x45, 0x80, 0xE8,
+	0x1A, 0x4D, 0x80, 0xE8,
 
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x55, 0x80, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
+	0x15, 0x41, 0x49, 0xBD,
+	0x1D, 0x41, 0x51, 0xBD,
 
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
+	0x2E, 0x41, 0x2A, 0xB8,
+	0x34, 0x53, 0xA0, 0xE8,
 
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
+	0x15, 0x30,
+	0x1D, 0x30,
+	0x58, 0xE3,
+	0x00, 0xE0,
 
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0xB5, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
+	0x24, 0x43, 0xA0, 0xE8,
+	0x2C, 0x4B, 0xA0, 0xE8,
 
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
+	0x15, 0x72,
+	0x09, 0xE3,
+	0x00, 0xE0,
+	0x1D, 0x72,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0x97, 0x57, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
+	0x6C, 0x64, 0xC8, 0xEC,
+	0x98, 0xE1,
+	0xB5, 0x05,
 
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
+	0xBD, 0x05,
+	0x2E, 0x30,
+	0x32, 0xC0, 0xA0, 0xE8,
 
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
+	0x33, 0xC0, 0xA0, 0xE8,
+	0x74, 0x64, 0xC8, 0xEC,
 
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
+	0x40, 0x3C, 0x40, 0xAD,
+	0x32, 0x6A,
+	0x2A, 0x30,
 
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
+	0x20, 0x73,
+	0x33, 0x6A,
+	0x00, 0xE0,
+	0x28, 0x73,
 
-0x1C, 0x72,
-0x83, 0xE2,
-0x6B, 0x80, 0x15, 0xEA,
+	0x1C, 0x72,
+	0x83, 0xE2,
+	0x6B, 0x80, 0x15, 0xEA,
 
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
+	0xB8, 0x3D, 0x28, 0xDF,
+	0x30, 0x35, 0x20, 0xDF,
 
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
+	0x40, 0x30,
+	0x00, 0xE0,
+	0xCC, 0xE2,
+	0x64, 0x72,
 
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
+	0x25, 0x42, 0x52, 0xBF,
+	0x2D, 0x42, 0x4A, 0xBF,
 
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
+	0x30, 0x2E, 0x30, 0xDF,
+	0x38, 0x2E, 0x38, 0xDF,
 
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
+	0x18, 0x1D, 0x45, 0xE9,
+	0x1E, 0x15, 0x45, 0xE9,
 
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
+	0x2B, 0x49, 0x51, 0xBD,
+	0x00, 0xE0,
+	0x1F, 0x73,
 
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
+	0x38, 0x38, 0x40, 0xAF,
+	0x30, 0x30, 0x40, 0xAF,
 
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
+	0x24, 0x1F, 0x24, 0xDF,
+	0x1D, 0x32, 0x20, 0xE9,
 
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
+	0x2C, 0x1F, 0x2C, 0xDF,
+	0x1A, 0x33, 0x20, 0xE9,
 
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
+	0xB0, 0x10,
+	0x08, 0xE3,
+	0x40, 0x10,
+	0xB8, 0x10,
 
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
+	0x26, 0xF0, 0x30, 0xCD,
+	0x2F, 0xF0, 0x38, 0xCD,
 
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
+	0x2B, 0x80, 0x20, 0xE9,
+	0x2A, 0x80, 0x20, 0xE9,
 
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
+	0xA6, 0x20,
+	0x88, 0xE2,
+	0x00, 0xE0,
+	0xAF, 0x20,
 
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
+	0x28, 0x2A, 0x26, 0xAF,
+	0x20, 0x2A, 0xC0, 0xAF,
 
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
+	0x34, 0x1F, 0x34, 0xDF,
+	0x46, 0x24, 0x46, 0xDF,
 
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
+	0x28, 0x30, 0x80, 0xBF,
+	0x20, 0x38, 0x80, 0xBF,
 
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
+	0x47, 0x24, 0x47, 0xDF,
+	0x4E, 0x2C, 0x4E, 0xDF,
 
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
+	0x4F, 0x2C, 0x4F, 0xDF,
+	0x56, 0x34, 0x56, 0xDF,
 
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
+	0x28, 0x15, 0x28, 0xDF,
+	0x20, 0x1D, 0x20, 0xDF,
 
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
+	0x57, 0x34, 0x57, 0xDF,
+	0x00, 0xE0,
+	0x1D, 0x05,
 
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
+	0x04, 0x80, 0x10, 0xEA,
+	0x89, 0xE2,
+	0x2B, 0x30,
 
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x3F, 0xC1, 0x1D, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
+	0xA0, 0x68,
+	0xBF, 0x25,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
+	0x20, 0xC0, 0x20, 0xAF,
+	0x28, 0x05,
+	0x97, 0x74,
 
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
+	0x00, 0xE0,
+	0x2A, 0x10,
+	0x16, 0xC0, 0x20, 0xE9,
 
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
+	0x04, 0x80, 0x10, 0xEA,
+	0x8C, 0xE2,
+	0x95, 0x05,
 
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
+	0x28, 0xC1, 0x28, 0xAD,
+	0x1F, 0xC1, 0x15, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
+	0xA8, 0x67,
+	0x9F, 0x6B,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
+	0x28, 0xC0, 0x28, 0xAD,
+	0x1D, 0x25,
+	0x20, 0x05,
 
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
+	0x28, 0x32, 0x80, 0xAD,
+	0x40, 0x2A, 0x40, 0xBD,
 
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
+	0x1C, 0x80, 0x20, 0xE9,
+	0x20, 0x33, 0x20, 0xAD,
 
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
+	0x20, 0x73,
+	0x00, 0xE0,
+	0xB6, 0x49, 0x51, 0xBB,
 
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
+	0x26, 0x2F, 0xB0, 0xE8,
+	0x19, 0x20, 0x20, 0xE9,
 
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
+	0x35, 0x20, 0x35, 0xDF,
+	0x3D, 0x20, 0x3D, 0xDF,
 
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
+	0x15, 0x20, 0x15, 0xDF,
+	0x1D, 0x20, 0x1D, 0xDF,
 
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
+	0x26, 0xD0, 0x26, 0xCD,
+	0x29, 0x49, 0x2A, 0xB8,
 
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
+	0x26, 0x40, 0x80, 0xBD,
+	0x3B, 0x48, 0x50, 0xBD,
 
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
+	0x3E, 0x54, 0x57, 0x9F,
+	0x00, 0xE0,
+	0x82, 0xE1,
 
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x1E, 0xAF, 0x59, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
+	0x26, 0x30,
+	0x29, 0x30,
+	0x48, 0x3C, 0x48, 0xAD,
 
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
+	0x2B, 0x72,
+	0xC2, 0xE1,
+	0x2C, 0xC0, 0x44, 0xC2,
 
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
+	0x05, 0x24, 0x34, 0xBF,
+	0x0D, 0x24, 0x2C, 0xBF,
 
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
+	0x2D, 0x46, 0x4E, 0xBF,
+	0x25, 0x46, 0x56, 0xBF,
 
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
+	0x20, 0x1D, 0x6F, 0x8F,
+	0x32, 0x3E, 0x5F, 0xE9,
 
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
+	0x3E, 0x50, 0x56, 0x9F,
+	0x00, 0xE0,
+	0x3B, 0x30,
 
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
+	0x1E, 0x8F, 0x51, 0x9F,
+	0x33, 0x1E, 0x5F, 0xE9,
 
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
+	0x05, 0x44, 0x54, 0xB2,
+	0x0D, 0x44, 0x4C, 0xB2,
 
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
+	0x19, 0xC0, 0xB0, 0xE8,
+	0x34, 0xC0, 0x44, 0xC4,
 
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
+	0x33, 0x73,
+	0x00, 0xE0,
+	0x3E, 0x62, 0x57, 0x9F,
 
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
+	0x1E, 0xAF, 0x59, 0x9F,
+	0x00, 0xE0,
+	0x0D, 0x20,
 
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
+	0x84, 0x3E, 0x58, 0xE9,
+	0x28, 0x1D, 0x6F, 0x8F,
 
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
+	0x05, 0x20,
+	0x00, 0xE0,
+	0x85, 0x1E, 0x58, 0xE9,
 
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
+	0x9B, 0x3B, 0x33, 0xDF,
+	0x20, 0x20, 0x42, 0xAF,
 
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
+	0x30, 0x42, 0x56, 0x9F,
+	0x80, 0x3E, 0x57, 0xE9,
 
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
+	0x3F, 0x8F, 0x51, 0x9F,
+	0x30, 0x80, 0x5F, 0xE9,
 
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
+	0x28, 0x28, 0x24, 0xAF,
+	0x81, 0x1E, 0x57, 0xE9,
 
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
+	0x05, 0x47, 0x57, 0xBF,
+	0x0D, 0x47, 0x4F, 0xBF,
 
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
+	0x88, 0x80, 0x58, 0xE9,
+	0x1B, 0x29, 0x1B, 0xDF,
 
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
+	0x30, 0x1D, 0x6F, 0x8F,
+	0x3A, 0x30, 0x4F, 0xE9,
 
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
+	0x1C, 0x30, 0x26, 0xDF,
+	0x09, 0xE3,
+	0x3B, 0x05,
 
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
+	0x3E, 0x50, 0x56, 0x9F,
+	0x3B, 0x3F, 0x4F, 0xE9,
 
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
+	0x1E, 0x8F, 0x51, 0x9F,
+	0x00, 0xE0,
+	0xAC, 0x20,
 
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
+	0x2D, 0x44, 0x4C, 0xB4,
+	0x2C, 0x1C, 0xC0, 0xAF,
 
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
+	0x25, 0x44, 0x54, 0xB4,
+	0x00, 0xE0,
+	0xC8, 0x30,
 
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
+	0x30, 0x46, 0x30, 0xAF,
+	0x1B, 0x1B, 0x48, 0xAF,
 
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
+	0x00, 0xE0,
+	0x25, 0x20,
+	0x38, 0x2C, 0x4F, 0xE9,
 
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
+	0x86, 0x80, 0x57, 0xE9,
+	0x38, 0x1D, 0x6F, 0x8F,
 
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
+	0x28, 0x74,
+	0x00, 0xE0,
+	0x0D, 0x44, 0x4C, 0xB0,
 
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
+	0x05, 0x44, 0x54, 0xB0,
+	0x2D, 0x20,
+	0x9B, 0x10,
 
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
+	0x82, 0x3E, 0x57, 0xE9,
+	0x32, 0xF0, 0x1B, 0xCD,
 
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
+	0x1E, 0xBD, 0x59, 0x9F,
+	0x83, 0x1E, 0x57, 0xE9,
 
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
+	0x38, 0x47, 0x38, 0xAF,
+	0x34, 0x20,
+	0x2A, 0x30,
 
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
+	0x00, 0xE0,
+	0x0D, 0x20,
+	0x32, 0x20,
+	0x05, 0x20,
 
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
+	0x87, 0x80, 0x57, 0xE9,
+	0x1F, 0x54, 0x57, 0x9F,
 
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
+	0x17, 0x42, 0x56, 0x9F,
+	0x00, 0xE0,
+	0x3B, 0x6A,
 
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
+	0x3F, 0x8F, 0x51, 0x9F,
+	0x37, 0x1E, 0x4F, 0xE9,
 
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
+	0x37, 0x32, 0x2A, 0xAF,
+	0x00, 0xE0,
+	0x32, 0x00,
 
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
+	0x00, 0x80, 0x00, 0xE8,
+	0x27, 0xC0, 0x44, 0xC0,
 
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
+	0x36, 0x1F, 0x4F, 0xE9,
+	0x1F, 0x1F, 0x26, 0xDF,
 
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
+	0x37, 0x1B, 0x37, 0xBF,
+	0x17, 0x26, 0x17, 0xDF,
 
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
+	0x3E, 0x17, 0x4F, 0xE9,
+	0x3F, 0x3F, 0x4F, 0xE9,
 
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
+	0x34, 0x1F, 0x34, 0xAF,
+	0x2B, 0x05,
+	0xA7, 0x20,
 
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
+	0x33, 0x2B, 0x37, 0xDF,
+	0x27, 0x17, 0xC0, 0xAF,
 
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x34, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x0D, 0x21, 0x1A, 0xB6,
-0x05, 0x21, 0x31, 0xB6,
+	0x0D, 0x21, 0x1A, 0xB6,
+	0x05, 0x21, 0x31, 0xB6,
 
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
+	0x03, 0x80, 0x2A, 0xEA,
+	0x17, 0xC1, 0x2B, 0xBD,
 
-0x0D, 0x20,
-0x05, 0x20,
-0x2F, 0xC0, 0x21, 0xC6,
+	0x0D, 0x20,
+	0x05, 0x20,
+	0x2F, 0xC0, 0x21, 0xC6,
 
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0x68,
+	0x97, 0x25,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x33, 0xC0, 0x33, 0xAF,
-0x3C, 0x27, 0x4F, 0xE9,
+	0x33, 0xC0, 0x33, 0xAF,
+	0x3C, 0x27, 0x4F, 0xE9,
 
-0x17, 0x50, 0x56, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x17, 0x50, 0x56, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0xE0,
-0x2F, 0x20,
+	0x37, 0x0F, 0x5C, 0x9F,
+	0x00, 0xE0,
+	0x2F, 0x20,
 
-0x00, 0x80, 0x00, 0xE8,
-0x28, 0x19, 0x60, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
+	0x28, 0x19, 0x60, 0xEC,
 
-0xB3, 0x05,
-0x00, 0xE0,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0x05,
+	0x00, 0xE0,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x23, 0x3B, 0x33, 0xAD,
-0x00, 0x80, 0x00, 0xE8,
+	0x23, 0x3B, 0x33, 0xAD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x17, 0x26, 0x17, 0xDF,
-0x35, 0x17, 0x4F, 0xE9,
+	0x17, 0x26, 0x17, 0xDF,
+	0x35, 0x17, 0x4F, 0xE9,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x39, 0x37, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0x39, 0x37, 0x4F, 0xE9,
 
-0x2F, 0x2F, 0x17, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
+	0x2F, 0x2F, 0x17, 0xAF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x31, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0x57, 0x39, 0x20, 0xE9,
 
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
+	0x16, 0x28, 0x20, 0xE9,
+	0x1D, 0x3B, 0x20, 0xE9,
 
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
+	0x1E, 0x2B, 0x20, 0xE9,
+	0x2B, 0x32, 0x20, 0xE9,
 
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
+	0x1C, 0x23, 0x20, 0xE9,
+	0x57, 0x36, 0x20, 0xE9,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x90, 0xE2,
+	0x00, 0xE0,
 
-0x78, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
+	0x78, 0xFF, 0x20, 0xEA,
+	0x19, 0xC8, 0xC1, 0xCD,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x9F, 0x41, 0x49, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
+	0x25, 0x41, 0x49, 0xBD,
+	0x2D, 0x41, 0x51, 0xBD,
 
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x0D, 0x80, 0x07, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0x35, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
+	0x00, 0x80, 0x00, 0xE8,
+	0x25, 0x30,
+	0x2D, 0x30,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0xA7, 0x5B, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x77, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x77, 0xFF, 0x0A, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC8, 0xEC,
+	0x42, 0xE1,
+	0x00, 0xE0,
 
-0x75, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x75, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0xC8, 0x40, 0xC0, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x72, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x72, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
 };
 
 static unsigned char warp_g200_tgzs[] = {
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x98, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
+	0x81, 0x04,
+	0x89, 0x04,
+	0x01, 0x04,
+	0x09, 0x04,
 
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC0, 0xEC,
+	0x11, 0x04,
+	0x00, 0xE0,
 
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
+	0x41, 0xCC, 0x41, 0xCD,
+	0x49, 0xCC, 0x49, 0xCD,
 
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
+	0xD1, 0x41, 0xC0, 0xEC,
+	0x51, 0xCC, 0x51, 0xCD,
 
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
+	0x80, 0x04,
+	0x10, 0x04,
+	0x08, 0x04,
+	0x00, 0xE0,
 
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
+	0x00, 0xCC, 0xC0, 0xCD,
+	0xD1, 0x49, 0xC0, 0xEC,
 
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
+	0x8A, 0x1F, 0x20, 0xE9,
+	0x8B, 0x3F, 0x20, 0xE9,
 
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
+	0x41, 0x3C, 0x41, 0xAD,
+	0x49, 0x3C, 0x49, 0xAD,
 
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
+	0x10, 0xCC, 0x10, 0xCD,
+	0x08, 0xCC, 0x08, 0xCD,
 
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
+	0xB9, 0x41, 0x49, 0xBB,
+	0x1F, 0xF0, 0x41, 0xCD,
 
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
+	0x51, 0x3C, 0x51, 0xAD,
+	0x00, 0x98, 0x80, 0xE9,
 
-0x8B, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
+	0x8B, 0x80, 0x07, 0xEA,
+	0x24, 0x1F, 0x20, 0xE9,
 
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
+	0x21, 0x45, 0x80, 0xE8,
+	0x1A, 0x4D, 0x80, 0xE8,
 
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x55, 0x80, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
+	0x15, 0x41, 0x49, 0xBD,
+	0x1D, 0x41, 0x51, 0xBD,
 
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
+	0x2E, 0x41, 0x2A, 0xB8,
+	0x34, 0x53, 0xA0, 0xE8,
 
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
+	0x15, 0x30,
+	0x1D, 0x30,
+	0x58, 0xE3,
+	0x00, 0xE0,
 
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0xB5, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
+	0x24, 0x43, 0xA0, 0xE8,
+	0x2C, 0x4B, 0xA0, 0xE8,
 
-0x15, 0x72,
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+	0x25, 0x21, 0x31, 0xB0,
 
-0x0D, 0x21, 0x1A, 0xB2,
-0x05, 0x21, 0x31, 0xB2,
+	0x0D, 0x21, 0x1A, 0xB2,
+	0x05, 0x21, 0x31, 0xB2,
 
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
+	0x03, 0x80, 0x2A, 0xEA,
+	0x17, 0xC1, 0x2B, 0xBD,
 
-0x2D, 0x20,
-0x25, 0x20,
-0x05, 0x20,
-0x0D, 0x20,
+	0x2D, 0x20,
+	0x25, 0x20,
+	0x05, 0x20,
+	0x0D, 0x20,
 
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0x68,
+	0x97, 0x25,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x33, 0xC0, 0x33, 0xAF,
-0x2F, 0xC0, 0x21, 0xC0,
+	0x33, 0xC0, 0x33, 0xAF,
+	0x2F, 0xC0, 0x21, 0xC0,
 
-0x16, 0x42, 0x56, 0x9F,
-0x3C, 0x27, 0x4F, 0xE9,
+	0x16, 0x42, 0x56, 0x9F,
+	0x3C, 0x27, 0x4F, 0xE9,
 
-0x1E, 0x62, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x1E, 0x62, 0x57, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x25, 0x21, 0x31, 0xB4,
-0x2D, 0x21, 0x1A, 0xB4,
+	0x25, 0x21, 0x31, 0xB4,
+	0x2D, 0x21, 0x1A, 0xB4,
 
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x3F, 0x2F, 0x5D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x33, 0x05,
-0x00, 0xE0,
-0x28, 0x19, 0x60, 0xEC,
+	0x33, 0x05,
+	0x00, 0xE0,
+	0x28, 0x19, 0x60, 0xEC,
 
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0xE0,
-0x2F, 0x20,
+	0x37, 0x0F, 0x5C, 0x9F,
+	0x00, 0xE0,
+	0x2F, 0x20,
 
-0x23, 0x3B, 0x33, 0xAD,
-0x1E, 0x26, 0x1E, 0xDF,
+	0x23, 0x3B, 0x33, 0xAD,
+	0x1E, 0x26, 0x1E, 0xDF,
 
-0xA7, 0x1E, 0x4F, 0xE9,
-0x17, 0x26, 0x16, 0xDF,
+	0xA7, 0x1E, 0x4F, 0xE9,
+	0x17, 0x26, 0x16, 0xDF,
 
-0x2D, 0x20,
-0x00, 0xE0,
-0xA8, 0x3F, 0x4F, 0xE9,
+	0x2D, 0x20,
+	0x00, 0xE0,
+	0xA8, 0x3F, 0x4F, 0xE9,
 
-0x2F, 0x2F, 0x1E, 0xAF,
-0x25, 0x20,
-0x00, 0xE0,
+	0x2F, 0x2F, 0x1E, 0xAF,
+	0x25, 0x20,
+	0x00, 0xE0,
 
-0xA4, 0x16, 0x4F, 0xE9,
-0x0F, 0xC0, 0x21, 0xC2,
+	0xA4, 0x16, 0x4F, 0xE9,
+	0x0F, 0xC0, 0x21, 0xC2,
 
-0xA6, 0x80, 0x4F, 0xE9,
-0x1F, 0x62, 0x57, 0x9F,
+	0xA6, 0x80, 0x4F, 0xE9,
+	0x1F, 0x62, 0x57, 0x9F,
 
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0xE0,
-0x8F, 0x20,
+	0x3F, 0x2F, 0x5D, 0x9F,
+	0x00, 0xE0,
+	0x8F, 0x20,
 
-0xA5, 0x37, 0x4F, 0xE9,
-0x0F, 0x17, 0x0F, 0xAF,
+	0xA5, 0x37, 0x4F, 0xE9,
+	0x0F, 0x17, 0x0F, 0xAF,
 
-0x06, 0xC0, 0x21, 0xC4,
-0x00, 0x80, 0x00, 0xE8,
+	0x06, 0xC0, 0x21, 0xC4,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0xA3, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0xA3, 0x80, 0x4F, 0xE9,
 
-0x06, 0x20,
-0x00, 0xE0,
-0x1F, 0x26, 0x1F, 0xDF,
+	0x06, 0x20,
+	0x00, 0xE0,
+	0x1F, 0x26, 0x1F, 0xDF,
 
-0xA1, 0x1F, 0x4F, 0xE9,
-0xA2, 0x3F, 0x4F, 0xE9,
+	0xA1, 0x1F, 0x4F, 0xE9,
+	0xA2, 0x3F, 0x4F, 0xE9,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x06, 0x06, 0x1F, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
+	0x06, 0x06, 0x1F, 0xAF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xA0, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xA0, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0x57, 0x39, 0x20, 0xE9,
 
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
+	0x16, 0x28, 0x20, 0xE9,
+	0x1D, 0x3B, 0x20, 0xE9,
 
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
+	0x1E, 0x2B, 0x20, 0xE9,
+	0x2B, 0x32, 0x20, 0xE9,
 
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
+	0x1C, 0x23, 0x20, 0xE9,
+	0x57, 0x36, 0x20, 0xE9,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x90, 0xE2,
+	0x00, 0xE0,
 
-0x6C, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
+	0x6C, 0xFF, 0x20, 0xEA,
+	0x19, 0xC8, 0xC1, 0xCD,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x9F, 0x41, 0x49, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
+	0x25, 0x41, 0x49, 0xBD,
+	0x2D, 0x41, 0x51, 0xBD,
 
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x0D, 0x80, 0x07, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0x35, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
+	0x00, 0x80, 0x00, 0xE8,
+	0x25, 0x30,
+	0x2D, 0x30,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0xA7, 0x5B, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x6B, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x6B, 0xFF, 0x0A, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC8, 0xEC,
+	0x42, 0xE1,
+	0x00, 0xE0,
 
-0x69, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x69, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0xC8, 0x40, 0xC0, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x66, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x66, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
 };
 
 static unsigned char warp_g200_tgzsa[] = {
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x98, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
+	0x81, 0x04,
+	0x89, 0x04,
+	0x01, 0x04,
+	0x09, 0x04,
 
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC0, 0xEC,
+	0x11, 0x04,
+	0x00, 0xE0,
 
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
+	0x41, 0xCC, 0x41, 0xCD,
+	0x49, 0xCC, 0x49, 0xCD,
 
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
+	0xD1, 0x41, 0xC0, 0xEC,
+	0x51, 0xCC, 0x51, 0xCD,
 
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
+	0x80, 0x04,
+	0x10, 0x04,
+	0x08, 0x04,
+	0x00, 0xE0,
 
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
+	0x00, 0xCC, 0xC0, 0xCD,
+	0xD1, 0x49, 0xC0, 0xEC,
 
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
+	0x8A, 0x1F, 0x20, 0xE9,
+	0x8B, 0x3F, 0x20, 0xE9,
 
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
+	0x41, 0x3C, 0x41, 0xAD,
+	0x49, 0x3C, 0x49, 0xAD,
 
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
+	0x10, 0xCC, 0x10, 0xCD,
+	0x08, 0xCC, 0x08, 0xCD,
 
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
+	0xB9, 0x41, 0x49, 0xBB,
+	0x1F, 0xF0, 0x41, 0xCD,
 
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
+	0x51, 0x3C, 0x51, 0xAD,
+	0x00, 0x98, 0x80, 0xE9,
 
-0x8F, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
+	0x8F, 0x80, 0x07, 0xEA,
+	0x24, 0x1F, 0x20, 0xE9,
 
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
+	0x21, 0x45, 0x80, 0xE8,
+	0x1A, 0x4D, 0x80, 0xE8,
 
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x55, 0x80, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
+	0x15, 0x41, 0x49, 0xBD,
+	0x1D, 0x41, 0x51, 0xBD,
 
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
+	0x2E, 0x41, 0x2A, 0xB8,
+	0x34, 0x53, 0xA0, 0xE8,
 
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
+	0x15, 0x30,
+	0x1D, 0x30,
+	0x58, 0xE3,
+	0x00, 0xE0,
 
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0xB5, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
+	0x24, 0x43, 0xA0, 0xE8,
+	0x2C, 0x4B, 0xA0, 0xE8,
 
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
+	0x15, 0x72,
+	0x09, 0xE3,
+	0x00, 0xE0,
+	0x1D, 0x72,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0x97, 0x57, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
+	0x6C, 0x64, 0xC8, 0xEC,
+	0x98, 0xE1,
+	0xB5, 0x05,
 
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
+	0xBD, 0x05,
+	0x2E, 0x30,
+	0x32, 0xC0, 0xA0, 0xE8,
 
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
+	0x33, 0xC0, 0xA0, 0xE8,
+	0x74, 0x64, 0xC8, 0xEC,
 
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
+	0x40, 0x3C, 0x40, 0xAD,
+	0x32, 0x6A,
+	0x2A, 0x30,
 
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
+	0x20, 0x73,
+	0x33, 0x6A,
+	0x00, 0xE0,
+	0x28, 0x73,
 
-0x1C, 0x72,
-0x83, 0xE2,
-0x7B, 0x80, 0x15, 0xEA,
+	0x1C, 0x72,
+	0x83, 0xE2,
+	0x7B, 0x80, 0x15, 0xEA,
 
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
+	0xB8, 0x3D, 0x28, 0xDF,
+	0x30, 0x35, 0x20, 0xDF,
 
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
+	0x40, 0x30,
+	0x00, 0xE0,
+	0xCC, 0xE2,
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-0x00, 0xE0,
-0x2F, 0x20,
+	0x37, 0x0F, 0x5C, 0x9F,
+	0x00, 0xE0,
+	0x2F, 0x20,
 
-0x23, 0x3B, 0x33, 0xAD,
-0x1E, 0x26, 0x1E, 0xDF,
+	0x23, 0x3B, 0x33, 0xAD,
+	0x1E, 0x26, 0x1E, 0xDF,
 
-0xA7, 0x1E, 0x4F, 0xE9,
-0x17, 0x26, 0x16, 0xDF,
+	0xA7, 0x1E, 0x4F, 0xE9,
+	0x17, 0x26, 0x16, 0xDF,
 
-0x2D, 0x20,
-0x00, 0xE0,
-0xA8, 0x3F, 0x4F, 0xE9,
+	0x2D, 0x20,
+	0x00, 0xE0,
+	0xA8, 0x3F, 0x4F, 0xE9,
 
-0x2F, 0x2F, 0x1E, 0xAF,
-0x25, 0x20,
-0x00, 0xE0,
+	0x2F, 0x2F, 0x1E, 0xAF,
+	0x25, 0x20,
+	0x00, 0xE0,
 
-0xA4, 0x16, 0x4F, 0xE9,
-0x0F, 0xC0, 0x21, 0xC2,
+	0xA4, 0x16, 0x4F, 0xE9,
+	0x0F, 0xC0, 0x21, 0xC2,
 
-0xA6, 0x80, 0x4F, 0xE9,
-0x1F, 0x62, 0x57, 0x9F,
+	0xA6, 0x80, 0x4F, 0xE9,
+	0x1F, 0x62, 0x57, 0x9F,
 
-0x0D, 0x20,
-0x05, 0x20,
-0x00, 0x80, 0x00, 0xE8,
+	0x0D, 0x20,
+	0x05, 0x20,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0xE0,
-0x0F, 0x20,
+	0x3F, 0x2F, 0x5D, 0x9F,
+	0x00, 0xE0,
+	0x0F, 0x20,
 
-0x17, 0x50, 0x56, 0x9F,
-0xA5, 0x37, 0x4F, 0xE9,
+	0x17, 0x50, 0x56, 0x9F,
+	0xA5, 0x37, 0x4F, 0xE9,
 
-0x06, 0xC0, 0x21, 0xC4,
-0x0F, 0x17, 0x0F, 0xAF,
+	0x06, 0xC0, 0x21, 0xC4,
+	0x0F, 0x17, 0x0F, 0xAF,
 
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x37, 0x0F, 0x5C, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x2F, 0xC0, 0x44, 0xC6,
-0xA3, 0x80, 0x4F, 0xE9,
+	0x2F, 0xC0, 0x44, 0xC6,
+	0xA3, 0x80, 0x4F, 0xE9,
 
-0x06, 0x20,
-0x00, 0xE0,
-0x1F, 0x26, 0x1F, 0xDF,
+	0x06, 0x20,
+	0x00, 0xE0,
+	0x1F, 0x26, 0x1F, 0xDF,
 
-0x17, 0x26, 0x17, 0xDF,
-0x9D, 0x17, 0x4F, 0xE9,
+	0x17, 0x26, 0x17, 0xDF,
+	0x9D, 0x17, 0x4F, 0xE9,
 
-0xA1, 0x1F, 0x4F, 0xE9,
-0xA2, 0x3F, 0x4F, 0xE9,
+	0xA1, 0x1F, 0x4F, 0xE9,
+	0xA2, 0x3F, 0x4F, 0xE9,
 
-0x06, 0x06, 0x1F, 0xAF,
-0x00, 0xE0,
-0xAF, 0x20,
+	0x06, 0x06, 0x1F, 0xAF,
+	0x00, 0xE0,
+	0xAF, 0x20,
 
-0x9E, 0x37, 0x4F, 0xE9,
-0x2F, 0x17, 0x2F, 0xAF,
+	0x9E, 0x37, 0x4F, 0xE9,
+	0x2F, 0x17, 0x2F, 0xAF,
 
-0xA0, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xA0, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x9C, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0x80, 0x4F, 0xE9,
 
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0x57, 0x39, 0x20, 0xE9,
 
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
+	0x16, 0x28, 0x20, 0xE9,
+	0x1D, 0x3B, 0x20, 0xE9,
 
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
+	0x1E, 0x2B, 0x20, 0xE9,
+	0x2B, 0x32, 0x20, 0xE9,
 
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
+	0x1C, 0x23, 0x20, 0xE9,
+	0x57, 0x36, 0x20, 0xE9,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x90, 0xE2,
+	0x00, 0xE0,
 
-0x68, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
+	0x68, 0xFF, 0x20, 0xEA,
+	0x19, 0xC8, 0xC1, 0xCD,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x9F, 0x41, 0x49, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
+	0x25, 0x41, 0x49, 0xBD,
+	0x2D, 0x41, 0x51, 0xBD,
 
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x0D, 0x80, 0x07, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0x35, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
+	0x00, 0x80, 0x00, 0xE8,
+	0x25, 0x30,
+	0x2D, 0x30,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0xA7, 0x5B, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x67, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x67, 0xFF, 0x0A, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC8, 0xEC,
+	0x42, 0xE1,
+	0x00, 0xE0,
 
-0x65, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x65, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0xC8, 0x40, 0xC0, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x62, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x62, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
 };
 
 static unsigned char warp_g200_tgzsaf[] = {
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x98, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
+	0x81, 0x04,
+	0x89, 0x04,
+	0x01, 0x04,
+	0x09, 0x04,
 
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC0, 0xEC,
+	0x11, 0x04,
+	0x00, 0xE0,
 
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
+	0x41, 0xCC, 0x41, 0xCD,
+	0x49, 0xCC, 0x49, 0xCD,
 
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
+	0xD1, 0x41, 0xC0, 0xEC,
+	0x51, 0xCC, 0x51, 0xCD,
 
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
+	0x80, 0x04,
+	0x10, 0x04,
+	0x08, 0x04,
+	0x00, 0xE0,
 
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
+	0x00, 0xCC, 0xC0, 0xCD,
+	0xD1, 0x49, 0xC0, 0xEC,
 
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
+	0x8A, 0x1F, 0x20, 0xE9,
+	0x8B, 0x3F, 0x20, 0xE9,
 
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
+	0x41, 0x3C, 0x41, 0xAD,
+	0x49, 0x3C, 0x49, 0xAD,
 
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
+	0x10, 0xCC, 0x10, 0xCD,
+	0x08, 0xCC, 0x08, 0xCD,
 
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
+	0xB9, 0x41, 0x49, 0xBB,
+	0x1F, 0xF0, 0x41, 0xCD,
 
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
+	0x51, 0x3C, 0x51, 0xAD,
+	0x00, 0x98, 0x80, 0xE9,
 
-0x94, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
+	0x94, 0x80, 0x07, 0xEA,
+	0x24, 0x1F, 0x20, 0xE9,
 
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
+	0x21, 0x45, 0x80, 0xE8,
+	0x1A, 0x4D, 0x80, 0xE8,
 
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x55, 0x80, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
+	0x15, 0x41, 0x49, 0xBD,
+	0x1D, 0x41, 0x51, 0xBD,
 
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
+	0x2E, 0x41, 0x2A, 0xB8,
+	0x34, 0x53, 0xA0, 0xE8,
 
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
+	0x15, 0x30,
+	0x1D, 0x30,
+	0x58, 0xE3,
+	0x00, 0xE0,
 
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0xB5, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
+	0x24, 0x43, 0xA0, 0xE8,
+	0x2C, 0x4B, 0xA0, 0xE8,
 
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
+	0x15, 0x72,
+	0x09, 0xE3,
+	0x00, 0xE0,
+	0x1D, 0x72,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0x97, 0x57, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
+	0x6C, 0x64, 0xC8, 0xEC,
+	0x98, 0xE1,
+	0xB5, 0x05,
 
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
+	0xBD, 0x05,
+	0x2E, 0x30,
+	0x32, 0xC0, 0xA0, 0xE8,
 
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
+	0x33, 0xC0, 0xA0, 0xE8,
+	0x74, 0x64, 0xC8, 0xEC,
 
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
+	0x40, 0x3C, 0x40, 0xAD,
+	0x32, 0x6A,
+	0x2A, 0x30,
 
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
+	0x20, 0x73,
+	0x33, 0x6A,
+	0x00, 0xE0,
+	0x28, 0x73,
 
-0x1C, 0x72,
-0x83, 0xE2,
-0x80, 0x80, 0x15, 0xEA,
+	0x1C, 0x72,
+	0x83, 0xE2,
+	0x80, 0x80, 0x15, 0xEA,
 
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
+	0xB8, 0x3D, 0x28, 0xDF,
+	0x30, 0x35, 0x20, 0xDF,
 
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
+	0x40, 0x30,
+	0x00, 0xE0,
+	0xCC, 0xE2,
+	0x64, 0x72,
 
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
+	0x25, 0x42, 0x52, 0xBF,
+	0x2D, 0x42, 0x4A, 0xBF,
 
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
+	0x30, 0x2E, 0x30, 0xDF,
+	0x38, 0x2E, 0x38, 0xDF,
 
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
+	0x18, 0x1D, 0x45, 0xE9,
+	0x1E, 0x15, 0x45, 0xE9,
 
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
+	0x2B, 0x49, 0x51, 0xBD,
+	0x00, 0xE0,
+	0x1F, 0x73,
 
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
+	0x38, 0x38, 0x40, 0xAF,
+	0x30, 0x30, 0x40, 0xAF,
 
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
+	0x24, 0x1F, 0x24, 0xDF,
+	0x1D, 0x32, 0x20, 0xE9,
 
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
+	0x2C, 0x1F, 0x2C, 0xDF,
+	0x1A, 0x33, 0x20, 0xE9,
 
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
+	0xB0, 0x10,
+	0x08, 0xE3,
+	0x40, 0x10,
+	0xB8, 0x10,
 
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
+	0x26, 0xF0, 0x30, 0xCD,
+	0x2F, 0xF0, 0x38, 0xCD,
 
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
+	0x2B, 0x80, 0x20, 0xE9,
+	0x2A, 0x80, 0x20, 0xE9,
 
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
+	0xA6, 0x20,
+	0x88, 0xE2,
+	0x00, 0xE0,
+	0xAF, 0x20,
 
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
+	0x28, 0x2A, 0x26, 0xAF,
+	0x20, 0x2A, 0xC0, 0xAF,
 
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
+	0x34, 0x1F, 0x34, 0xDF,
+	0x46, 0x24, 0x46, 0xDF,
 
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
+	0x28, 0x30, 0x80, 0xBF,
+	0x20, 0x38, 0x80, 0xBF,
 
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
+	0x47, 0x24, 0x47, 0xDF,
+	0x4E, 0x2C, 0x4E, 0xDF,
 
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
+	0x4F, 0x2C, 0x4F, 0xDF,
+	0x56, 0x34, 0x56, 0xDF,
 
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
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-0x2F, 0x20,
-0x00, 0xE0,
-0xA3, 0x0F, 0x4F, 0xE9,
+	0x2F, 0x20,
+	0x00, 0xE0,
+	0xA3, 0x0F, 0x4F, 0xE9,
 
-0x06, 0x20,
-0x00, 0xE0,
-0x1F, 0x26, 0x1F, 0xDF,
+	0x06, 0x20,
+	0x00, 0xE0,
+	0x1F, 0x26, 0x1F, 0xDF,
 
-0x17, 0x26, 0x17, 0xDF,
-0xA1, 0x1F, 0x4F, 0xE9,
+	0x17, 0x26, 0x17, 0xDF,
+	0xA1, 0x1F, 0x4F, 0xE9,
 
-0x1E, 0x26, 0x1E, 0xDF,
-0x9D, 0x1E, 0x4F, 0xE9,
+	0x1E, 0x26, 0x1E, 0xDF,
+	0x9D, 0x1E, 0x4F, 0xE9,
 
-0x35, 0x17, 0x4F, 0xE9,
-0xA2, 0x3F, 0x4F, 0xE9,
+	0x35, 0x17, 0x4F, 0xE9,
+	0xA2, 0x3F, 0x4F, 0xE9,
 
-0x06, 0x06, 0x1F, 0xAF,
-0x39, 0x37, 0x4F, 0xE9,
+	0x06, 0x06, 0x1F, 0xAF,
+	0x39, 0x37, 0x4F, 0xE9,
 
-0x2F, 0x2F, 0x17, 0xAF,
-0x07, 0x07, 0x1E, 0xAF,
+	0x2F, 0x2F, 0x17, 0xAF,
+	0x07, 0x07, 0x1E, 0xAF,
 
-0xA0, 0x80, 0x4F, 0xE9,
-0x9E, 0x3E, 0x4F, 0xE9,
+	0xA0, 0x80, 0x4F, 0xE9,
+	0x9E, 0x3E, 0x4F, 0xE9,
 
-0x31, 0x80, 0x4F, 0xE9,
-0x9C, 0x80, 0x4F, 0xE9,
+	0x31, 0x80, 0x4F, 0xE9,
+	0x9C, 0x80, 0x4F, 0xE9,
 
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0x57, 0x39, 0x20, 0xE9,
 
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
+	0x16, 0x28, 0x20, 0xE9,
+	0x1D, 0x3B, 0x20, 0xE9,
 
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
+	0x1E, 0x2B, 0x20, 0xE9,
+	0x2B, 0x32, 0x20, 0xE9,
 
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
+	0x1C, 0x23, 0x20, 0xE9,
+	0x57, 0x36, 0x20, 0xE9,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x90, 0xE2,
+	0x00, 0xE0,
 
-0x63, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
+	0x63, 0xFF, 0x20, 0xEA,
+	0x19, 0xC8, 0xC1, 0xCD,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x9F, 0x41, 0x49, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
+	0x25, 0x41, 0x49, 0xBD,
+	0x2D, 0x41, 0x51, 0xBD,
 
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x0D, 0x80, 0x07, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0x35, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
+	0x00, 0x80, 0x00, 0xE8,
+	0x25, 0x30,
+	0x2D, 0x30,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0xA7, 0x5B, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x62, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x62, 0xFF, 0x0A, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC8, 0xEC,
+	0x42, 0xE1,
+	0x00, 0xE0,
 
-0x60, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x60, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0xC8, 0x40, 0xC0, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x5D, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x5D, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
 };
 
 static unsigned char warp_g200_tgzsf[] = {
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x98, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
+	0x81, 0x04,
+	0x89, 0x04,
+	0x01, 0x04,
+	0x09, 0x04,
 
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC0, 0xEC,
+	0x11, 0x04,
+	0x00, 0xE0,
 
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
+	0x41, 0xCC, 0x41, 0xCD,
+	0x49, 0xCC, 0x49, 0xCD,
 
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
+	0xD1, 0x41, 0xC0, 0xEC,
+	0x51, 0xCC, 0x51, 0xCD,
 
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
+	0x80, 0x04,
+	0x10, 0x04,
+	0x08, 0x04,
+	0x00, 0xE0,
 
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
+	0x00, 0xCC, 0xC0, 0xCD,
+	0xD1, 0x49, 0xC0, 0xEC,
 
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
+	0x8A, 0x1F, 0x20, 0xE9,
+	0x8B, 0x3F, 0x20, 0xE9,
 
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
+	0x41, 0x3C, 0x41, 0xAD,
+	0x49, 0x3C, 0x49, 0xAD,
 
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
+	0x10, 0xCC, 0x10, 0xCD,
+	0x08, 0xCC, 0x08, 0xCD,
 
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
+	0xB9, 0x41, 0x49, 0xBB,
+	0x1F, 0xF0, 0x41, 0xCD,
 
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
+	0x51, 0x3C, 0x51, 0xAD,
+	0x00, 0x98, 0x80, 0xE9,
 
-0x8F, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
+	0x8F, 0x80, 0x07, 0xEA,
+	0x24, 0x1F, 0x20, 0xE9,
 
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
+	0x21, 0x45, 0x80, 0xE8,
+	0x1A, 0x4D, 0x80, 0xE8,
 
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x55, 0x80, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
+	0x15, 0x41, 0x49, 0xBD,
+	0x1D, 0x41, 0x51, 0xBD,
 
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
+	0x2E, 0x41, 0x2A, 0xB8,
+	0x34, 0x53, 0xA0, 0xE8,
 
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
+	0x15, 0x30,
+	0x1D, 0x30,
+	0x58, 0xE3,
+	0x00, 0xE0,
 
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0xB5, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
+	0x24, 0x43, 0xA0, 0xE8,
+	0x2C, 0x4B, 0xA0, 0xE8,
 
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
+	0x15, 0x72,
+	0x09, 0xE3,
+	0x00, 0xE0,
+	0x1D, 0x72,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0x97, 0x57, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
+	0x6C, 0x64, 0xC8, 0xEC,
+	0x98, 0xE1,
+	0xB5, 0x05,
 
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
+	0xBD, 0x05,
+	0x2E, 0x30,
+	0x32, 0xC0, 0xA0, 0xE8,
 
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
+	0x33, 0xC0, 0xA0, 0xE8,
+	0x74, 0x64, 0xC8, 0xEC,
 
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
+	0x40, 0x3C, 0x40, 0xAD,
+	0x32, 0x6A,
+	0x2A, 0x30,
 
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
+	0x20, 0x73,
+	0x33, 0x6A,
+	0x00, 0xE0,
+	0x28, 0x73,
 
-0x1C, 0x72,
-0x83, 0xE2,
-0x7B, 0x80, 0x15, 0xEA,
+	0x1C, 0x72,
+	0x83, 0xE2,
+	0x7B, 0x80, 0x15, 0xEA,
 
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
+	0xB8, 0x3D, 0x28, 0xDF,
+	0x30, 0x35, 0x20, 0xDF,
 
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
+	0x40, 0x30,
+	0x00, 0xE0,
+	0xCC, 0xE2,
+	0x64, 0x72,
 
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
+	0x25, 0x42, 0x52, 0xBF,
+	0x2D, 0x42, 0x4A, 0xBF,
 
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
+	0x30, 0x2E, 0x30, 0xDF,
+	0x38, 0x2E, 0x38, 0xDF,
 
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
+	0x18, 0x1D, 0x45, 0xE9,
+	0x1E, 0x15, 0x45, 0xE9,
 
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
+	0x2B, 0x49, 0x51, 0xBD,
+	0x00, 0xE0,
+	0x1F, 0x73,
 
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
+	0x38, 0x38, 0x40, 0xAF,
+	0x30, 0x30, 0x40, 0xAF,
 
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
+	0x24, 0x1F, 0x24, 0xDF,
+	0x1D, 0x32, 0x20, 0xE9,
 
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
+	0x2C, 0x1F, 0x2C, 0xDF,
+	0x1A, 0x33, 0x20, 0xE9,
 
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
+	0xB0, 0x10,
+	0x08, 0xE3,
+	0x40, 0x10,
+	0xB8, 0x10,
 
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
+	0x26, 0xF0, 0x30, 0xCD,
+	0x2F, 0xF0, 0x38, 0xCD,
 
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
+	0x2B, 0x80, 0x20, 0xE9,
+	0x2A, 0x80, 0x20, 0xE9,
 
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
+	0xA6, 0x20,
+	0x88, 0xE2,
+	0x00, 0xE0,
+	0xAF, 0x20,
 
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
+	0x28, 0x2A, 0x26, 0xAF,
+	0x20, 0x2A, 0xC0, 0xAF,
 
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
+	0x34, 0x1F, 0x34, 0xDF,
+	0x46, 0x24, 0x46, 0xDF,
 
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
+	0x28, 0x30, 0x80, 0xBF,
+	0x20, 0x38, 0x80, 0xBF,
 
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
+	0x47, 0x24, 0x47, 0xDF,
+	0x4E, 0x2C, 0x4E, 0xDF,
 
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
+	0x4F, 0x2C, 0x4F, 0xDF,
+	0x56, 0x34, 0x56, 0xDF,
 
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
+	0x28, 0x15, 0x28, 0xDF,
+	0x20, 0x1D, 0x20, 0xDF,
 
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
+	0x57, 0x34, 0x57, 0xDF,
+	0x00, 0xE0,
+	0x1D, 0x05,
 
-0x04, 0x80, 0x10, 0xEA,
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+	0x00, 0x80, 0x00, 0xE8,
 
-0xA0, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xA0, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x31, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x80, 0x4F, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
+	0x57, 0x39, 0x20, 0xE9,
 
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
+	0x16, 0x28, 0x20, 0xE9,
+	0x1D, 0x3B, 0x20, 0xE9,
 
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
+	0x1E, 0x2B, 0x20, 0xE9,
+	0x2B, 0x32, 0x20, 0xE9,
 
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
+	0x1C, 0x23, 0x20, 0xE9,
+	0x57, 0x36, 0x20, 0xE9,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x40, 0x40, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x90, 0xE2,
+	0x00, 0xE0,
 
-0x68, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
+	0x68, 0xFF, 0x20, 0xEA,
+	0x19, 0xC8, 0xC1, 0xCD,
 
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
+	0x1F, 0xD7, 0x18, 0xBD,
+	0x3F, 0xD7, 0x22, 0xBD,
 
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
+	0x9F, 0x41, 0x49, 0xBD,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
+	0x25, 0x41, 0x49, 0xBD,
+	0x2D, 0x41, 0x51, 0xBD,
 
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x0D, 0x80, 0x07, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
+	0x35, 0x40, 0x48, 0xBD,
+	0x3D, 0x40, 0x50, 0xBD,
 
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
+	0x00, 0x80, 0x00, 0xE8,
+	0x25, 0x30,
+	0x2D, 0x30,
 
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
+	0x35, 0x30,
+	0xB5, 0x30,
+	0xBD, 0x30,
+	0x3D, 0x30,
 
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x9C, 0xA7, 0x5B, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x67, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x67, 0xFF, 0x0A, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
+	0xC9, 0x41, 0xC8, 0xEC,
+	0x42, 0xE1,
+	0x00, 0xE0,
 
-0x65, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x65, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0xC8, 0x40, 0xC0, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x62, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0x62, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
 };
 
 static unsigned char warp_g400_t2gz[] = {
 
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x8A, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
+	0x0A, 0x40, 0x50, 0xBF,
+	0x2A, 0x40, 0x60, 0xBF,
 
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
+	0x32, 0x41, 0x51, 0xBF,
+	0x3A, 0x41, 0x61, 0xBF,
 
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xD3, 0x6B,
+	0x00, 0x8A, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
+	0xAD, 0xEE, 0x23, 0x9F,
+	0x00, 0xE0,
+	0x51, 0x04,
 
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x61, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
+	0x51, 0x41, 0xE0, 0xEC,
+	0x39, 0x67, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x63, 0xA0, 0xE8,
 
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x61, 0x41, 0xE0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x78, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
+	0x78, 0x80, 0x15, 0xEA,
+	0x10, 0x04,
+	0x20, 0x04,
 
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x61, 0x51, 0xE0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
+	0x2A, 0x42, 0x52, 0xBF,
+	0x0F, 0x52, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
+	0x1A, 0x42, 0x62, 0xBF,
+	0x1E, 0x51, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x0E, 0x61, 0x60, 0xEA,
 
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
+	0x32, 0x40, 0x50, 0xBD,
+	0x22, 0x40, 0x60, 0xBD,
 
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
+	0x12, 0x41, 0x51, 0xBD,
+	0x3A, 0x41, 0x61, 0xBD,
 
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x0E, 0xBD,
+	0x97, 0xE2,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
+	0x35, 0x48, 0xB1, 0xE8,
+	0x3D, 0x59, 0xB1, 0xE8,
 
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x66, 0x31, 0x66, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
+	0x67, 0x39, 0x67, 0xBF,
 
-0x69, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x69, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x35, 0x00,
+	0x3D, 0x00,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0x8D, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
+	0x43, 0x75, 0xF8, 0xEC,
+	0x35, 0x20,
+	0x3D, 0x20,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x53, 0x53, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x0E, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
+	0x48, 0x35, 0x48, 0xBF,
+	0x58, 0x35, 0x58, 0xBF,
 
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
+	0x68, 0x35, 0x68, 0xBF,
+	0x49, 0x3D, 0x49, 0xBF,
 
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
+	0x59, 0x3D, 0x59, 0xBF,
+	0x69, 0x3D, 0x69, 0xBF,
 
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
+	0x63, 0x63, 0x2D, 0xDF,
+	0x4D, 0x7D, 0xF8, 0xEC,
 
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
+	0x59, 0xE3,
+	0x00, 0xE0,
+	0xB8, 0x38, 0x33, 0xBF,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x18, 0x3A, 0x41, 0xE9,
 
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
+	0x3F, 0x53, 0xA0, 0xE8,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x63, 0xA0, 0xE8,
 
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
+	0x50, 0x70, 0xF8, 0xEC,
+	0x2B, 0x50, 0x3C, 0xE9,
 
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x0F, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0x59, 0x78, 0xF8, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x56, 0x3F, 0x56, 0xDF,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x66, 0x3D, 0x66, 0xDF,
 
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
+	0x1D, 0x32, 0x41, 0xE9,
+	0x67, 0x3D, 0x67, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3F, 0x57, 0xDF,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x59, 0x3F, 0x59, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x69, 0x3D, 0x69, 0xDF,
 
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
+	0x48, 0x37, 0x48, 0xDF,
+	0x58, 0x3F, 0x58, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
+	0x68, 0x3D, 0x68, 0xDF,
+	0x49, 0x37, 0x49, 0xDF,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x80, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x34, 0x80, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
+	0x0A, 0x44, 0x54, 0xB0,
+	0x02, 0x44, 0x64, 0xB0,
 
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
+	0x2A, 0x44, 0x54, 0xB2,
+	0x1A, 0x44, 0x64, 0xB2,
 
-0x25, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x25, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x3D, 0xCF, 0x74, 0xC2,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x3D, 0xCF, 0x74, 0xC2,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x2A, 0x44, 0x54, 0xB4,
-0x1A, 0x44, 0x64, 0xB4,
+	0x2A, 0x44, 0x54, 0xB4,
+	0x1A, 0x44, 0x64, 0xB4,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x38, 0x3D, 0x20, 0xE9,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
+	0x2A, 0x46, 0x56, 0xBF,
+	0x1A, 0x46, 0x66, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
+	0x0A, 0x47, 0x57, 0xBF,
+	0x02, 0x47, 0x67, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
+	0x2A, 0x43, 0x53, 0xBF,
+	0x1A, 0x43, 0x63, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x36, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x37, 0x39, 0x4F, 0xE9,
 
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
+	0x0A, 0x48, 0x58, 0xBF,
+	0x02, 0x48, 0x68, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
+	0x2A, 0x49, 0x59, 0xBF,
+	0x1A, 0x49, 0x69, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x82, 0x30, 0x57, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x83, 0x38, 0x57, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x84, 0x31, 0x5E, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x85, 0x39, 0x5E, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
+	0x87, 0x77, 0x57, 0xE9,
+	0x8B, 0x3E, 0xBF, 0xEA,
 
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
+	0x80, 0x30, 0x57, 0xE9,
+	0x81, 0x38, 0x57, 0xE9,
 
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
+	0x82, 0x31, 0x57, 0xE9,
+	0x86, 0x78, 0x57, 0xE9,
 
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
+	0x83, 0x39, 0x57, 0xE9,
+	0x87, 0x79, 0x57, 0xE9,
 
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
+	0x8A, 0x34, 0x20, 0xE9,
 
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
+	0x8B, 0x3C, 0x20, 0xE9,
+	0x37, 0x50, 0x60, 0xBD,
 
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
+	0x57, 0x0D, 0x20, 0xE9,
+	0x35, 0x51, 0x61, 0xBD,
 
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x50, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x0E, 0x77,
 
-0x24, 0x51, 0x20, 0xE9,
-0x9F, 0xFF, 0x20, 0xEA,
+	0x24, 0x51, 0x20, 0xE9,
+	0x9F, 0xFF, 0x20, 0xEA,
 
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x0E, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
+	0x0B, 0x46, 0xA0, 0xE8,
+	0x1B, 0x56, 0xA0, 0xE8,
 
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
+	0x2B, 0x66, 0xA0, 0xE8,
+	0x0C, 0x47, 0xA0, 0xE8,
 
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
+	0x1C, 0x57, 0xA0, 0xE8,
+	0x2C, 0x67, 0xA0, 0xE8,
 
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x0B, 0x00,
+	0x1B, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x0C, 0x00,
+	0x1C, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x0B, 0x65,
+	0x1B, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x0C, 0x65,
+	0x1C, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x0B, 0x1B, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x0C, 0x1C, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x57, 0x80, 0x57, 0xCF,
 
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x66, 0x33, 0x66, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x67, 0x3B, 0x67, 0xCF,
 
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
+	0x0B, 0x48, 0xA0, 0xE8,
+	0x1B, 0x58, 0xA0, 0xE8,
 
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
+	0x2B, 0x68, 0xA0, 0xE8,
+	0x0C, 0x49, 0xA0, 0xE8,
 
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
+	0x1C, 0x59, 0xA0, 0xE8,
+	0x2C, 0x69, 0xA0, 0xE8,
 
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x0B, 0x00,
+	0x1B, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x0C, 0x00,
+	0x1C, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x0B, 0x65,
+	0x1B, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x0C, 0x65,
+	0x1C, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
+	0x0B, 0x1B, 0x60, 0xEC,
+	0x34, 0xD7, 0x34, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x0C, 0x1C, 0x60, 0xEC,
 
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3C, 0xD7, 0x3C, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
+	0x34, 0x80, 0x34, 0xBD,
+	0x3C, 0x80, 0x3C, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
+	0x48, 0x80, 0x48, 0xCF,
+	0x59, 0x80, 0x59, 0xCF,
 
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
+	0x68, 0x33, 0x68, 0xCF,
+	0x49, 0x3B, 0x49, 0xCF,
 
-0xBE, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xBE, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
+	0x58, 0x33, 0x58, 0xCF,
+	0x69, 0x3B, 0x69, 0xCF,
 
-0x7D, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x7D, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_t2gza[] = {
 
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x8A, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
+	0x0A, 0x40, 0x50, 0xBF,
+	0x2A, 0x40, 0x60, 0xBF,
 
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
+	0x32, 0x41, 0x51, 0xBF,
+	0x3A, 0x41, 0x61, 0xBF,
 
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xD3, 0x6B,
+	0x00, 0x8A, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
+	0xAD, 0xEE, 0x23, 0x9F,
+	0x00, 0xE0,
+	0x51, 0x04,
 
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x61, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
+	0x51, 0x41, 0xE0, 0xEC,
+	0x39, 0x67, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x63, 0xA0, 0xE8,
 
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x61, 0x41, 0xE0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x7C, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
+	0x7C, 0x80, 0x15, 0xEA,
+	0x10, 0x04,
+	0x20, 0x04,
 
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x61, 0x51, 0xE0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
+	0x2A, 0x42, 0x52, 0xBF,
+	0x0F, 0x52, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
+	0x1A, 0x42, 0x62, 0xBF,
+	0x1E, 0x51, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x0E, 0x61, 0x60, 0xEA,
 
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
+	0x32, 0x40, 0x50, 0xBD,
+	0x22, 0x40, 0x60, 0xBD,
 
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
+	0x12, 0x41, 0x51, 0xBD,
+	0x3A, 0x41, 0x61, 0xBD,
 
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x0E, 0xBD,
+	0x97, 0xE2,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
+	0x35, 0x48, 0xB1, 0xE8,
+	0x3D, 0x59, 0xB1, 0xE8,
 
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x66, 0x31, 0x66, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
+	0x67, 0x39, 0x67, 0xBF,
 
-0x6D, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x6D, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x35, 0x00,
+	0x3D, 0x00,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0x8D, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
+	0x43, 0x75, 0xF8, 0xEC,
+	0x35, 0x20,
+	0x3D, 0x20,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x53, 0x53, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x0E, 0xBD,
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+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
+	0x34, 0x80, 0x34, 0xBD,
+	0x3C, 0x80, 0x3C, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
+	0x48, 0x80, 0x48, 0xCF,
+	0x59, 0x80, 0x59, 0xCF,
 
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
+	0x68, 0x33, 0x68, 0xCF,
+	0x49, 0x3B, 0x49, 0xCF,
 
-0xBA, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xBA, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
+	0x58, 0x33, 0x58, 0xCF,
+	0x69, 0x3B, 0x69, 0xCF,
 
-0x79, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x79, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_t2gzaf[] = {
 
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x8A, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
+	0x0A, 0x40, 0x50, 0xBF,
+	0x2A, 0x40, 0x60, 0xBF,
 
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
+	0x32, 0x41, 0x51, 0xBF,
+	0x3A, 0x41, 0x61, 0xBF,
 
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xD3, 0x6B,
+	0x00, 0x8A, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
+	0xAD, 0xEE, 0x23, 0x9F,
+	0x00, 0xE0,
+	0x51, 0x04,
 
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x61, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
+	0x51, 0x41, 0xE0, 0xEC,
+	0x39, 0x67, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x63, 0xA0, 0xE8,
 
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x61, 0x41, 0xE0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x81, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
+	0x81, 0x80, 0x15, 0xEA,
+	0x10, 0x04,
+	0x20, 0x04,
 
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x61, 0x51, 0xE0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
+	0x2A, 0x42, 0x52, 0xBF,
+	0x0F, 0x52, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
+	0x1A, 0x42, 0x62, 0xBF,
+	0x1E, 0x51, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x0E, 0x61, 0x60, 0xEA,
 
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
+	0x32, 0x40, 0x50, 0xBD,
+	0x22, 0x40, 0x60, 0xBD,
 
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
+	0x12, 0x41, 0x51, 0xBD,
+	0x3A, 0x41, 0x61, 0xBD,
 
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x0E, 0xBD,
+	0x97, 0xE2,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
+	0x35, 0x48, 0xB1, 0xE8,
+	0x3D, 0x59, 0xB1, 0xE8,
 
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x66, 0x31, 0x66, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
+	0x67, 0x39, 0x67, 0xBF,
 
-0x72, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x72, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x35, 0x00,
+	0x3D, 0x00,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0x8D, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
+	0x43, 0x75, 0xF8, 0xEC,
+	0x35, 0x20,
+	0x3D, 0x20,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x53, 0x53, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x0E, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
+	0x48, 0x35, 0x48, 0xBF,
+	0x58, 0x35, 0x58, 0xBF,
 
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
+	0x68, 0x35, 0x68, 0xBF,
+	0x49, 0x3D, 0x49, 0xBF,
 
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
+	0x59, 0x3D, 0x59, 0xBF,
+	0x69, 0x3D, 0x69, 0xBF,
 
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
+	0x63, 0x63, 0x2D, 0xDF,
+	0x4D, 0x7D, 0xF8, 0xEC,
 
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
+	0x59, 0xE3,
+	0x00, 0xE0,
+	0xB8, 0x38, 0x33, 0xBF,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x18, 0x3A, 0x41, 0xE9,
 
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
+	0x3F, 0x53, 0xA0, 0xE8,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x63, 0xA0, 0xE8,
 
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
+	0x50, 0x70, 0xF8, 0xEC,
+	0x2B, 0x50, 0x3C, 0xE9,
 
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x0F, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0x59, 0x78, 0xF8, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x56, 0x3F, 0x56, 0xDF,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x66, 0x3D, 0x66, 0xDF,
 
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
+	0x1D, 0x32, 0x41, 0xE9,
+	0x67, 0x3D, 0x67, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3F, 0x57, 0xDF,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x59, 0x3F, 0x59, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x69, 0x3D, 0x69, 0xDF,
 
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
+	0x48, 0x37, 0x48, 0xDF,
+	0x58, 0x3F, 0x58, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
+	0x68, 0x3D, 0x68, 0xDF,
+	0x49, 0x37, 0x49, 0xDF,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
+	0x0A, 0x44, 0x54, 0xB0,
+	0x02, 0x44, 0x64, 0xB0,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x37, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x34, 0x37, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
+	0x2A, 0x44, 0x54, 0xB2,
+	0x1A, 0x44, 0x64, 0xB2,
 
-0x2E, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x2E, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x3D, 0xCF, 0x74, 0xC2,
-0x0F, 0xCF, 0x74, 0xC6,
+	0x3D, 0xCF, 0x74, 0xC2,
+	0x0F, 0xCF, 0x74, 0xC6,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x0F, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x9C, 0x0F, 0x20, 0xE9,
 
-0x0A, 0x44, 0x54, 0xB4,
-0x02, 0x44, 0x64, 0xB4,
+	0x0A, 0x44, 0x54, 0xB4,
+	0x02, 0x44, 0x64, 0xB4,
 
-0x2A, 0x44, 0x54, 0xB6,
-0x1A, 0x44, 0x64, 0xB6,
+	0x2A, 0x44, 0x54, 0xB6,
+	0x1A, 0x44, 0x64, 0xB6,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x38, 0x3D, 0x20, 0xE9,
 
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x0A, 0x20,
+	0x02, 0x20,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x3D, 0xCF, 0x75, 0xC6,
-0x00, 0x80, 0x00, 0xE8,
+	0x3D, 0xCF, 0x75, 0xC6,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x0A, 0x45, 0x55, 0xB6,
-0x02, 0x45, 0x65, 0xB6,
+	0x0A, 0x45, 0x55, 0xB6,
+	0x02, 0x45, 0x65, 0xB6,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x31, 0x3D, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0x31, 0x3D, 0x20, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
+	0x2A, 0x46, 0x56, 0xBF,
+	0x1A, 0x46, 0x66, 0xBF,
 
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
+	0x0A, 0x47, 0x57, 0xBF,
+	0x02, 0x47, 0x67, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x36, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x37, 0x38, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x9D, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x9E, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
+	0x2A, 0x43, 0x53, 0xBF,
+	0x1A, 0x43, 0x63, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x35, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x39, 0x38, 0x4F, 0xE9,
 
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
+	0x0A, 0x48, 0x58, 0xBF,
+	0x02, 0x48, 0x68, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
+	0x2A, 0x49, 0x59, 0xBF,
+	0x1A, 0x49, 0x69, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x82, 0x30, 0x57, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x83, 0x38, 0x57, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x84, 0x31, 0x5E, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x85, 0x39, 0x5E, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
+	0x87, 0x77, 0x57, 0xE9,
+	0x8B, 0x3E, 0xBF, 0xEA,
 
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
+	0x80, 0x30, 0x57, 0xE9,
+	0x81, 0x38, 0x57, 0xE9,
 
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
+	0x82, 0x31, 0x57, 0xE9,
+	0x86, 0x78, 0x57, 0xE9,
 
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
+	0x83, 0x39, 0x57, 0xE9,
+	0x87, 0x79, 0x57, 0xE9,
 
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
+	0x8A, 0x34, 0x20, 0xE9,
 
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
+	0x8B, 0x3C, 0x20, 0xE9,
+	0x37, 0x50, 0x60, 0xBD,
 
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
+	0x57, 0x0D, 0x20, 0xE9,
+	0x35, 0x51, 0x61, 0xBD,
 
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x50, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x0E, 0x77,
 
-0x24, 0x51, 0x20, 0xE9,
-0x96, 0xFF, 0x20, 0xEA,
+	0x24, 0x51, 0x20, 0xE9,
+	0x96, 0xFF, 0x20, 0xEA,
 
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x0E, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
+	0x0B, 0x46, 0xA0, 0xE8,
+	0x1B, 0x56, 0xA0, 0xE8,
 
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
+	0x2B, 0x66, 0xA0, 0xE8,
+	0x0C, 0x47, 0xA0, 0xE8,
 
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
+	0x1C, 0x57, 0xA0, 0xE8,
+	0x2C, 0x67, 0xA0, 0xE8,
 
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x0B, 0x00,
+	0x1B, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x0C, 0x00,
+	0x1C, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x0B, 0x65,
+	0x1B, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x0C, 0x65,
+	0x1C, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x0B, 0x1B, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x0C, 0x1C, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x57, 0x80, 0x57, 0xCF,
 
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x66, 0x33, 0x66, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x67, 0x3B, 0x67, 0xCF,
 
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
+	0x0B, 0x48, 0xA0, 0xE8,
+	0x1B, 0x58, 0xA0, 0xE8,
 
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
+	0x2B, 0x68, 0xA0, 0xE8,
+	0x0C, 0x49, 0xA0, 0xE8,
 
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
+	0x1C, 0x59, 0xA0, 0xE8,
+	0x2C, 0x69, 0xA0, 0xE8,
 
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x0B, 0x00,
+	0x1B, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x0C, 0x00,
+	0x1C, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x0B, 0x65,
+	0x1B, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x0C, 0x65,
+	0x1C, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
+	0x0B, 0x1B, 0x60, 0xEC,
+	0x34, 0xD7, 0x34, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x0C, 0x1C, 0x60, 0xEC,
 
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3C, 0xD7, 0x3C, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
+	0x34, 0x80, 0x34, 0xBD,
+	0x3C, 0x80, 0x3C, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
+	0x48, 0x80, 0x48, 0xCF,
+	0x59, 0x80, 0x59, 0xCF,
 
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
+	0x68, 0x33, 0x68, 0xCF,
+	0x49, 0x3B, 0x49, 0xCF,
 
-0xB5, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xB5, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
+	0x58, 0x33, 0x58, 0xCF,
+	0x69, 0x3B, 0x69, 0xCF,
 
-0x74, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x74, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_t2gzf[] = {
 
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x8A, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
+	0x0A, 0x40, 0x50, 0xBF,
+	0x2A, 0x40, 0x60, 0xBF,
 
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
+	0x32, 0x41, 0x51, 0xBF,
+	0x3A, 0x41, 0x61, 0xBF,
 
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xD3, 0x6B,
+	0x00, 0x8A, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
+	0xAD, 0xEE, 0x23, 0x9F,
+	0x00, 0xE0,
+	0x51, 0x04,
 
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x61, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
+	0x51, 0x41, 0xE0, 0xEC,
+	0x39, 0x67, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x63, 0xA0, 0xE8,
 
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x61, 0x41, 0xE0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x7D, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
+	0x7D, 0x80, 0x15, 0xEA,
+	0x10, 0x04,
+	0x20, 0x04,
 
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x61, 0x51, 0xE0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
+	0x2A, 0x42, 0x52, 0xBF,
+	0x0F, 0x52, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
+	0x1A, 0x42, 0x62, 0xBF,
+	0x1E, 0x51, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x0E, 0x61, 0x60, 0xEA,
 
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
+	0x32, 0x40, 0x50, 0xBD,
+	0x22, 0x40, 0x60, 0xBD,
 
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
+	0x12, 0x41, 0x51, 0xBD,
+	0x3A, 0x41, 0x61, 0xBD,
 
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x0E, 0xBD,
+	0x97, 0xE2,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
+	0x35, 0x48, 0xB1, 0xE8,
+	0x3D, 0x59, 0xB1, 0xE8,
 
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x66, 0x31, 0x66, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
+	0x67, 0x39, 0x67, 0xBF,
 
-0x6E, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x6E, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x35, 0x00,
+	0x3D, 0x00,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0x8D, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
+	0x43, 0x75, 0xF8, 0xEC,
+	0x35, 0x20,
+	0x3D, 0x20,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x53, 0x53, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x0E, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
+	0x48, 0x35, 0x48, 0xBF,
+	0x58, 0x35, 0x58, 0xBF,
 
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
+	0x68, 0x35, 0x68, 0xBF,
+	0x49, 0x3D, 0x49, 0xBF,
 
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
+	0x59, 0x3D, 0x59, 0xBF,
+	0x69, 0x3D, 0x69, 0xBF,
 
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
+	0x63, 0x63, 0x2D, 0xDF,
+	0x4D, 0x7D, 0xF8, 0xEC,
 
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
+	0x59, 0xE3,
+	0x00, 0xE0,
+	0xB8, 0x38, 0x33, 0xBF,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x18, 0x3A, 0x41, 0xE9,
 
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
+	0x3F, 0x53, 0xA0, 0xE8,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x63, 0xA0, 0xE8,
 
-0x50, 0x70, 0xF8, 0xEC,
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-0x0C, 0x1C, 0x60, 0xEC,
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-0x2C, 0x80, 0x60, 0xEC,
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-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_t2gzs[] = {
 
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x8A, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
+	0x0A, 0x40, 0x50, 0xBF,
+	0x2A, 0x40, 0x60, 0xBF,
 
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
+	0x32, 0x41, 0x51, 0xBF,
+	0x3A, 0x41, 0x61, 0xBF,
 
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xD3, 0x6B,
+	0x00, 0x8A, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
+	0xAD, 0xEE, 0x23, 0x9F,
+	0x00, 0xE0,
+	0x51, 0x04,
 
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x61, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
+	0x51, 0x41, 0xE0, 0xEC,
+	0x39, 0x67, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x63, 0xA0, 0xE8,
 
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x61, 0x41, 0xE0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x85, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
+	0x85, 0x80, 0x15, 0xEA,
+	0x10, 0x04,
+	0x20, 0x04,
 
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x61, 0x51, 0xE0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
+	0x2A, 0x42, 0x52, 0xBF,
+	0x0F, 0x52, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
+	0x1A, 0x42, 0x62, 0xBF,
+	0x1E, 0x51, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x0E, 0x61, 0x60, 0xEA,
 
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
+	0x32, 0x40, 0x50, 0xBD,
+	0x22, 0x40, 0x60, 0xBD,
 
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
+	0x12, 0x41, 0x51, 0xBD,
+	0x3A, 0x41, 0x61, 0xBD,
 
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x0E, 0xBD,
+	0x97, 0xE2,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
+	0x35, 0x48, 0xB1, 0xE8,
+	0x3D, 0x59, 0xB1, 0xE8,
 
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x66, 0x31, 0x66, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
+	0x67, 0x39, 0x67, 0xBF,
 
-0x76, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x76, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x35, 0x00,
+	0x3D, 0x00,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0x8D, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
+	0x43, 0x75, 0xF8, 0xEC,
+	0x35, 0x20,
+	0x3D, 0x20,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x53, 0x53, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x0E, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
+	0x48, 0x35, 0x48, 0xBF,
+	0x58, 0x35, 0x58, 0xBF,
 
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
+	0x68, 0x35, 0x68, 0xBF,
+	0x49, 0x3D, 0x49, 0xBF,
 
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
+	0x59, 0x3D, 0x59, 0xBF,
+	0x69, 0x3D, 0x69, 0xBF,
 
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
+	0x63, 0x63, 0x2D, 0xDF,
+	0x4D, 0x7D, 0xF8, 0xEC,
 
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
+	0x59, 0xE3,
+	0x00, 0xE0,
+	0xB8, 0x38, 0x33, 0xBF,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x18, 0x3A, 0x41, 0xE9,
 
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
+	0x3F, 0x53, 0xA0, 0xE8,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x63, 0xA0, 0xE8,
 
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
+	0x50, 0x70, 0xF8, 0xEC,
+	0x2B, 0x50, 0x3C, 0xE9,
 
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x0F, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0x59, 0x78, 0xF8, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x56, 0x3F, 0x56, 0xDF,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x66, 0x3D, 0x66, 0xDF,
 
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
+	0x1D, 0x32, 0x41, 0xE9,
+	0x67, 0x3D, 0x67, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3F, 0x57, 0xDF,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x59, 0x3F, 0x59, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x69, 0x3D, 0x69, 0xDF,
 
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
+	0x48, 0x37, 0x48, 0xDF,
+	0x58, 0x3F, 0x58, 0xDF,
 
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
+	0x68, 0x3D, 0x68, 0xDF,
+	0x49, 0x37, 0x49, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x0F, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
+	0x0F, 0xCF, 0x74, 0xC2,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
+	0x0A, 0x44, 0x54, 0xB0,
+	0x02, 0x44, 0x64, 0xB0,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x34, 0x37, 0x20, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x0F, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x38, 0x0F, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
+	0x2A, 0x44, 0x54, 0xB2,
+	0x1A, 0x44, 0x64, 0xB2,
 
-0x31, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x31, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x0F, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x0F, 0xCF, 0x75, 0xC0,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
+	0x3D, 0xCF, 0x75, 0xC2,
+	0x37, 0xCF, 0x75, 0xC4,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x0F, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA6, 0x0F, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA3, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x54, 0xB4,
-0x1A, 0x44, 0x64, 0xB4,
+	0x2A, 0x44, 0x54, 0xB4,
+	0x1A, 0x44, 0x64, 0xB4,
 
-0x0A, 0x45, 0x55, 0xB0,
-0x02, 0x45, 0x65, 0xB0,
+	0x0A, 0x45, 0x55, 0xB0,
+	0x02, 0x45, 0x65, 0xB0,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0xA0, 0x37, 0x20, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x2A, 0x45, 0x55, 0xB2,
-0x1A, 0x45, 0x65, 0xB2,
+	0x2A, 0x45, 0x55, 0xB2,
+	0x1A, 0x45, 0x65, 0xB2,
 
-0x0A, 0x45, 0x55, 0xB4,
-0x02, 0x45, 0x65, 0xB4,
+	0x0A, 0x45, 0x55, 0xB4,
+	0x02, 0x45, 0x65, 0xB4,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x20,
-0x1A, 0x20,
-0x0A, 0x20,
-0x02, 0x20,
+	0x2A, 0x20,
+	0x1A, 0x20,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
+	0x2A, 0x46, 0x56, 0xBF,
+	0x1A, 0x46, 0x66, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x36, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x37, 0x39, 0x4F, 0xE9,
 
-0x30, 0x50, 0x2E, 0x9F,
-0xA7, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0xA7, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0xA8, 0x38, 0x4F, 0xE9,
 
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
+	0x0A, 0x47, 0x57, 0xBF,
+	0x02, 0x47, 0x67, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA4, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA5, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
+	0x2A, 0x43, 0x53, 0xBF,
+	0x1A, 0x43, 0x63, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0xA1, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0xA2, 0x38, 0x4F, 0xE9,
 
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
+	0x0A, 0x48, 0x58, 0xBF,
+	0x02, 0x48, 0x68, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
+	0x2A, 0x49, 0x59, 0xBF,
+	0x1A, 0x49, 0x69, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x82, 0x30, 0x57, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x83, 0x38, 0x57, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x84, 0x31, 0x5E, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x85, 0x39, 0x5E, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
+	0x87, 0x77, 0x57, 0xE9,
+	0x8B, 0x3E, 0xBF, 0xEA,
 
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
+	0x80, 0x30, 0x57, 0xE9,
+	0x81, 0x38, 0x57, 0xE9,
 
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
+	0x82, 0x31, 0x57, 0xE9,
+	0x86, 0x78, 0x57, 0xE9,
 
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
+	0x83, 0x39, 0x57, 0xE9,
+	0x87, 0x79, 0x57, 0xE9,
 
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
+	0x8A, 0x34, 0x20, 0xE9,
 
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
+	0x8B, 0x3C, 0x20, 0xE9,
+	0x37, 0x50, 0x60, 0xBD,
 
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
+	0x57, 0x0D, 0x20, 0xE9,
+	0x35, 0x51, 0x61, 0xBD,
 
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x50, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x0E, 0x77,
 
-0x24, 0x51, 0x20, 0xE9,
-0x92, 0xFF, 0x20, 0xEA,
+	0x24, 0x51, 0x20, 0xE9,
+	0x92, 0xFF, 0x20, 0xEA,
 
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x0E, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
+	0x0B, 0x46, 0xA0, 0xE8,
+	0x1B, 0x56, 0xA0, 0xE8,
 
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
+	0x2B, 0x66, 0xA0, 0xE8,
+	0x0C, 0x47, 0xA0, 0xE8,
 
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
+	0x1C, 0x57, 0xA0, 0xE8,
+	0x2C, 0x67, 0xA0, 0xE8,
 
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x0B, 0x00,
+	0x1B, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x0C, 0x00,
+	0x1C, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x0B, 0x65,
+	0x1B, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x0C, 0x65,
+	0x1C, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x0B, 0x1B, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x0C, 0x1C, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x57, 0x80, 0x57, 0xCF,
 
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x66, 0x33, 0x66, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x67, 0x3B, 0x67, 0xCF,
 
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
+	0x0B, 0x48, 0xA0, 0xE8,
+	0x1B, 0x58, 0xA0, 0xE8,
 
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
+	0x2B, 0x68, 0xA0, 0xE8,
+	0x0C, 0x49, 0xA0, 0xE8,
 
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
+	0x1C, 0x59, 0xA0, 0xE8,
+	0x2C, 0x69, 0xA0, 0xE8,
 
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x0B, 0x00,
+	0x1B, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x0C, 0x00,
+	0x1C, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x0B, 0x65,
+	0x1B, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x0C, 0x65,
+	0x1C, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
+	0x0B, 0x1B, 0x60, 0xEC,
+	0x34, 0xD7, 0x34, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x0C, 0x1C, 0x60, 0xEC,
 
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3C, 0xD7, 0x3C, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
+	0x34, 0x80, 0x34, 0xBD,
+	0x3C, 0x80, 0x3C, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
+	0x48, 0x80, 0x48, 0xCF,
+	0x59, 0x80, 0x59, 0xCF,
 
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
+	0x68, 0x33, 0x68, 0xCF,
+	0x49, 0x3B, 0x49, 0xCF,
 
-0xB2, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xB2, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
+	0x58, 0x33, 0x58, 0xCF,
+	0x69, 0x3B, 0x69, 0xCF,
 
-0x70, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x70, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_t2gzsa[] = {
 
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x8A, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
+	0x0A, 0x40, 0x50, 0xBF,
+	0x2A, 0x40, 0x60, 0xBF,
 
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
+	0x32, 0x41, 0x51, 0xBF,
+	0x3A, 0x41, 0x61, 0xBF,
 
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xD3, 0x6B,
+	0x00, 0x8A, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
+	0xAD, 0xEE, 0x23, 0x9F,
+	0x00, 0xE0,
+	0x51, 0x04,
 
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x61, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
+	0x51, 0x41, 0xE0, 0xEC,
+	0x39, 0x67, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x63, 0xA0, 0xE8,
 
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x61, 0x41, 0xE0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x8A, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
+	0x8A, 0x80, 0x15, 0xEA,
+	0x10, 0x04,
+	0x20, 0x04,
 
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x61, 0x51, 0xE0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
+	0x2A, 0x42, 0x52, 0xBF,
+	0x0F, 0x52, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
+	0x1A, 0x42, 0x62, 0xBF,
+	0x1E, 0x51, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x0E, 0x61, 0x60, 0xEA,
 
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
+	0x32, 0x40, 0x50, 0xBD,
+	0x22, 0x40, 0x60, 0xBD,
 
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
+	0x12, 0x41, 0x51, 0xBD,
+	0x3A, 0x41, 0x61, 0xBD,
 
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x0E, 0xBD,
+	0x97, 0xE2,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
+	0x35, 0x48, 0xB1, 0xE8,
+	0x3D, 0x59, 0xB1, 0xE8,
 
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x66, 0x31, 0x66, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
+	0x67, 0x39, 0x67, 0xBF,
 
-0x7B, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x7B, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x35, 0x00,
+	0x3D, 0x00,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0x8D, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
+	0x43, 0x75, 0xF8, 0xEC,
+	0x35, 0x20,
+	0x3D, 0x20,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x53, 0x53, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x0E, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
+	0x48, 0x35, 0x48, 0xBF,
+	0x58, 0x35, 0x58, 0xBF,
 
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
+	0x68, 0x35, 0x68, 0xBF,
+	0x49, 0x3D, 0x49, 0xBF,
 
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
+	0x59, 0x3D, 0x59, 0xBF,
+	0x69, 0x3D, 0x69, 0xBF,
 
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
+	0x63, 0x63, 0x2D, 0xDF,
+	0x4D, 0x7D, 0xF8, 0xEC,
 
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
+	0x59, 0xE3,
+	0x00, 0xE0,
+	0xB8, 0x38, 0x33, 0xBF,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x18, 0x3A, 0x41, 0xE9,
 
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
+	0x3F, 0x53, 0xA0, 0xE8,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x63, 0xA0, 0xE8,
 
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
+	0x50, 0x70, 0xF8, 0xEC,
+	0x2B, 0x50, 0x3C, 0xE9,
 
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x0F, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0x59, 0x78, 0xF8, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
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-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3C, 0xD7, 0x3C, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
+	0x34, 0x80, 0x34, 0xBD,
+	0x3C, 0x80, 0x3C, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
+	0x48, 0x80, 0x48, 0xCF,
+	0x59, 0x80, 0x59, 0xCF,
 
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
+	0x68, 0x33, 0x68, 0xCF,
+	0x49, 0x3B, 0x49, 0xCF,
 
-0xAD, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xAD, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
+	0x58, 0x33, 0x58, 0xCF,
+	0x69, 0x3B, 0x69, 0xCF,
 
-0x6B, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x6B, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_t2gzsaf[] = {
 
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x8A, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
+	0x0A, 0x40, 0x50, 0xBF,
+	0x2A, 0x40, 0x60, 0xBF,
 
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
+	0x32, 0x41, 0x51, 0xBF,
+	0x3A, 0x41, 0x61, 0xBF,
 
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xD3, 0x6B,
+	0x00, 0x8A, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
+	0xAD, 0xEE, 0x23, 0x9F,
+	0x00, 0xE0,
+	0x51, 0x04,
 
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x61, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
+	0x51, 0x41, 0xE0, 0xEC,
+	0x39, 0x67, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x63, 0xA0, 0xE8,
 
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x61, 0x41, 0xE0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x8E, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
+	0x8E, 0x80, 0x15, 0xEA,
+	0x10, 0x04,
+	0x20, 0x04,
 
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x61, 0x51, 0xE0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
+	0x2A, 0x42, 0x52, 0xBF,
+	0x0F, 0x52, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
+	0x1A, 0x42, 0x62, 0xBF,
+	0x1E, 0x51, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x0E, 0x61, 0x60, 0xEA,
 
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
+	0x32, 0x40, 0x50, 0xBD,
+	0x22, 0x40, 0x60, 0xBD,
 
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
+	0x12, 0x41, 0x51, 0xBD,
+	0x3A, 0x41, 0x61, 0xBD,
 
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x0E, 0xBD,
+	0x97, 0xE2,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
+	0x35, 0x48, 0xB1, 0xE8,
+	0x3D, 0x59, 0xB1, 0xE8,
 
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x66, 0x31, 0x66, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
+	0x67, 0x39, 0x67, 0xBF,
 
-0x7F, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x7F, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x35, 0x00,
+	0x3D, 0x00,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0x8D, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
+	0x43, 0x75, 0xF8, 0xEC,
+	0x35, 0x20,
+	0x3D, 0x20,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x53, 0x53, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x0E, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
+	0x48, 0x35, 0x48, 0xBF,
+	0x58, 0x35, 0x58, 0xBF,
 
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
+	0x68, 0x35, 0x68, 0xBF,
+	0x49, 0x3D, 0x49, 0xBF,
 
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
+	0x59, 0x3D, 0x59, 0xBF,
+	0x69, 0x3D, 0x69, 0xBF,
 
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
+	0x63, 0x63, 0x2D, 0xDF,
+	0x4D, 0x7D, 0xF8, 0xEC,
 
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
+	0x59, 0xE3,
+	0x00, 0xE0,
+	0xB8, 0x38, 0x33, 0xBF,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x18, 0x3A, 0x41, 0xE9,
 
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
+	0x3F, 0x53, 0xA0, 0xE8,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x63, 0xA0, 0xE8,
 
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
+	0x50, 0x70, 0xF8, 0xEC,
+	0x2B, 0x50, 0x3C, 0xE9,
 
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x0F, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
+	0x59, 0x78, 0xF8, 0xEC,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x56, 0x3F, 0x56, 0xDF,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x66, 0x3D, 0x66, 0xDF,
 
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
+	0x1D, 0x32, 0x41, 0xE9,
+	0x67, 0x3D, 0x67, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3F, 0x57, 0xDF,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x59, 0x3F, 0x59, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x69, 0x3D, 0x69, 0xDF,
 
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
+	0x48, 0x37, 0x48, 0xDF,
+	0x58, 0x3F, 0x58, 0xDF,
 
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
+	0x68, 0x3D, 0x68, 0xDF,
+	0x49, 0x37, 0x49, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x0F, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
+	0x0F, 0xCF, 0x74, 0xC2,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
+	0x0A, 0x44, 0x54, 0xB0,
+	0x02, 0x44, 0x64, 0xB0,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x34, 0x37, 0x20, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x0F, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x38, 0x0F, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
+	0x2A, 0x44, 0x54, 0xB2,
+	0x1A, 0x44, 0x64, 0xB2,
 
-0x3A, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x3A, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x0F, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x0F, 0xCF, 0x75, 0xC0,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
+	0x3D, 0xCF, 0x75, 0xC2,
+	0x37, 0xCF, 0x75, 0xC4,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x0F, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA6, 0x0F, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA3, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x54, 0xB4,
-0x1A, 0x44, 0x64, 0xB4,
+	0x2A, 0x44, 0x54, 0xB4,
+	0x1A, 0x44, 0x64, 0xB4,
 
-0x0A, 0x45, 0x55, 0xB0,
-0x02, 0x45, 0x65, 0xB0,
+	0x0A, 0x45, 0x55, 0xB0,
+	0x02, 0x45, 0x65, 0xB0,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0xA0, 0x37, 0x20, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x45, 0x55, 0xB2,
-0x1A, 0x45, 0x65, 0xB2,
+	0x2A, 0x45, 0x55, 0xB2,
+	0x1A, 0x45, 0x65, 0xB2,
 
-0x0A, 0x45, 0x55, 0xB4,
-0x02, 0x45, 0x65, 0xB4,
+	0x0A, 0x45, 0x55, 0xB4,
+	0x02, 0x45, 0x65, 0xB4,
 
-0x0F, 0xCF, 0x74, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x0F, 0xCF, 0x74, 0xC6,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0xA7, 0x30, 0x4F, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0xA7, 0x30, 0x4F, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x0F, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x9C, 0x0F, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA8, 0x38, 0x4F, 0xE9,
 
-0x2A, 0x44, 0x54, 0xB6,
-0x1A, 0x44, 0x64, 0xB6,
+	0x2A, 0x44, 0x54, 0xB6,
+	0x1A, 0x44, 0x64, 0xB6,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x36, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x37, 0x39, 0x4F, 0xE9,
 
-0x0A, 0x45, 0x55, 0xB6,
-0x02, 0x45, 0x65, 0xB6,
+	0x0A, 0x45, 0x55, 0xB6,
+	0x02, 0x45, 0x65, 0xB6,
 
-0x3D, 0xCF, 0x75, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x3D, 0xCF, 0x75, 0xC6,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
+	0x2A, 0x46, 0x56, 0xBF,
+	0x1A, 0x46, 0x66, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA4, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA5, 0x39, 0x4F, 0xE9,
 
-0x31, 0x3D, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0x31, 0x3D, 0x20, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
+	0x0A, 0x47, 0x57, 0xBF,
+	0x02, 0x47, 0x67, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0xA1, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0xA2, 0x38, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x9D, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x9E, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
+	0x2A, 0x43, 0x53, 0xBF,
+	0x1A, 0x43, 0x63, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x35, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x39, 0x38, 0x4F, 0xE9,
 
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
+	0x0A, 0x48, 0x58, 0xBF,
+	0x02, 0x48, 0x68, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
+	0x2A, 0x49, 0x59, 0xBF,
+	0x1A, 0x49, 0x69, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x82, 0x30, 0x57, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x83, 0x38, 0x57, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x84, 0x31, 0x5E, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x85, 0x39, 0x5E, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
+	0x87, 0x77, 0x57, 0xE9,
+	0x8B, 0x3E, 0xBF, 0xEA,
 
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
+	0x80, 0x30, 0x57, 0xE9,
+	0x81, 0x38, 0x57, 0xE9,
 
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
+	0x82, 0x31, 0x57, 0xE9,
+	0x86, 0x78, 0x57, 0xE9,
 
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
+	0x83, 0x39, 0x57, 0xE9,
+	0x87, 0x79, 0x57, 0xE9,
 
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
+	0x8A, 0x34, 0x20, 0xE9,
 
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
+	0x8B, 0x3C, 0x20, 0xE9,
+	0x37, 0x50, 0x60, 0xBD,
 
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
+	0x57, 0x0D, 0x20, 0xE9,
+	0x35, 0x51, 0x61, 0xBD,
 
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x50, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x0E, 0x77,
 
-0x24, 0x51, 0x20, 0xE9,
-0x89, 0xFF, 0x20, 0xEA,
+	0x24, 0x51, 0x20, 0xE9,
+	0x89, 0xFF, 0x20, 0xEA,
 
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x0E, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
+	0x0B, 0x46, 0xA0, 0xE8,
+	0x1B, 0x56, 0xA0, 0xE8,
 
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
+	0x2B, 0x66, 0xA0, 0xE8,
+	0x0C, 0x47, 0xA0, 0xE8,
 
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
+	0x1C, 0x57, 0xA0, 0xE8,
+	0x2C, 0x67, 0xA0, 0xE8,
 
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x0B, 0x00,
+	0x1B, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x0C, 0x00,
+	0x1C, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x0B, 0x65,
+	0x1B, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x0C, 0x65,
+	0x1C, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x0B, 0x1B, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x0C, 0x1C, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x57, 0x80, 0x57, 0xCF,
 
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x66, 0x33, 0x66, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x67, 0x3B, 0x67, 0xCF,
 
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
+	0x0B, 0x48, 0xA0, 0xE8,
+	0x1B, 0x58, 0xA0, 0xE8,
 
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
+	0x2B, 0x68, 0xA0, 0xE8,
+	0x0C, 0x49, 0xA0, 0xE8,
 
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
+	0x1C, 0x59, 0xA0, 0xE8,
+	0x2C, 0x69, 0xA0, 0xE8,
 
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x0B, 0x00,
+	0x1B, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x0C, 0x00,
+	0x1C, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x0B, 0x65,
+	0x1B, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x0C, 0x65,
+	0x1C, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
+	0x0B, 0x1B, 0x60, 0xEC,
+	0x34, 0xD7, 0x34, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x0C, 0x1C, 0x60, 0xEC,
 
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3C, 0xD7, 0x3C, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
+	0x34, 0x80, 0x34, 0xBD,
+	0x3C, 0x80, 0x3C, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
+	0x48, 0x80, 0x48, 0xCF,
+	0x59, 0x80, 0x59, 0xCF,
 
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
+	0x68, 0x33, 0x68, 0xCF,
+	0x49, 0x3B, 0x49, 0xCF,
 
-0xA9, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xA9, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
+	0x58, 0x33, 0x58, 0xCF,
+	0x69, 0x3B, 0x69, 0xCF,
 
-0x67, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x67, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_t2gzsf[] = {
 
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x8A, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
+	0x0A, 0x40, 0x50, 0xBF,
+	0x2A, 0x40, 0x60, 0xBF,
 
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
+	0x32, 0x41, 0x51, 0xBF,
+	0x3A, 0x41, 0x61, 0xBF,
 
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xD3, 0x6B,
+	0x00, 0x8A, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
+	0xAD, 0xEE, 0x23, 0x9F,
+	0x00, 0xE0,
+	0x51, 0x04,
 
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x61, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
+	0x51, 0x41, 0xE0, 0xEC,
+	0x39, 0x67, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x63, 0xA0, 0xE8,
 
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x61, 0x41, 0xE0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x8A, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
+	0x8A, 0x80, 0x15, 0xEA,
+	0x10, 0x04,
+	0x20, 0x04,
 
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x61, 0x51, 0xE0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
+	0x2A, 0x42, 0x52, 0xBF,
+	0x0F, 0x52, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
+	0x1A, 0x42, 0x62, 0xBF,
+	0x1E, 0x51, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x0E, 0x61, 0x60, 0xEA,
 
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
+	0x32, 0x40, 0x50, 0xBD,
+	0x22, 0x40, 0x60, 0xBD,
 
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
+	0x12, 0x41, 0x51, 0xBD,
+	0x3A, 0x41, 0x61, 0xBD,
 
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x0E, 0xBD,
+	0x97, 0xE2,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
+	0x35, 0x48, 0xB1, 0xE8,
+	0x3D, 0x59, 0xB1, 0xE8,
 
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x66, 0x31, 0x66, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
+	0x67, 0x39, 0x67, 0xBF,
 
-0x7B, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
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-0x36, 0xD7, 0x36, 0xAD,
+	0x0B, 0x1B, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x0C, 0x1C, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x57, 0x80, 0x57, 0xCF,
 
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x66, 0x33, 0x66, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x67, 0x3B, 0x67, 0xCF,
 
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
+	0x0B, 0x48, 0xA0, 0xE8,
+	0x1B, 0x58, 0xA0, 0xE8,
 
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
+	0x2B, 0x68, 0xA0, 0xE8,
+	0x0C, 0x49, 0xA0, 0xE8,
 
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
+	0x1C, 0x59, 0xA0, 0xE8,
+	0x2C, 0x69, 0xA0, 0xE8,
 
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x0B, 0x00,
+	0x1B, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x0C, 0x00,
+	0x1C, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x0B, 0x65,
+	0x1B, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x0C, 0x65,
+	0x1C, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
+	0x0B, 0x1B, 0x60, 0xEC,
+	0x34, 0xD7, 0x34, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x0C, 0x1C, 0x60, 0xEC,
 
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3C, 0xD7, 0x3C, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
+	0x0B, 0x2B, 0xDE, 0xE8,
+	0x1B, 0x80, 0xDE, 0xE8,
 
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
+	0x34, 0x80, 0x34, 0xBD,
+	0x3C, 0x80, 0x3C, 0xBD,
 
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
+	0x33, 0xD7, 0x0B, 0xBD,
+	0x3B, 0xD7, 0x1B, 0xBD,
 
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
+	0x48, 0x80, 0x48, 0xCF,
+	0x59, 0x80, 0x59, 0xCF,
 
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
+	0x68, 0x33, 0x68, 0xCF,
+	0x49, 0x3B, 0x49, 0xCF,
 
-0xAD, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xAD, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
+	0x58, 0x33, 0x58, 0xCF,
+	0x69, 0x3B, 0x69, 0xCF,
 
-0x6B, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x6B, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_tgz[] = {
 
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x88, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
+	0x22, 0x40, 0x48, 0xBF,
+	0x2A, 0x40, 0x50, 0xBF,
 
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
+	0x32, 0x41, 0x49, 0xBF,
+	0x3A, 0x41, 0x51, 0xBF,
 
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xCB, 0x6B,
+	0x00, 0x88, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x4B, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
+	0xAD, 0xEE, 0x29, 0x9F,
+	0x00, 0xE0,
+	0x49, 0x04,
 
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x51, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
+	0x49, 0x41, 0xC0, 0xEC,
+	0x39, 0x57, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x51, 0x41, 0xC0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x58, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
+	0x58, 0x80, 0x15, 0xEA,
+	0x08, 0x04,
+	0x10, 0x04,
 
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x51, 0x49, 0xC0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
+	0x2A, 0x42, 0x4A, 0xBF,
+	0x27, 0x4A, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
+	0x1A, 0x42, 0x52, 0xBF,
+	0x1E, 0x49, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x26, 0x51, 0x60, 0xEA,
 
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
+	0x32, 0x40, 0x48, 0xBD,
+	0x22, 0x40, 0x50, 0xBD,
 
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
+	0x12, 0x41, 0x49, 0xBD,
+	0x3A, 0x41, 0x51, 0xBD,
 
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x26, 0xBD,
+	0x00, 0xE0,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x4E, 0x31, 0x4E, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
+	0x4F, 0x39, 0x4F, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
 
-0x4A, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x4A, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x42, 0x73, 0xF8, 0xEC,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0xA5, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x4B, 0x4B, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x26, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
+	0x53, 0x53, 0x2D, 0xDF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
+	0xB8, 0x38, 0x33, 0xBF,
+	0x00, 0xE0,
+	0x59, 0xE3,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x3F, 0x4B, 0xA0, 0xE8,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x53, 0xA0, 0xE8,
 
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
+	0x48, 0x70, 0xF8, 0xEC,
+	0x2B, 0x48, 0x3C, 0xE9,
 
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x27, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
+	0x18, 0x3A, 0x41, 0xE9,
+	0x1D, 0x32, 0x41, 0xE9,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x56, 0x3D, 0x56, 0xDF,
 
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x4E, 0x3F, 0x4E, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x4F, 0x3F, 0x4F, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3D, 0x57, 0xDF,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x80, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x34, 0x80, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
+	0x0A, 0x44, 0x4C, 0xB0,
+	0x02, 0x44, 0x54, 0xB0,
 
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
+	0x2A, 0x44, 0x4C, 0xB2,
+	0x1A, 0x44, 0x54, 0xB2,
 
-0x1D, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x1D, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x3D, 0xCF, 0x74, 0xC2,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x3D, 0xCF, 0x74, 0xC2,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x2A, 0x44, 0x4C, 0xB4,
-0x1A, 0x44, 0x54, 0xB4,
+	0x2A, 0x44, 0x4C, 0xB4,
+	0x1A, 0x44, 0x54, 0xB4,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x38, 0x3D, 0x20, 0xE9,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
+	0x2A, 0x46, 0x4E, 0xBF,
+	0x1A, 0x46, 0x56, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
+	0x0A, 0x47, 0x4F, 0xBF,
+	0x02, 0x47, 0x57, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
+	0x2A, 0x43, 0x4B, 0xBF,
+	0x1A, 0x43, 0x53, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x36, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x37, 0x39, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
+	0x37, 0x48, 0x50, 0xBD,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8B, 0x3E, 0x20, 0xE9,
 
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
+	0x82, 0x30, 0x57, 0xE9,
+	0x87, 0x77, 0x57, 0xE9,
 
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
+	0x83, 0x38, 0x57, 0xE9,
+	0x35, 0x49, 0x51, 0xBD,
 
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
+	0x84, 0x31, 0x5E, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
 
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
+	0x85, 0x39, 0x5E, 0xE9,
+	0x57, 0x25, 0x20, 0xE9,
 
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x48, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x26, 0x77,
 
-0x24, 0x49, 0x20, 0xE9,
-0xAF, 0xFF, 0x20, 0xEA,
+	0x24, 0x49, 0x20, 0xE9,
+	0xAF, 0xFF, 0x20, 0xEA,
 
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x26, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
+	0x1C, 0x46, 0xA0, 0xE8,
+	0x23, 0x4E, 0xA0, 0xE8,
 
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
+	0x2B, 0x56, 0xA0, 0xE8,
+	0x1D, 0x47, 0xA0, 0xE8,
 
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
+	0x24, 0x4F, 0xA0, 0xE8,
+	0x2C, 0x57, 0xA0, 0xE8,
 
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x1C, 0x00,
+	0x23, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x1D, 0x00,
+	0x24, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x1C, 0x65,
+	0x23, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x1D, 0x65,
+	0x24, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x1C, 0x23, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x1D, 0x24, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
+	0x1C, 0x2B, 0xDE, 0xE8,
+	0x23, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
+	0x33, 0xD7, 0x1C, 0xBD,
+	0x3B, 0xD7, 0x23, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x4F, 0x80, 0x4F, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0xD6, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xD6, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
+	0x4E, 0x33, 0x4E, 0xCF,
+	0x57, 0x3B, 0x57, 0xCF,
 
-0x9D, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x9D, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_tgza[] = {
 
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x88, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
+	0x22, 0x40, 0x48, 0xBF,
+	0x2A, 0x40, 0x50, 0xBF,
 
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
+	0x32, 0x41, 0x49, 0xBF,
+	0x3A, 0x41, 0x51, 0xBF,
 
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xCB, 0x6B,
+	0x00, 0x88, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x4B, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
+	0xAD, 0xEE, 0x29, 0x9F,
+	0x00, 0xE0,
+	0x49, 0x04,
 
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x51, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
+	0x49, 0x41, 0xC0, 0xEC,
+	0x39, 0x57, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x51, 0x41, 0xC0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x5C, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
+	0x5C, 0x80, 0x15, 0xEA,
+	0x08, 0x04,
+	0x10, 0x04,
 
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x51, 0x49, 0xC0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
+	0x2A, 0x42, 0x4A, 0xBF,
+	0x27, 0x4A, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
+	0x1A, 0x42, 0x52, 0xBF,
+	0x1E, 0x49, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x26, 0x51, 0x60, 0xEA,
 
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
+	0x32, 0x40, 0x48, 0xBD,
+	0x22, 0x40, 0x50, 0xBD,
 
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
+	0x12, 0x41, 0x49, 0xBD,
+	0x3A, 0x41, 0x51, 0xBD,
 
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x26, 0xBD,
+	0x00, 0xE0,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x4E, 0x31, 0x4E, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
+	0x4F, 0x39, 0x4F, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
 
-0x4E, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x4E, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x42, 0x73, 0xF8, 0xEC,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0xA5, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x4B, 0x4B, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x26, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
+	0x53, 0x53, 0x2D, 0xDF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
+	0xB8, 0x38, 0x33, 0xBF,
+	0x00, 0xE0,
+	0x59, 0xE3,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x3F, 0x4B, 0xA0, 0xE8,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x53, 0xA0, 0xE8,
 
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
+	0x48, 0x70, 0xF8, 0xEC,
+	0x2B, 0x48, 0x3C, 0xE9,
 
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x27, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
+	0x18, 0x3A, 0x41, 0xE9,
+	0x1D, 0x32, 0x41, 0xE9,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x56, 0x3D, 0x56, 0xDF,
 
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x4E, 0x3F, 0x4E, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x4F, 0x3F, 0x4F, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3D, 0x57, 0xDF,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x80, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x34, 0x80, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x27, 0xCF, 0x74, 0xC6,
-0x3D, 0xCF, 0x74, 0xC2,
+	0x27, 0xCF, 0x74, 0xC6,
+	0x3D, 0xCF, 0x74, 0xC2,
 
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
+	0x0A, 0x44, 0x4C, 0xB0,
+	0x02, 0x44, 0x54, 0xB0,
 
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
+	0x2A, 0x44, 0x4C, 0xB2,
+	0x1A, 0x44, 0x54, 0xB2,
 
-0x20, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x20, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x9C, 0x27, 0x20, 0xE9,
 
-0x0A, 0x44, 0x4C, 0xB4,
-0x02, 0x44, 0x54, 0xB4,
+	0x0A, 0x44, 0x4C, 0xB4,
+	0x02, 0x44, 0x54, 0xB4,
 
-0x2A, 0x44, 0x4C, 0xB6,
-0x1A, 0x44, 0x54, 0xB6,
+	0x2A, 0x44, 0x4C, 0xB6,
+	0x1A, 0x44, 0x54, 0xB6,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x38, 0x3D, 0x20, 0xE9,
 
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x0A, 0x20,
+	0x02, 0x20,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
+	0x0A, 0x47, 0x4F, 0xBF,
+	0x02, 0x47, 0x57, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
+	0x2A, 0x46, 0x4E, 0xBF,
+	0x1A, 0x46, 0x56, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x36, 0x30, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x36, 0x30, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x37, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x37, 0x38, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
+	0x2A, 0x43, 0x4B, 0xBF,
+	0x1A, 0x43, 0x53, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x9D, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x9E, 0x39, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
+	0x37, 0x48, 0x50, 0xBD,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8B, 0x3E, 0x20, 0xE9,
 
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
+	0x82, 0x30, 0x57, 0xE9,
+	0x87, 0x77, 0x57, 0xE9,
 
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
+	0x83, 0x38, 0x57, 0xE9,
+	0x35, 0x49, 0x51, 0xBD,
 
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
+	0x84, 0x31, 0x5E, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
 
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
+	0x85, 0x39, 0x5E, 0xE9,
+	0x57, 0x25, 0x20, 0xE9,
 
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x48, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x26, 0x77,
 
-0x24, 0x49, 0x20, 0xE9,
-0xAB, 0xFF, 0x20, 0xEA,
+	0x24, 0x49, 0x20, 0xE9,
+	0xAB, 0xFF, 0x20, 0xEA,
 
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x26, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
+	0x1C, 0x46, 0xA0, 0xE8,
+	0x23, 0x4E, 0xA0, 0xE8,
 
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
+	0x2B, 0x56, 0xA0, 0xE8,
+	0x1D, 0x47, 0xA0, 0xE8,
 
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
+	0x24, 0x4F, 0xA0, 0xE8,
+	0x2C, 0x57, 0xA0, 0xE8,
 
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x1C, 0x00,
+	0x23, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x1D, 0x00,
+	0x24, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x1C, 0x65,
+	0x23, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x1D, 0x65,
+	0x24, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x1C, 0x23, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x1D, 0x24, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
+	0x1C, 0x2B, 0xDE, 0xE8,
+	0x23, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
+	0x33, 0xD7, 0x1C, 0xBD,
+	0x3B, 0xD7, 0x23, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x4F, 0x80, 0x4F, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0xD3, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xD3, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
+	0x4E, 0x33, 0x4E, 0xCF,
+	0x57, 0x3B, 0x57, 0xCF,
 
-0x99, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x99, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_tgzaf[] = {
 
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x88, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
+	0x22, 0x40, 0x48, 0xBF,
+	0x2A, 0x40, 0x50, 0xBF,
 
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
+	0x32, 0x41, 0x49, 0xBF,
+	0x3A, 0x41, 0x51, 0xBF,
 
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xCB, 0x6B,
+	0x00, 0x88, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x4B, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
+	0xAD, 0xEE, 0x29, 0x9F,
+	0x00, 0xE0,
+	0x49, 0x04,
 
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x51, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
+	0x49, 0x41, 0xC0, 0xEC,
+	0x39, 0x57, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x51, 0x41, 0xC0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x61, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
+	0x61, 0x80, 0x15, 0xEA,
+	0x08, 0x04,
+	0x10, 0x04,
 
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x51, 0x49, 0xC0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
+	0x2A, 0x42, 0x4A, 0xBF,
+	0x27, 0x4A, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
+	0x1A, 0x42, 0x52, 0xBF,
+	0x1E, 0x49, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x26, 0x51, 0x60, 0xEA,
 
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
+	0x32, 0x40, 0x48, 0xBD,
+	0x22, 0x40, 0x50, 0xBD,
 
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
+	0x12, 0x41, 0x49, 0xBD,
+	0x3A, 0x41, 0x51, 0xBD,
 
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x26, 0xBD,
+	0x00, 0xE0,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x4E, 0x31, 0x4E, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
+	0x4F, 0x39, 0x4F, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
 
-0x53, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x53, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x42, 0x73, 0xF8, 0xEC,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0xA5, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x4B, 0x4B, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x26, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
+	0x53, 0x53, 0x2D, 0xDF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
+	0xB8, 0x38, 0x33, 0xBF,
+	0x00, 0xE0,
+	0x59, 0xE3,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x3F, 0x4B, 0xA0, 0xE8,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x53, 0xA0, 0xE8,
 
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
+	0x48, 0x70, 0xF8, 0xEC,
+	0x2B, 0x48, 0x3C, 0xE9,
 
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x27, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
+	0x18, 0x3A, 0x41, 0xE9,
+	0x1D, 0x32, 0x41, 0xE9,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x56, 0x3D, 0x56, 0xDF,
 
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x4E, 0x3F, 0x4E, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x4F, 0x3F, 0x4F, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3D, 0x57, 0xDF,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
+	0x0A, 0x44, 0x4C, 0xB0,
+	0x02, 0x44, 0x54, 0xB0,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x37, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x34, 0x37, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
+	0x2A, 0x44, 0x4C, 0xB2,
+	0x1A, 0x44, 0x54, 0xB2,
 
-0x26, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x26, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x3D, 0xCF, 0x74, 0xC2,
-0x27, 0xCF, 0x74, 0xC6,
+	0x3D, 0xCF, 0x74, 0xC2,
+	0x27, 0xCF, 0x74, 0xC6,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x9C, 0x27, 0x20, 0xE9,
 
-0x0A, 0x44, 0x4C, 0xB4,
-0x02, 0x44, 0x54, 0xB4,
+	0x0A, 0x44, 0x4C, 0xB4,
+	0x02, 0x44, 0x54, 0xB4,
 
-0x2A, 0x44, 0x4C, 0xB6,
-0x1A, 0x44, 0x54, 0xB6,
+	0x2A, 0x44, 0x4C, 0xB6,
+	0x1A, 0x44, 0x54, 0xB6,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x38, 0x3D, 0x20, 0xE9,
 
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x0A, 0x20,
+	0x02, 0x20,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x3D, 0xCF, 0x75, 0xC6,
-0x00, 0x80, 0x00, 0xE8,
+	0x3D, 0xCF, 0x75, 0xC6,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x0A, 0x45, 0x4D, 0xB6,
-0x02, 0x45, 0x55, 0xB6,
+	0x0A, 0x45, 0x4D, 0xB6,
+	0x02, 0x45, 0x55, 0xB6,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x31, 0x3D, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0x31, 0x3D, 0x20, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
+	0x2A, 0x46, 0x4E, 0xBF,
+	0x1A, 0x46, 0x56, 0xBF,
 
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
+	0x0A, 0x47, 0x4F, 0xBF,
+	0x02, 0x47, 0x57, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x36, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x37, 0x38, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x9D, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x9E, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
+	0x2A, 0x43, 0x4B, 0xBF,
+	0x1A, 0x43, 0x53, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x35, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x39, 0x38, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
+	0x37, 0x48, 0x50, 0xBD,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8B, 0x3E, 0x20, 0xE9,
 
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
+	0x82, 0x30, 0x57, 0xE9,
+	0x87, 0x77, 0x57, 0xE9,
 
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
+	0x83, 0x38, 0x57, 0xE9,
+	0x35, 0x49, 0x51, 0xBD,
 
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
+	0x84, 0x31, 0x5E, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
 
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
+	0x85, 0x39, 0x5E, 0xE9,
+	0x57, 0x25, 0x20, 0xE9,
 
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x48, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x26, 0x77,
 
-0x24, 0x49, 0x20, 0xE9,
-0xA6, 0xFF, 0x20, 0xEA,
+	0x24, 0x49, 0x20, 0xE9,
+	0xA6, 0xFF, 0x20, 0xEA,
 
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x26, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
+	0x1C, 0x46, 0xA0, 0xE8,
+	0x23, 0x4E, 0xA0, 0xE8,
 
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
+	0x2B, 0x56, 0xA0, 0xE8,
+	0x1D, 0x47, 0xA0, 0xE8,
 
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
+	0x24, 0x4F, 0xA0, 0xE8,
+	0x2C, 0x57, 0xA0, 0xE8,
 
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x1C, 0x00,
+	0x23, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x1D, 0x00,
+	0x24, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x1C, 0x65,
+	0x23, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x1D, 0x65,
+	0x24, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x1C, 0x23, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x1D, 0x24, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
+	0x1C, 0x2B, 0xDE, 0xE8,
+	0x23, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
+	0x33, 0xD7, 0x1C, 0xBD,
+	0x3B, 0xD7, 0x23, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x4F, 0x80, 0x4F, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0xCD, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xCD, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
+	0x4E, 0x33, 0x4E, 0xCF,
+	0x57, 0x3B, 0x57, 0xCF,
 
-0x94, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x94, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_tgzf[] = {
 
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x88, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
+	0x22, 0x40, 0x48, 0xBF,
+	0x2A, 0x40, 0x50, 0xBF,
 
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
+	0x32, 0x41, 0x49, 0xBF,
+	0x3A, 0x41, 0x51, 0xBF,
 
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xCB, 0x6B,
+	0x00, 0x88, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x4B, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
+	0xAD, 0xEE, 0x29, 0x9F,
+	0x00, 0xE0,
+	0x49, 0x04,
 
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x51, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
+	0x49, 0x41, 0xC0, 0xEC,
+	0x39, 0x57, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x51, 0x41, 0xC0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x5D, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
+	0x5D, 0x80, 0x15, 0xEA,
+	0x08, 0x04,
+	0x10, 0x04,
 
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x51, 0x49, 0xC0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
+	0x2A, 0x42, 0x4A, 0xBF,
+	0x27, 0x4A, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
+	0x1A, 0x42, 0x52, 0xBF,
+	0x1E, 0x49, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x26, 0x51, 0x60, 0xEA,
 
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
+	0x32, 0x40, 0x48, 0xBD,
+	0x22, 0x40, 0x50, 0xBD,
 
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
+	0x12, 0x41, 0x49, 0xBD,
+	0x3A, 0x41, 0x51, 0xBD,
 
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x26, 0xBD,
+	0x00, 0xE0,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x4E, 0x31, 0x4E, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
+	0x4F, 0x39, 0x4F, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
 
-0x4F, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x4F, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x42, 0x73, 0xF8, 0xEC,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0xA5, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x4B, 0x4B, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x26, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
+	0x53, 0x53, 0x2D, 0xDF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
+	0xB8, 0x38, 0x33, 0xBF,
+	0x00, 0xE0,
+	0x59, 0xE3,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x3F, 0x4B, 0xA0, 0xE8,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x53, 0xA0, 0xE8,
 
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
+	0x48, 0x70, 0xF8, 0xEC,
+	0x2B, 0x48, 0x3C, 0xE9,
 
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x27, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
+	0x18, 0x3A, 0x41, 0xE9,
+	0x1D, 0x32, 0x41, 0xE9,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x56, 0x3D, 0x56, 0xDF,
 
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x4E, 0x3F, 0x4E, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x4F, 0x3F, 0x4F, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3D, 0x57, 0xDF,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x34, 0x80, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x34, 0x80, 0x20, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x27, 0xCF, 0x75, 0xC6,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x27, 0xCF, 0x75, 0xC6,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
+	0x0A, 0x44, 0x4C, 0xB0,
+	0x02, 0x44, 0x54, 0xB0,
 
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
+	0x2A, 0x44, 0x4C, 0xB2,
+	0x1A, 0x44, 0x54, 0xB2,
 
-0x20, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x20, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x3D, 0xCF, 0x74, 0xC2,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x3D, 0xCF, 0x74, 0xC2,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x31, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x31, 0x27, 0x20, 0xE9,
 
-0x0A, 0x44, 0x4C, 0xB4,
-0x02, 0x44, 0x54, 0xB4,
+	0x0A, 0x44, 0x4C, 0xB4,
+	0x02, 0x44, 0x54, 0xB4,
 
-0x2A, 0x45, 0x4D, 0xB6,
-0x1A, 0x45, 0x55, 0xB6,
+	0x2A, 0x45, 0x4D, 0xB6,
+	0x1A, 0x45, 0x55, 0xB6,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x38, 0x3D, 0x20, 0xE9,
 
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x0A, 0x20,
+	0x02, 0x20,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
+	0x0A, 0x47, 0x4F, 0xBF,
+	0x02, 0x47, 0x57, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
+	0x2A, 0x46, 0x4E, 0xBF,
+	0x1A, 0x46, 0x56, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x36, 0x30, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x36, 0x30, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x37, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x37, 0x38, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
+	0x2A, 0x43, 0x4B, 0xBF,
+	0x1A, 0x43, 0x53, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x35, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x39, 0x39, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
+	0x37, 0x48, 0x50, 0xBD,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8B, 0x3E, 0x20, 0xE9,
 
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
+	0x82, 0x30, 0x57, 0xE9,
+	0x87, 0x77, 0x57, 0xE9,
 
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
+	0x83, 0x38, 0x57, 0xE9,
+	0x35, 0x49, 0x51, 0xBD,
 
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
+	0x84, 0x31, 0x5E, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
 
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
+	0x85, 0x39, 0x5E, 0xE9,
+	0x57, 0x25, 0x20, 0xE9,
 
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x48, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x26, 0x77,
 
-0x24, 0x49, 0x20, 0xE9,
-0xAA, 0xFF, 0x20, 0xEA,
+	0x24, 0x49, 0x20, 0xE9,
+	0xAA, 0xFF, 0x20, 0xEA,
 
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x26, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
+	0x1C, 0x46, 0xA0, 0xE8,
+	0x23, 0x4E, 0xA0, 0xE8,
 
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
+	0x2B, 0x56, 0xA0, 0xE8,
+	0x1D, 0x47, 0xA0, 0xE8,
 
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
+	0x24, 0x4F, 0xA0, 0xE8,
+	0x2C, 0x57, 0xA0, 0xE8,
 
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x1C, 0x00,
+	0x23, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x1D, 0x00,
+	0x24, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x1C, 0x65,
+	0x23, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x1D, 0x65,
+	0x24, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x1C, 0x23, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x1D, 0x24, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
+	0x1C, 0x2B, 0xDE, 0xE8,
+	0x23, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
+	0x33, 0xD7, 0x1C, 0xBD,
+	0x3B, 0xD7, 0x23, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x4F, 0x80, 0x4F, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0xD3, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xD3, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
+	0x4E, 0x33, 0x4E, 0xCF,
+	0x57, 0x3B, 0x57, 0xCF,
 
-0x98, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x98, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_tgzs[] = {
 
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x88, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
+	0x22, 0x40, 0x48, 0xBF,
+	0x2A, 0x40, 0x50, 0xBF,
 
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
+	0x32, 0x41, 0x49, 0xBF,
+	0x3A, 0x41, 0x51, 0xBF,
 
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xCB, 0x6B,
+	0x00, 0x88, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x4B, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
+	0xAD, 0xEE, 0x29, 0x9F,
+	0x00, 0xE0,
+	0x49, 0x04,
 
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x51, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
+	0x49, 0x41, 0xC0, 0xEC,
+	0x39, 0x57, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x51, 0x41, 0xC0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x65, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
+	0x65, 0x80, 0x15, 0xEA,
+	0x08, 0x04,
+	0x10, 0x04,
 
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x51, 0x49, 0xC0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
+	0x2A, 0x42, 0x4A, 0xBF,
+	0x27, 0x4A, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
+	0x1A, 0x42, 0x52, 0xBF,
+	0x1E, 0x49, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x26, 0x51, 0x60, 0xEA,
 
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
+	0x32, 0x40, 0x48, 0xBD,
+	0x22, 0x40, 0x50, 0xBD,
 
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
+	0x12, 0x41, 0x49, 0xBD,
+	0x3A, 0x41, 0x51, 0xBD,
 
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x26, 0xBD,
+	0x00, 0xE0,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x4E, 0x31, 0x4E, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
+	0x4F, 0x39, 0x4F, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
 
-0x57, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x57, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x42, 0x73, 0xF8, 0xEC,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0xA5, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x4B, 0x4B, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x26, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
+	0x53, 0x53, 0x2D, 0xDF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
+	0xB8, 0x38, 0x33, 0xBF,
+	0x00, 0xE0,
+	0x59, 0xE3,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x3F, 0x4B, 0xA0, 0xE8,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x53, 0xA0, 0xE8,
 
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
+	0x48, 0x70, 0xF8, 0xEC,
+	0x2B, 0x48, 0x3C, 0xE9,
 
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x27, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
+	0x18, 0x3A, 0x41, 0xE9,
+	0x1D, 0x32, 0x41, 0xE9,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x56, 0x3D, 0x56, 0xDF,
 
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x4E, 0x3F, 0x4E, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x4F, 0x3F, 0x4F, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3D, 0x57, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x27, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
+	0x27, 0xCF, 0x74, 0xC2,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
+	0x0A, 0x44, 0x4C, 0xB0,
+	0x02, 0x44, 0x54, 0xB0,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x34, 0x37, 0x20, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x38, 0x27, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
+	0x2A, 0x44, 0x4C, 0xB2,
+	0x1A, 0x44, 0x54, 0xB2,
 
-0x29, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x29, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x27, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x27, 0xCF, 0x75, 0xC0,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
+	0x3D, 0xCF, 0x75, 0xC2,
+	0x37, 0xCF, 0x75, 0xC4,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA6, 0x27, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA3, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x4C, 0xB4,
-0x1A, 0x44, 0x54, 0xB4,
+	0x2A, 0x44, 0x4C, 0xB4,
+	0x1A, 0x44, 0x54, 0xB4,
 
-0x0A, 0x45, 0x4D, 0xB0,
-0x02, 0x45, 0x55, 0xB0,
+	0x0A, 0x45, 0x4D, 0xB0,
+	0x02, 0x45, 0x55, 0xB0,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0xA0, 0x37, 0x20, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x2A, 0x45, 0x4D, 0xB2,
-0x1A, 0x45, 0x55, 0xB2,
+	0x2A, 0x45, 0x4D, 0xB2,
+	0x1A, 0x45, 0x55, 0xB2,
 
-0x0A, 0x45, 0x4D, 0xB4,
-0x02, 0x45, 0x55, 0xB4,
+	0x0A, 0x45, 0x4D, 0xB4,
+	0x02, 0x45, 0x55, 0xB4,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x0A, 0x20,
+	0x02, 0x20,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
+	0x2A, 0x46, 0x4E, 0xBF,
+	0x1A, 0x46, 0x56, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x36, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x37, 0x39, 0x4F, 0xE9,
 
-0x30, 0x50, 0x2E, 0x9F,
-0xA7, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0xA7, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0xA8, 0x38, 0x4F, 0xE9,
 
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
+	0x0A, 0x47, 0x4F, 0xBF,
+	0x02, 0x47, 0x57, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA4, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA5, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
+	0x2A, 0x43, 0x4B, 0xBF,
+	0x1A, 0x43, 0x53, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0xA1, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0xA2, 0x38, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
+	0x37, 0x48, 0x50, 0xBD,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8B, 0x3E, 0x20, 0xE9,
 
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
+	0x82, 0x30, 0x57, 0xE9,
+	0x87, 0x77, 0x57, 0xE9,
 
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
+	0x83, 0x38, 0x57, 0xE9,
+	0x35, 0x49, 0x51, 0xBD,
 
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
+	0x84, 0x31, 0x5E, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
 
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
+	0x85, 0x39, 0x5E, 0xE9,
+	0x57, 0x25, 0x20, 0xE9,
 
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x48, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x26, 0x77,
 
-0x24, 0x49, 0x20, 0xE9,
-0xA2, 0xFF, 0x20, 0xEA,
+	0x24, 0x49, 0x20, 0xE9,
+	0xA2, 0xFF, 0x20, 0xEA,
 
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x26, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
+	0x1C, 0x46, 0xA0, 0xE8,
+	0x23, 0x4E, 0xA0, 0xE8,
 
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
+	0x2B, 0x56, 0xA0, 0xE8,
+	0x1D, 0x47, 0xA0, 0xE8,
 
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
+	0x24, 0x4F, 0xA0, 0xE8,
+	0x2C, 0x57, 0xA0, 0xE8,
 
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x1C, 0x00,
+	0x23, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x1D, 0x00,
+	0x24, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x1C, 0x65,
+	0x23, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x1D, 0x65,
+	0x24, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x1C, 0x23, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x1D, 0x24, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
+	0x1C, 0x2B, 0xDE, 0xE8,
+	0x23, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
+	0x33, 0xD7, 0x1C, 0xBD,
+	0x3B, 0xD7, 0x23, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x4F, 0x80, 0x4F, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0xCA, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xCA, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
+	0x4E, 0x33, 0x4E, 0xCF,
+	0x57, 0x3B, 0x57, 0xCF,
 
-0x90, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x90, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_tgzsa[] = {
 
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x88, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
+	0x22, 0x40, 0x48, 0xBF,
+	0x2A, 0x40, 0x50, 0xBF,
 
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
+	0x32, 0x41, 0x49, 0xBF,
+	0x3A, 0x41, 0x51, 0xBF,
 
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xCB, 0x6B,
+	0x00, 0x88, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x4B, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
+	0xAD, 0xEE, 0x29, 0x9F,
+	0x00, 0xE0,
+	0x49, 0x04,
 
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x51, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
+	0x49, 0x41, 0xC0, 0xEC,
+	0x39, 0x57, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x53, 0xA0, 0xE8,
 
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+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x1C, 0x23, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x1D, 0x24, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
+	0x1C, 0x2B, 0xDE, 0xE8,
+	0x23, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
+	0x33, 0xD7, 0x1C, 0xBD,
+	0x3B, 0xD7, 0x23, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x4F, 0x80, 0x4F, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0xC5, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xC5, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
+	0x4E, 0x33, 0x4E, 0xCF,
+	0x57, 0x3B, 0x57, 0xCF,
 
-0x8B, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x8B, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_tgzsaf[] = {
 
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x88, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
+	0x22, 0x40, 0x48, 0xBF,
+	0x2A, 0x40, 0x50, 0xBF,
 
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
+	0x32, 0x41, 0x49, 0xBF,
+	0x3A, 0x41, 0x51, 0xBF,
 
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xCB, 0x6B,
+	0x00, 0x88, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x4B, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
+	0xAD, 0xEE, 0x29, 0x9F,
+	0x00, 0xE0,
+	0x49, 0x04,
 
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x51, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
+	0x49, 0x41, 0xC0, 0xEC,
+	0x39, 0x57, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x51, 0x41, 0xC0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x6E, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
+	0x6E, 0x80, 0x15, 0xEA,
+	0x08, 0x04,
+	0x10, 0x04,
 
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x51, 0x49, 0xC0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
+	0x2A, 0x42, 0x4A, 0xBF,
+	0x27, 0x4A, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
+	0x1A, 0x42, 0x52, 0xBF,
+	0x1E, 0x49, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x26, 0x51, 0x60, 0xEA,
 
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
+	0x32, 0x40, 0x48, 0xBD,
+	0x22, 0x40, 0x50, 0xBD,
 
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
+	0x12, 0x41, 0x49, 0xBD,
+	0x3A, 0x41, 0x51, 0xBD,
 
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x26, 0xBD,
+	0x00, 0xE0,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x4E, 0x31, 0x4E, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
+	0x4F, 0x39, 0x4F, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
 
-0x60, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x60, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x42, 0x73, 0xF8, 0xEC,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0xA5, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x4B, 0x4B, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x26, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
+	0x53, 0x53, 0x2D, 0xDF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
+	0xB8, 0x38, 0x33, 0xBF,
+	0x00, 0xE0,
+	0x59, 0xE3,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x3F, 0x4B, 0xA0, 0xE8,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x53, 0xA0, 0xE8,
 
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
+	0x48, 0x70, 0xF8, 0xEC,
+	0x2B, 0x48, 0x3C, 0xE9,
 
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x27, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
+	0x18, 0x3A, 0x41, 0xE9,
+	0x1D, 0x32, 0x41, 0xE9,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x56, 0x3D, 0x56, 0xDF,
 
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x4E, 0x3F, 0x4E, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x4F, 0x3F, 0x4F, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3D, 0x57, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x27, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
+	0x27, 0xCF, 0x74, 0xC2,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
+	0x0A, 0x44, 0x4C, 0xB0,
+	0x02, 0x44, 0x54, 0xB0,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x34, 0x37, 0x20, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x38, 0x27, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
+	0x2A, 0x44, 0x4C, 0xB2,
+	0x1A, 0x44, 0x54, 0xB2,
 
-0x32, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x32, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x27, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x27, 0xCF, 0x75, 0xC0,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
+	0x3D, 0xCF, 0x75, 0xC2,
+	0x37, 0xCF, 0x75, 0xC4,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA6, 0x27, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA3, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x4C, 0xB4,
-0x1A, 0x44, 0x54, 0xB4,
+	0x2A, 0x44, 0x4C, 0xB4,
+	0x1A, 0x44, 0x54, 0xB4,
 
-0x0A, 0x45, 0x4D, 0xB0,
-0x02, 0x45, 0x55, 0xB0,
+	0x0A, 0x45, 0x4D, 0xB0,
+	0x02, 0x45, 0x55, 0xB0,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0xA0, 0x37, 0x20, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x45, 0x4D, 0xB2,
-0x1A, 0x45, 0x55, 0xB2,
+	0x2A, 0x45, 0x4D, 0xB2,
+	0x1A, 0x45, 0x55, 0xB2,
 
-0x0A, 0x45, 0x4D, 0xB4,
-0x02, 0x45, 0x55, 0xB4,
+	0x0A, 0x45, 0x4D, 0xB4,
+	0x02, 0x45, 0x55, 0xB4,
 
-0x27, 0xCF, 0x74, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x27, 0xCF, 0x74, 0xC6,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0xA7, 0x30, 0x4F, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0xA7, 0x30, 0x4F, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x9C, 0x27, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA8, 0x38, 0x4F, 0xE9,
 
-0x2A, 0x44, 0x4C, 0xB6,
-0x1A, 0x44, 0x54, 0xB6,
+	0x2A, 0x44, 0x4C, 0xB6,
+	0x1A, 0x44, 0x54, 0xB6,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x36, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x37, 0x39, 0x4F, 0xE9,
 
-0x0A, 0x45, 0x4D, 0xB6,
-0x02, 0x45, 0x55, 0xB6,
+	0x0A, 0x45, 0x4D, 0xB6,
+	0x02, 0x45, 0x55, 0xB6,
 
-0x3D, 0xCF, 0x75, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x3D, 0xCF, 0x75, 0xC6,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
+	0x2A, 0x46, 0x4E, 0xBF,
+	0x1A, 0x46, 0x56, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA4, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA5, 0x39, 0x4F, 0xE9,
 
-0x31, 0x3D, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0x31, 0x3D, 0x20, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
+	0x0A, 0x47, 0x4F, 0xBF,
+	0x02, 0x47, 0x57, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0xA1, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0xA2, 0x38, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x9D, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x9E, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
+	0x2A, 0x43, 0x4B, 0xBF,
+	0x1A, 0x43, 0x53, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x30, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x35, 0x30, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x38, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x39, 0x38, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
+	0x37, 0x48, 0x50, 0xBD,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8B, 0x3E, 0x20, 0xE9,
 
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
+	0x82, 0x30, 0x57, 0xE9,
+	0x87, 0x77, 0x57, 0xE9,
 
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
+	0x83, 0x38, 0x57, 0xE9,
+	0x35, 0x49, 0x51, 0xBD,
 
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
+	0x84, 0x31, 0x5E, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
 
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
+	0x85, 0x39, 0x5E, 0xE9,
+	0x57, 0x25, 0x20, 0xE9,
 
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x48, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x26, 0x77,
 
-0x24, 0x49, 0x20, 0xE9,
-0x99, 0xFF, 0x20, 0xEA,
+	0x24, 0x49, 0x20, 0xE9,
+	0x99, 0xFF, 0x20, 0xEA,
 
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x26, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
+	0x1C, 0x46, 0xA0, 0xE8,
+	0x23, 0x4E, 0xA0, 0xE8,
 
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
+	0x2B, 0x56, 0xA0, 0xE8,
+	0x1D, 0x47, 0xA0, 0xE8,
 
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
+	0x24, 0x4F, 0xA0, 0xE8,
+	0x2C, 0x57, 0xA0, 0xE8,
 
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x1C, 0x00,
+	0x23, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x1D, 0x00,
+	0x24, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x1C, 0x65,
+	0x23, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x1D, 0x65,
+	0x24, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x1C, 0x23, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x1D, 0x24, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
+	0x1C, 0x2B, 0xDE, 0xE8,
+	0x23, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
+	0x33, 0xD7, 0x1C, 0xBD,
+	0x3B, 0xD7, 0x23, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x4F, 0x80, 0x4F, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0xC1, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xC1, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
+	0x4E, 0x33, 0x4E, 0xCF,
+	0x57, 0x3B, 0x57, 0xCF,
 
-0x87, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x87, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
 
 static unsigned char warp_g400_tgzsf[] = {
 
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x88, 0x98, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
+	0xFF, 0x80, 0xC0, 0xE9,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
+	0x22, 0x40, 0x48, 0xBF,
+	0x2A, 0x40, 0x50, 0xBF,
 
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
+	0x32, 0x41, 0x49, 0xBF,
+	0x3A, 0x41, 0x51, 0xBF,
 
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
+	0xC3, 0x6B,
+	0xCB, 0x6B,
+	0x00, 0x88, 0x98, 0xE9,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x96, 0xE2,
+	0x41, 0x04,
 
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
+	0x7B, 0x43, 0xA0, 0xE8,
+	0x73, 0x4B, 0xA0, 0xE8,
 
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
+	0xAD, 0xEE, 0x29, 0x9F,
+	0x00, 0xE0,
+	0x49, 0x04,
 
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
+	0x90, 0xE2,
+	0x51, 0x04,
+	0x31, 0x46, 0xB1, 0xE8,
 
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
+	0x49, 0x41, 0xC0, 0xEC,
+	0x39, 0x57, 0xB1, 0xE8,
 
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
+	0x00, 0x04,
+	0x46, 0xE2,
+	0x73, 0x53, 0xA0, 0xE8,
 
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
+	0x51, 0x41, 0xC0, 0xEC,
+	0x31, 0x00,
+	0x39, 0x00,
 
-0x6A, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
+	0x6A, 0x80, 0x15, 0xEA,
+	0x08, 0x04,
+	0x10, 0x04,
 
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
+	0x51, 0x49, 0xC0, 0xEC,
+	0x2F, 0x41, 0x60, 0xEA,
 
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
+	0x31, 0x20,
+	0x39, 0x20,
+	0x1F, 0x42, 0xA0, 0xE8,
 
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
+	0x2A, 0x42, 0x4A, 0xBF,
+	0x27, 0x4A, 0xA0, 0xE8,
 
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
+	0x1A, 0x42, 0x52, 0xBF,
+	0x1E, 0x49, 0x60, 0xEA,
 
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
+	0x73, 0x7B, 0xC8, 0xEC,
+	0x26, 0x51, 0x60, 0xEA,
 
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
+	0x32, 0x40, 0x48, 0xBD,
+	0x22, 0x40, 0x50, 0xBD,
 
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
+	0x12, 0x41, 0x49, 0xBD,
+	0x3A, 0x41, 0x51, 0xBD,
 
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
+	0xBF, 0x2F, 0x26, 0xBD,
+	0x00, 0xE0,
+	0x7B, 0x72,
 
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
+	0x32, 0x20,
+	0x22, 0x20,
+	0x12, 0x20,
+	0x3A, 0x20,
 
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
+	0x46, 0x31, 0x46, 0xBF,
+	0x4E, 0x31, 0x4E, 0xBF,
 
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
+	0xB3, 0xE2, 0x2D, 0x9F,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
+	0x56, 0x31, 0x56, 0xBF,
+	0x47, 0x39, 0x47, 0xBF,
 
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
+	0x4F, 0x39, 0x4F, 0xBF,
+	0x57, 0x39, 0x57, 0xBF,
 
-0x5C, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
+	0x5C, 0x80, 0x07, 0xEA,
+	0x24, 0x41, 0x20, 0xE9,
 
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
+	0x42, 0x73, 0xF8, 0xEC,
+	0x00, 0xE0,
+	0x2D, 0x73,
 
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
+	0x33, 0x72,
+	0x0C, 0xE3,
+	0xA5, 0x2F, 0x1E, 0xBD,
 
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
+	0x43, 0x43, 0x2D, 0xDF,
+	0x4B, 0x4B, 0x2D, 0xDF,
 
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
+	0xAE, 0x1E, 0x26, 0xBD,
+	0x58, 0xE3,
+	0x33, 0x66,
 
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
+	0x53, 0x53, 0x2D, 0xDF,
+	0x00, 0x80, 0x00, 0xE8,
 
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
+	0xB8, 0x38, 0x33, 0xBF,
+	0x00, 0xE0,
+	0x59, 0xE3,
 
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
+	0x1E, 0x12, 0x41, 0xE9,
+	0x1A, 0x22, 0x41, 0xE9,
 
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
+	0x2B, 0x40, 0x3D, 0xE9,
+	0x3F, 0x4B, 0xA0, 0xE8,
 
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
+	0x2D, 0x73,
+	0x30, 0x76,
+	0x05, 0x80, 0x3D, 0xEA,
 
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
+	0x37, 0x43, 0xA0, 0xE8,
+	0x3D, 0x53, 0xA0, 0xE8,
 
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
+	0x48, 0x70, 0xF8, 0xEC,
+	0x2B, 0x48, 0x3C, 0xE9,
 
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x1F, 0x27, 0xBC, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
+	0x15, 0xC0, 0x20, 0xE9,
 
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
+	0x18, 0x3A, 0x41, 0xE9,
+	0x1D, 0x32, 0x41, 0xE9,
 
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
+	0x2A, 0x40, 0x20, 0xE9,
+	0x56, 0x3D, 0x56, 0xDF,
 
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
+	0x46, 0x37, 0x46, 0xDF,
+	0x4E, 0x3F, 0x4E, 0xDF,
 
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
+	0x16, 0x30, 0x20, 0xE9,
+	0x4F, 0x3F, 0x4F, 0xDF,
 
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
+	0x47, 0x37, 0x47, 0xDF,
+	0x57, 0x3D, 0x57, 0xDF,
 
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
+	0x32, 0x32, 0x2D, 0xDF,
+	0x22, 0x22, 0x2D, 0xDF,
 
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
+	0x12, 0x12, 0x2D, 0xDF,
+	0x3A, 0x3A, 0x2D, 0xDF,
 
-0x27, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
+	0x27, 0xCF, 0x74, 0xC2,
+	0x37, 0xCF, 0x74, 0xC4,
 
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
+	0x0A, 0x44, 0x4C, 0xB0,
+	0x02, 0x44, 0x54, 0xB0,
 
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
+	0x3D, 0xCF, 0x74, 0xC0,
+	0x34, 0x37, 0x20, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x38, 0x27, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3C, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
+	0x2A, 0x44, 0x4C, 0xB2,
+	0x1A, 0x44, 0x54, 0xB2,
 
-0x2E, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
+	0x2E, 0x80, 0x3A, 0xEA,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x27, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x27, 0xCF, 0x75, 0xC0,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x32, 0x31, 0x5F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x33, 0x39, 0x5F, 0xE9,
 
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
+	0x3D, 0xCF, 0x75, 0xC2,
+	0x37, 0xCF, 0x75, 0xC4,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA6, 0x27, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA3, 0x3D, 0x20, 0xE9,
 
-0x2A, 0x44, 0x4C, 0xB4,
-0x1A, 0x44, 0x54, 0xB4,
+	0x2A, 0x44, 0x4C, 0xB4,
+	0x1A, 0x44, 0x54, 0xB4,
 
-0x0A, 0x45, 0x4D, 0xB0,
-0x02, 0x45, 0x55, 0xB0,
+	0x0A, 0x45, 0x4D, 0xB0,
+	0x02, 0x45, 0x55, 0xB0,
 
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x88, 0x73, 0x5E, 0xE9,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0xA0, 0x37, 0x20, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x3E, 0x30, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x3F, 0x38, 0x4F, 0xE9,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x3A, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x3B, 0x39, 0x4F, 0xE9,
 
-0x2A, 0x45, 0x4D, 0xB2,
-0x1A, 0x45, 0x55, 0xB2,
+	0x2A, 0x45, 0x4D, 0xB2,
+	0x1A, 0x45, 0x55, 0xB2,
 
-0x0A, 0x45, 0x4D, 0xB4,
-0x02, 0x45, 0x55, 0xB4,
+	0x0A, 0x45, 0x4D, 0xB4,
+	0x02, 0x45, 0x55, 0xB4,
 
-0x27, 0xCF, 0x75, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x27, 0xCF, 0x75, 0xC6,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0xA7, 0x30, 0x4F, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
+	0xA7, 0x30, 0x4F, 0xE9,
+	0x0A, 0x20,
+	0x02, 0x20,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x31, 0x27, 0x20, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x31, 0x27, 0x20, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA8, 0x38, 0x4F, 0xE9,
 
-0x2A, 0x45, 0x4D, 0xB6,
-0x1A, 0x45, 0x55, 0xB6,
+	0x2A, 0x45, 0x4D, 0xB6,
+	0x1A, 0x45, 0x55, 0xB6,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x36, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x37, 0x39, 0x4F, 0xE9,
 
-0x00, 0x80, 0x00, 0xE8,
-0x2A, 0x20,
-0x1A, 0x20,
+	0x00, 0x80, 0x00, 0xE8,
+	0x2A, 0x20,
+	0x1A, 0x20,
 
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
+	0x2A, 0x46, 0x4E, 0xBF,
+	0x1A, 0x46, 0x56, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA4, 0x31, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA5, 0x39, 0x4F, 0xE9,
 
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
+	0x0A, 0x47, 0x4F, 0xBF,
+	0x02, 0x47, 0x57, 0xBF,
 
-0x31, 0x53, 0x2F, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0xA1, 0x30, 0x4F, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0xA2, 0x38, 0x4F, 0xE9,
 
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
+	0x2A, 0x43, 0x4B, 0xBF,
+	0x1A, 0x43, 0x53, 0xBF,
 
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x31, 0x4F, 0xE9,
+	0x30, 0x50, 0x2E, 0x9F,
+	0x35, 0x31, 0x4F, 0xE9,
 
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x39, 0x4F, 0xE9,
+	0x38, 0x21, 0x2C, 0x9F,
+	0x39, 0x39, 0x4F, 0xE9,
 
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
+	0x31, 0x53, 0x2F, 0x9F,
+	0x80, 0x31, 0x57, 0xE9,
 
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
+	0x39, 0xE5, 0x2C, 0x9F,
+	0x81, 0x39, 0x57, 0xE9,
 
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
+	0x37, 0x48, 0x50, 0xBD,
+	0x8A, 0x36, 0x20, 0xE9,
 
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
+	0x86, 0x76, 0x57, 0xE9,
+	0x8B, 0x3E, 0x20, 0xE9,
 
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
+	0x82, 0x30, 0x57, 0xE9,
+	0x87, 0x77, 0x57, 0xE9,
 
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
+	0x83, 0x38, 0x57, 0xE9,
+	0x35, 0x49, 0x51, 0xBD,
 
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
+	0x84, 0x31, 0x5E, 0xE9,
+	0x30, 0x1F, 0x5F, 0xE9,
 
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
+	0x85, 0x39, 0x5E, 0xE9,
+	0x57, 0x25, 0x20, 0xE9,
 
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
+	0x2B, 0x48, 0x20, 0xE9,
+	0x1D, 0x37, 0xE1, 0xEA,
 
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
+	0x1E, 0x35, 0xE1, 0xEA,
+	0x00, 0xE0,
+	0x26, 0x77,
 
-0x24, 0x49, 0x20, 0xE9,
-0x9D, 0xFF, 0x20, 0xEA,
+	0x24, 0x49, 0x20, 0xE9,
+	0x9D, 0xFF, 0x20, 0xEA,
 
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
+	0x16, 0x26, 0x20, 0xE9,
+	0x57, 0x2E, 0xBF, 0xEA,
 
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
+	0x1C, 0x46, 0xA0, 0xE8,
+	0x23, 0x4E, 0xA0, 0xE8,
 
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
+	0x2B, 0x56, 0xA0, 0xE8,
+	0x1D, 0x47, 0xA0, 0xE8,
 
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
+	0x24, 0x4F, 0xA0, 0xE8,
+	0x2C, 0x57, 0xA0, 0xE8,
 
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
+	0x1C, 0x00,
+	0x23, 0x00,
+	0x2B, 0x00,
+	0x00, 0xE0,
 
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
+	0x1D, 0x00,
+	0x24, 0x00,
+	0x2C, 0x00,
+	0x00, 0xE0,
 
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
+	0x1C, 0x65,
+	0x23, 0x65,
+	0x2B, 0x65,
+	0x00, 0xE0,
 
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
+	0x1D, 0x65,
+	0x24, 0x65,
+	0x2C, 0x65,
+	0x00, 0xE0,
 
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
+	0x1C, 0x23, 0x60, 0xEC,
+	0x36, 0xD7, 0x36, 0xAD,
 
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
+	0x2B, 0x80, 0x60, 0xEC,
+	0x1D, 0x24, 0x60, 0xEC,
 
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
+	0x3E, 0xD7, 0x3E, 0xAD,
+	0x2C, 0x80, 0x60, 0xEC,
 
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
+	0x1C, 0x2B, 0xDE, 0xE8,
+	0x23, 0x80, 0xDE, 0xE8,
 
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
+	0x36, 0x80, 0x36, 0xBD,
+	0x3E, 0x80, 0x3E, 0xBD,
 
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
+	0x33, 0xD7, 0x1C, 0xBD,
+	0x3B, 0xD7, 0x23, 0xBD,
 
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
+	0x46, 0x80, 0x46, 0xCF,
+	0x4F, 0x80, 0x4F, 0xCF,
 
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
+	0x56, 0x33, 0x56, 0xCF,
+	0x47, 0x3B, 0x47, 0xCF,
 
-0xC5, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
+	0xC5, 0xFF, 0x20, 0xEA,
+	0x00, 0x80, 0x00, 0xE8,
 
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
+	0x4E, 0x33, 0x4E, 0xCF,
+	0x57, 0x3B, 0x57, 0xCF,
 
-0x8B, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
+	0x8B, 0xFF, 0x20, 0xEA,
+	0x57, 0xC0, 0xBF, 0xEA,
 
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
+	0x00, 0x80, 0xA0, 0xE9,
+	0x00, 0x00, 0xD8, 0xEC,
 
 };
diff --git a/shared-core/mga_warp.c b/shared-core/mga_warp.c
index 0a3a0cc7..a5d35911 100644
--- a/shared-core/mga_warp.c
+++ b/shared-core/mga_warp.c
@@ -33,8 +33,7 @@
 #include "mga_drv.h"
 #include "mga_ucode.h"
 
-
-#define MGA_WARP_CODE_ALIGN		256		/* in bytes */
+#define MGA_WARP_CODE_ALIGN		256	/* in bytes */
 
 #define WARP_UCODE_SIZE( which )					\
 	((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN)
@@ -48,125 +47,122 @@ do {									\
 	vcbase += WARP_UCODE_SIZE( which );				\
 } while (0)
 
-
-static unsigned int mga_warp_g400_microcode_size( drm_mga_private_t *dev_priv )
+static unsigned int mga_warp_g400_microcode_size(drm_mga_private_t * dev_priv)
 {
 	unsigned int size;
 
-	size = ( WARP_UCODE_SIZE( warp_g400_tgz ) +
-		 WARP_UCODE_SIZE( warp_g400_tgza ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzaf ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzf ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzs ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzsa ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzsaf ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzsf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gz ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gza ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzaf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzs ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzsa ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzsaf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzsf ) );
-
-	size = PAGE_ALIGN( size );
-
-	DRM_DEBUG( "G400 ucode size = %d bytes\n", size );
+	size = (WARP_UCODE_SIZE(warp_g400_tgz) +
+		WARP_UCODE_SIZE(warp_g400_tgza) +
+		WARP_UCODE_SIZE(warp_g400_tgzaf) +
+		WARP_UCODE_SIZE(warp_g400_tgzf) +
+		WARP_UCODE_SIZE(warp_g400_tgzs) +
+		WARP_UCODE_SIZE(warp_g400_tgzsa) +
+		WARP_UCODE_SIZE(warp_g400_tgzsaf) +
+		WARP_UCODE_SIZE(warp_g400_tgzsf) +
+		WARP_UCODE_SIZE(warp_g400_t2gz) +
+		WARP_UCODE_SIZE(warp_g400_t2gza) +
+		WARP_UCODE_SIZE(warp_g400_t2gzaf) +
+		WARP_UCODE_SIZE(warp_g400_t2gzf) +
+		WARP_UCODE_SIZE(warp_g400_t2gzs) +
+		WARP_UCODE_SIZE(warp_g400_t2gzsa) +
+		WARP_UCODE_SIZE(warp_g400_t2gzsaf) +
+		WARP_UCODE_SIZE(warp_g400_t2gzsf));
+
+	size = PAGE_ALIGN(size);
+
+	DRM_DEBUG("G400 ucode size = %d bytes\n", size);
 	return size;
 }
 
-static unsigned int mga_warp_g200_microcode_size( drm_mga_private_t *dev_priv )
+static unsigned int mga_warp_g200_microcode_size(drm_mga_private_t * dev_priv)
 {
 	unsigned int size;
 
-	size = ( WARP_UCODE_SIZE( warp_g200_tgz ) +
-		 WARP_UCODE_SIZE( warp_g200_tgza ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzaf ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzf ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzs ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzsa ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzsaf ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzsf ) );
+	size = (WARP_UCODE_SIZE(warp_g200_tgz) +
+		WARP_UCODE_SIZE(warp_g200_tgza) +
+		WARP_UCODE_SIZE(warp_g200_tgzaf) +
+		WARP_UCODE_SIZE(warp_g200_tgzf) +
+		WARP_UCODE_SIZE(warp_g200_tgzs) +
+		WARP_UCODE_SIZE(warp_g200_tgzsa) +
+		WARP_UCODE_SIZE(warp_g200_tgzsaf) +
+		WARP_UCODE_SIZE(warp_g200_tgzsf));
 
-	size = PAGE_ALIGN( size );
+	size = PAGE_ALIGN(size);
 
-	DRM_DEBUG( "G200 ucode size = %d bytes\n", size );
+	DRM_DEBUG("G200 ucode size = %d bytes\n", size);
 	return size;
 }
 
-static int mga_warp_install_g400_microcode( drm_mga_private_t *dev_priv )
+static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv)
 {
 	unsigned char *vcbase = dev_priv->warp->handle;
 	unsigned long pcbase = dev_priv->warp->offset;
 	unsigned int size;
 
-	size = mga_warp_g400_microcode_size( dev_priv );
-	if ( size > dev_priv->warp->size ) {
-		DRM_ERROR( "microcode too large! (%u > %lu)\n",
-			   size, dev_priv->warp->size );
+	size = mga_warp_g400_microcode_size(dev_priv);
+	if (size > dev_priv->warp->size) {
+		DRM_ERROR("microcode too large! (%u > %lu)\n",
+			  size, dev_priv->warp->size);
 		return DRM_ERR(ENOMEM);
 	}
 
-	memset( dev_priv->warp_pipe_phys, 0,
-		sizeof(dev_priv->warp_pipe_phys) );
-
-	WARP_UCODE_INSTALL( warp_g400_tgz,	MGA_WARP_TGZ );
-	WARP_UCODE_INSTALL( warp_g400_tgzf,	MGA_WARP_TGZF );
-	WARP_UCODE_INSTALL( warp_g400_tgza,	MGA_WARP_TGZA );
-	WARP_UCODE_INSTALL( warp_g400_tgzaf,	MGA_WARP_TGZAF );
-	WARP_UCODE_INSTALL( warp_g400_tgzs,	MGA_WARP_TGZS );
-	WARP_UCODE_INSTALL( warp_g400_tgzsf,	MGA_WARP_TGZSF );
-	WARP_UCODE_INSTALL( warp_g400_tgzsa,	MGA_WARP_TGZSA );
-	WARP_UCODE_INSTALL( warp_g400_tgzsaf,	MGA_WARP_TGZSAF );
-
-	WARP_UCODE_INSTALL( warp_g400_t2gz,	MGA_WARP_T2GZ );
-	WARP_UCODE_INSTALL( warp_g400_t2gzf,	MGA_WARP_T2GZF );
-	WARP_UCODE_INSTALL( warp_g400_t2gza,	MGA_WARP_T2GZA );
-	WARP_UCODE_INSTALL( warp_g400_t2gzaf,	MGA_WARP_T2GZAF );
-	WARP_UCODE_INSTALL( warp_g400_t2gzs,	MGA_WARP_T2GZS );
-	WARP_UCODE_INSTALL( warp_g400_t2gzsf,	MGA_WARP_T2GZSF );
-	WARP_UCODE_INSTALL( warp_g400_t2gzsa,	MGA_WARP_T2GZSA );
-	WARP_UCODE_INSTALL( warp_g400_t2gzsaf,	MGA_WARP_T2GZSAF );
+	memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
+
+	WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ);
+	WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF);
+	WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA);
+	WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF);
+	WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS);
+	WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF);
+	WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA);
+	WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF);
+
+	WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ);
+	WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF);
+	WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA);
+	WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF);
+	WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS);
+	WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF);
+	WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA);
+	WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF);
 
 	return 0;
 }
 
-static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv )
+static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv)
 {
 	unsigned char *vcbase = dev_priv->warp->handle;
 	unsigned long pcbase = dev_priv->warp->offset;
 	unsigned int size;
 
-	size = mga_warp_g200_microcode_size( dev_priv );
-	if ( size > dev_priv->warp->size ) {
-		DRM_ERROR( "microcode too large! (%u > %lu)\n",
-			   size, dev_priv->warp->size );
+	size = mga_warp_g200_microcode_size(dev_priv);
+	if (size > dev_priv->warp->size) {
+		DRM_ERROR("microcode too large! (%u > %lu)\n",
+			  size, dev_priv->warp->size);
 		return DRM_ERR(ENOMEM);
 	}
 
-	memset( dev_priv->warp_pipe_phys, 0,
-		sizeof(dev_priv->warp_pipe_phys) );
+	memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
 
-	WARP_UCODE_INSTALL( warp_g200_tgz,	MGA_WARP_TGZ );
-	WARP_UCODE_INSTALL( warp_g200_tgzf,	MGA_WARP_TGZF );
-	WARP_UCODE_INSTALL( warp_g200_tgza,	MGA_WARP_TGZA );
-	WARP_UCODE_INSTALL( warp_g200_tgzaf,	MGA_WARP_TGZAF );
-	WARP_UCODE_INSTALL( warp_g200_tgzs,	MGA_WARP_TGZS );
-	WARP_UCODE_INSTALL( warp_g200_tgzsf,	MGA_WARP_TGZSF );
-	WARP_UCODE_INSTALL( warp_g200_tgzsa,	MGA_WARP_TGZSA );
-	WARP_UCODE_INSTALL( warp_g200_tgzsaf,	MGA_WARP_TGZSAF );
+	WARP_UCODE_INSTALL(warp_g200_tgz, MGA_WARP_TGZ);
+	WARP_UCODE_INSTALL(warp_g200_tgzf, MGA_WARP_TGZF);
+	WARP_UCODE_INSTALL(warp_g200_tgza, MGA_WARP_TGZA);
+	WARP_UCODE_INSTALL(warp_g200_tgzaf, MGA_WARP_TGZAF);
+	WARP_UCODE_INSTALL(warp_g200_tgzs, MGA_WARP_TGZS);
+	WARP_UCODE_INSTALL(warp_g200_tgzsf, MGA_WARP_TGZSF);
+	WARP_UCODE_INSTALL(warp_g200_tgzsa, MGA_WARP_TGZSA);
+	WARP_UCODE_INSTALL(warp_g200_tgzsaf, MGA_WARP_TGZSAF);
 
 	return 0;
 }
 
-int mga_warp_install_microcode(	drm_mga_private_t *dev_priv )
+int mga_warp_install_microcode(drm_mga_private_t * dev_priv)
 {
-	switch ( dev_priv->chipset ) {
+	switch (dev_priv->chipset) {
 	case MGA_CARD_TYPE_G400:
-		return mga_warp_install_g400_microcode( dev_priv );
+		return mga_warp_install_g400_microcode(dev_priv);
 	case MGA_CARD_TYPE_G200:
-		return mga_warp_install_g200_microcode( dev_priv );
+		return mga_warp_install_g200_microcode(dev_priv);
 	default:
 		return DRM_ERR(EINVAL);
 	}
@@ -174,35 +170,34 @@ int mga_warp_install_microcode(	drm_mga_private_t *dev_priv )
 
 #define WMISC_EXPECTED		(MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE)
 
-int mga_warp_init( drm_mga_private_t *dev_priv )
+int mga_warp_init(drm_mga_private_t * dev_priv)
 {
 	u32 wmisc;
 
 	/* FIXME: Get rid of these damned magic numbers...
 	 */
-	switch ( dev_priv->chipset ) {
+	switch (dev_priv->chipset) {
 	case MGA_CARD_TYPE_G400:
-		MGA_WRITE( MGA_WIADDR2, MGA_WMODE_SUSPEND );
-		MGA_WRITE( MGA_WGETMSB, 0x00000E00 );
-		MGA_WRITE( MGA_WVRTXSZ, 0x00001807 );
-		MGA_WRITE( MGA_WACCEPTSEQ, 0x18000000 );
+		MGA_WRITE(MGA_WIADDR2, MGA_WMODE_SUSPEND);
+		MGA_WRITE(MGA_WGETMSB, 0x00000E00);
+		MGA_WRITE(MGA_WVRTXSZ, 0x00001807);
+		MGA_WRITE(MGA_WACCEPTSEQ, 0x18000000);
 		break;
 	case MGA_CARD_TYPE_G200:
-		MGA_WRITE( MGA_WIADDR, MGA_WMODE_SUSPEND );
-		MGA_WRITE( MGA_WGETMSB, 0x1606 );
-		MGA_WRITE( MGA_WVRTXSZ, 7 );
+		MGA_WRITE(MGA_WIADDR, MGA_WMODE_SUSPEND);
+		MGA_WRITE(MGA_WGETMSB, 0x1606);
+		MGA_WRITE(MGA_WVRTXSZ, 7);
 		break;
 	default:
 		return DRM_ERR(EINVAL);
 	}
 
-	MGA_WRITE( MGA_WMISC, (MGA_WUCODECACHE_ENABLE |
-			       MGA_WMASTER_ENABLE |
-			       MGA_WCACHEFLUSH_ENABLE) );
-	wmisc = MGA_READ( MGA_WMISC );
-	if ( wmisc != WMISC_EXPECTED ) {
-		DRM_ERROR( "WARP engine config failed! 0x%x != 0x%x\n",
-			   wmisc, WMISC_EXPECTED );
+	MGA_WRITE(MGA_WMISC, (MGA_WUCODECACHE_ENABLE |
+			      MGA_WMASTER_ENABLE | MGA_WCACHEFLUSH_ENABLE));
+	wmisc = MGA_READ(MGA_WMISC);
+	if (wmisc != WMISC_EXPECTED) {
+		DRM_ERROR("WARP engine config failed! 0x%x != 0x%x\n",
+			  wmisc, WMISC_EXPECTED);
 		return DRM_ERR(EINVAL);
 	}
 
diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c
index 172ea258..4246cc7c 100644
--- a/shared-core/r128_cce.c
+++ b/shared-core/r128_cce.c
@@ -80,7 +80,7 @@ static u32 r128_cce_microcode[] = {
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 };
 
-int R128_READ_PLL(drm_device_t *dev, int addr)
+int R128_READ_PLL(drm_device_t * dev, int addr)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 
@@ -89,106 +89,105 @@ int R128_READ_PLL(drm_device_t *dev, int addr)
 }
 
 #if R128_FIFO_DEBUG
-static void r128_status( drm_r128_private_t *dev_priv )
+static void r128_status(drm_r128_private_t * dev_priv)
 {
-	printk( "GUI_STAT           = 0x%08x\n",
-		(unsigned int)R128_READ( R128_GUI_STAT ) );
-	printk( "PM4_STAT           = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_STAT ) );
-	printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) );
-	printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) );
-	printk( "PM4_MICRO_CNTL     = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) );
-	printk( "PM4_BUFFER_CNTL    = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) );
+	printk("GUI_STAT           = 0x%08x\n",
+	       (unsigned int)R128_READ(R128_GUI_STAT));
+	printk("PM4_STAT           = 0x%08x\n",
+	       (unsigned int)R128_READ(R128_PM4_STAT));
+	printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
+	       (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
+	printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
+	       (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
+	printk("PM4_MICRO_CNTL     = 0x%08x\n",
+	       (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
+	printk("PM4_BUFFER_CNTL    = 0x%08x\n",
+	       (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
 }
 #endif
 
-
 /* ================================================================
  * Engine, FIFO control
  */
 
-static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv )
+static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
 {
 	u32 tmp;
 	int i;
 
-	tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL;
-	R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp );
+	tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
+	R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) {
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
 			return 0;
 		}
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
 #if R128_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
+	DRM_ERROR("failed!\n");
 #endif
 	return DRM_ERR(EBUSY);
 }
 
-static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
+static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
 {
 	int i;
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
-		if ( slots >= entries ) return 0;
-		DRM_UDELAY( 1 );
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
+		if (slots >= entries)
+			return 0;
+		DRM_UDELAY(1);
 	}
 
 #if R128_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
+	DRM_ERROR("failed!\n");
 #endif
 	return DRM_ERR(EBUSY);
 }
 
-static int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
+static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
 {
 	int i, ret;
 
-	ret = r128_do_wait_for_fifo( dev_priv, 64 );
-	if ( ret ) return ret;
+	ret = r128_do_wait_for_fifo(dev_priv, 64);
+	if (ret)
+		return ret;
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) {
-			r128_do_pixcache_flush( dev_priv );
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
+			r128_do_pixcache_flush(dev_priv);
 			return 0;
 		}
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
 #if R128_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
+	DRM_ERROR("failed!\n");
 #endif
 	return DRM_ERR(EBUSY);
 }
 
-
 /* ================================================================
  * CCE control, initialization
  */
 
 /* Load the microcode for the CCE */
-static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
+static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
 {
 	int i;
 
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	r128_do_wait_for_idle( dev_priv );
+	r128_do_wait_for_idle(dev_priv);
 
-	R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 );
-	for ( i = 0 ; i < 256 ; i++ ) {
-		R128_WRITE( R128_PM4_MICROCODE_DATAH,
-			    r128_cce_microcode[i * 2] );
-		R128_WRITE( R128_PM4_MICROCODE_DATAL,
-			    r128_cce_microcode[i * 2 + 1] );
+	R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
+	for (i = 0; i < 256; i++) {
+		R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
+		R128_WRITE(R128_PM4_MICROCODE_DATAL,
+			   r128_cce_microcode[i * 2 + 1]);
 	}
 }
 
@@ -196,51 +195,51 @@ static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
  * prior to a wait for idle, as it informs the engine that the command
  * stream is ending.
  */
-static void r128_do_cce_flush( drm_r128_private_t *dev_priv )
+static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
 {
 	u32 tmp;
 
-	tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE;
-	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp );
+	tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
+	R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
 }
 
 /* Wait for the CCE to go idle.
  */
-int r128_do_cce_idle( drm_r128_private_t *dev_priv )
+int r128_do_cce_idle(drm_r128_private_t * dev_priv)
 {
 	int i;
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( GET_RING_HEAD( dev_priv ) == dev_priv->ring.tail ) {
-			int pm4stat = R128_READ( R128_PM4_STAT );
-			if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
-			       dev_priv->cce_fifo_size ) &&
-			     !(pm4stat & (R128_PM4_BUSY |
-					  R128_PM4_GUI_ACTIVE)) ) {
-				return r128_do_pixcache_flush( dev_priv );
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
+			int pm4stat = R128_READ(R128_PM4_STAT);
+			if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
+			     dev_priv->cce_fifo_size) &&
+			    !(pm4stat & (R128_PM4_BUSY |
+					 R128_PM4_GUI_ACTIVE))) {
+				return r128_do_pixcache_flush(dev_priv);
 			}
 		}
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
 #if R128_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	r128_status( dev_priv );
+	DRM_ERROR("failed!\n");
+	r128_status(dev_priv);
 #endif
 	return DRM_ERR(EBUSY);
 }
 
 /* Start the Concurrent Command Engine.
  */
-static void r128_do_cce_start( drm_r128_private_t *dev_priv )
+static void r128_do_cce_start(drm_r128_private_t * dev_priv)
 {
-	r128_do_wait_for_idle( dev_priv );
+	r128_do_wait_for_idle(dev_priv);
 
-	R128_WRITE( R128_PM4_BUFFER_CNTL,
-		    dev_priv->cce_mode | dev_priv->ring.size_l2qw
-		    | R128_PM4_BUFFER_CNTL_NOUPDATE );
-	R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */
-	R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN );
+	R128_WRITE(R128_PM4_BUFFER_CNTL,
+		   dev_priv->cce_mode | dev_priv->ring.size_l2qw
+		   | R128_PM4_BUFFER_CNTL_NOUPDATE);
+	R128_READ(R128_PM4_BUFFER_ADDR);	/* as per the sample code */
+	R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
 
 	dev_priv->cce_running = 1;
 }
@@ -249,10 +248,10 @@ static void r128_do_cce_start( drm_r128_private_t *dev_priv )
  * commands, so you must wait for the CCE command stream to complete
  * before calling this routine.
  */
-static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
+static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
 {
-	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
-	R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
+	R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
+	R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
 	dev_priv->ring.tail = 0;
 }
 
@@ -260,121 +259,119 @@ static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
  * commands, so you must flush the command stream and wait for the CCE
  * to go idle before calling this routine.
  */
-static void r128_do_cce_stop( drm_r128_private_t *dev_priv )
+static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
 {
-	R128_WRITE( R128_PM4_MICRO_CNTL, 0 );
-	R128_WRITE( R128_PM4_BUFFER_CNTL,
-		    R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE );
+	R128_WRITE(R128_PM4_MICRO_CNTL, 0);
+	R128_WRITE(R128_PM4_BUFFER_CNTL,
+		   R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
 
 	dev_priv->cce_running = 0;
 }
 
 /* Reset the engine.  This will stop the CCE if it is running.
  */
-static int r128_do_engine_reset( drm_device_t *dev )
+static int r128_do_engine_reset(drm_device_t * dev)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
 
-	r128_do_pixcache_flush( dev_priv );
+	r128_do_pixcache_flush(dev_priv);
 
-	clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX );
-	mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL );
+	clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
+	mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
 
-	R128_WRITE_PLL( R128_MCLK_CNTL,
-			mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP );
+	R128_WRITE_PLL(R128_MCLK_CNTL,
+		       mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
 
-	gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL );
+	gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
 
 	/* Taken from the sample code - do not change */
-	R128_WRITE( R128_GEN_RESET_CNTL,
-		    gen_reset_cntl | R128_SOFT_RESET_GUI );
-	R128_READ( R128_GEN_RESET_CNTL );
-	R128_WRITE( R128_GEN_RESET_CNTL,
-		    gen_reset_cntl & ~R128_SOFT_RESET_GUI );
-	R128_READ( R128_GEN_RESET_CNTL );
+	R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
+	R128_READ(R128_GEN_RESET_CNTL);
+	R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
+	R128_READ(R128_GEN_RESET_CNTL);
 
-	R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl );
-	R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index );
-	R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl );
+	R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
+	R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
+	R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
 
 	/* Reset the CCE ring */
-	r128_do_cce_reset( dev_priv );
+	r128_do_cce_reset(dev_priv);
 
 	/* The CCE is no longer running after an engine reset */
 	dev_priv->cce_running = 0;
 
 	/* Reset any pending vertex, indirect buffers */
-	r128_freelist_reset( dev );
+	r128_freelist_reset(dev);
 
 	return 0;
 }
 
-static void r128_cce_init_ring_buffer( drm_device_t *dev,
-				       drm_r128_private_t *dev_priv )
+static void r128_cce_init_ring_buffer(drm_device_t * dev,
+				      drm_r128_private_t * dev_priv)
 {
 	u32 ring_start;
 	u32 tmp;
 
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	/* The manual (p. 2) says this address is in "VM space".  This
 	 * means it's an offset from the start of AGP space.
 	 */
 #if __OS_HAS_AGP
-	if ( !dev_priv->is_pci )
+	if (!dev_priv->is_pci)
 		ring_start = dev_priv->cce_ring->offset - dev->agp->base;
 	else
 #endif
 		ring_start = dev_priv->cce_ring->offset - dev->sg->handle;
 
-	R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET );
+	R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
 
-	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
-	R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
+	R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
+	R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
 
 	/* Set watermark control */
-	R128_WRITE( R128_PM4_BUFFER_WM_CNTL,
-		    ((R128_WATERMARK_L/4) << R128_WMA_SHIFT)
-		    | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT)
-		    | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT)
-		    | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) );
+	R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
+		   ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
+		   | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
+		   | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
+		   | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
 
 	/* Force read.  Why?  Because it's in the examples... */
-	R128_READ( R128_PM4_BUFFER_ADDR );
+	R128_READ(R128_PM4_BUFFER_ADDR);
 
 	/* Turn on bus mastering */
-	tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS;
-	R128_WRITE( R128_BUS_CNTL, tmp );
+	tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
+	R128_WRITE(R128_BUS_CNTL, tmp);
 }
 
-static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
+static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
 {
 	drm_r128_private_t *dev_priv;
 
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	dev_priv = drm_alloc( sizeof(drm_r128_private_t), DRM_MEM_DRIVER );
-	if ( dev_priv == NULL )
+	dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
+	if (dev_priv == NULL)
 		return DRM_ERR(ENOMEM);
 
-	memset( dev_priv, 0, sizeof(drm_r128_private_t) );
+	memset(dev_priv, 0, sizeof(drm_r128_private_t));
 
 	dev_priv->is_pci = init->is_pci;
 
-	if ( dev_priv->is_pci && !dev->sg ) {
-		DRM_ERROR( "PCI GART memory not allocated!\n" );
+	if (dev_priv->is_pci && !dev->sg) {
+		DRM_ERROR("PCI GART memory not allocated!\n");
 		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
+		r128_do_cleanup_cce(dev);
 		return DRM_ERR(EINVAL);
 	}
 
 	dev_priv->usec_timeout = init->usec_timeout;
-	if ( dev_priv->usec_timeout < 1 ||
-	     dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) {
-		DRM_DEBUG( "TIMEOUT problem!\n" );
+	if (dev_priv->usec_timeout < 1 ||
+	    dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
+		DRM_DEBUG("TIMEOUT problem!\n");
 		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
+		r128_do_cleanup_cce(dev);
 		return DRM_ERR(EINVAL);
 	}
 
@@ -382,23 +379,23 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
 
 	/* GH: Simple idle check.
 	 */
-	atomic_set( &dev_priv->idle_count, 0 );
+	atomic_set(&dev_priv->idle_count, 0);
 
 	/* We don't support anything other than bus-mastering ring mode,
 	 * but the ring can be in either AGP or PCI space for the ring
 	 * read pointer.
 	 */
-	if ( ( init->cce_mode != R128_PM4_192BM ) &&
-	     ( init->cce_mode != R128_PM4_128BM_64INDBM ) &&
-	     ( init->cce_mode != R128_PM4_64BM_128INDBM ) &&
-	     ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) {
-		DRM_DEBUG( "Bad cce_mode!\n" );
+	if ((init->cce_mode != R128_PM4_192BM) &&
+	    (init->cce_mode != R128_PM4_128BM_64INDBM) &&
+	    (init->cce_mode != R128_PM4_64BM_128INDBM) &&
+	    (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
+		DRM_DEBUG("Bad cce_mode!\n");
 		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
+		r128_do_cleanup_cce(dev);
 		return DRM_ERR(EINVAL);
 	}
 
-	switch ( init->cce_mode ) {
+	switch (init->cce_mode) {
 	case R128_PM4_NONPM4:
 		dev_priv->cce_fifo_size = 0;
 		break;
@@ -419,7 +416,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
 		break;
 	}
 
-	switch ( init->fb_bpp ) {
+	switch (init->fb_bpp) {
 	case 16:
 		dev_priv->color_fmt = R128_DATATYPE_RGB565;
 		break;
@@ -428,12 +425,12 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
 		dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
 		break;
 	}
-	dev_priv->front_offset	= init->front_offset;
-	dev_priv->front_pitch	= init->front_pitch;
-	dev_priv->back_offset	= init->back_offset;
-	dev_priv->back_pitch	= init->back_pitch;
+	dev_priv->front_offset = init->front_offset;
+	dev_priv->front_pitch = init->front_pitch;
+	dev_priv->back_offset = init->back_offset;
+	dev_priv->back_pitch = init->back_pitch;
 
-	switch ( init->depth_bpp ) {
+	switch (init->depth_bpp) {
 	case 16:
 		dev_priv->depth_fmt = R128_DATATYPE_RGB565;
 		break;
@@ -443,219 +440,220 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
 		dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
 		break;
 	}
-	dev_priv->depth_offset	= init->depth_offset;
-	dev_priv->depth_pitch	= init->depth_pitch;
-	dev_priv->span_offset	= init->span_offset;
+	dev_priv->depth_offset = init->depth_offset;
+	dev_priv->depth_pitch = init->depth_pitch;
+	dev_priv->span_offset = init->span_offset;
 
-	dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) |
+	dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
 					  (dev_priv->front_offset >> 5));
-	dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) |
+	dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
 					 (dev_priv->back_offset >> 5));
-	dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
+	dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
 					  (dev_priv->depth_offset >> 5) |
 					  R128_DST_TILE);
-	dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
+	dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
 					 (dev_priv->span_offset >> 5));
 
 	DRM_GETSAREA();
-	
-	if(!dev_priv->sarea) {
+
+	if (!dev_priv->sarea) {
 		DRM_ERROR("could not find sarea!\n");
 		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
+		r128_do_cleanup_cce(dev);
 		return DRM_ERR(EINVAL);
 	}
 
 	dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
-	if(!dev_priv->mmio) {
+	if (!dev_priv->mmio) {
 		DRM_ERROR("could not find mmio region!\n");
 		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
+		r128_do_cleanup_cce(dev);
 		return DRM_ERR(EINVAL);
 	}
 	dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
-	if(!dev_priv->cce_ring) {
+	if (!dev_priv->cce_ring) {
 		DRM_ERROR("could not find cce ring region!\n");
 		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
+		r128_do_cleanup_cce(dev);
 		return DRM_ERR(EINVAL);
 	}
 	dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
-	if(!dev_priv->ring_rptr) {
+	if (!dev_priv->ring_rptr) {
 		DRM_ERROR("could not find ring read pointer!\n");
 		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
+		r128_do_cleanup_cce(dev);
 		return DRM_ERR(EINVAL);
 	}
 	dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
-	if(!dev->agp_buffer_map) {
+	if (!dev->agp_buffer_map) {
 		DRM_ERROR("could not find dma buffer region!\n");
 		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
+		r128_do_cleanup_cce(dev);
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( !dev_priv->is_pci ) {
-		dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset);
-		if(!dev_priv->agp_textures) {
+	if (!dev_priv->is_pci) {
+		dev_priv->agp_textures =
+		    drm_core_findmap(dev, init->agp_textures_offset);
+		if (!dev_priv->agp_textures) {
 			DRM_ERROR("could not find agp texture region!\n");
 			dev->dev_private = (void *)dev_priv;
-			r128_do_cleanup_cce( dev );
+			r128_do_cleanup_cce(dev);
 			return DRM_ERR(EINVAL);
 		}
 	}
 
 	dev_priv->sarea_priv =
-		(drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle +
-				     init->sarea_priv_offset);
+	    (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
+				  init->sarea_priv_offset);
 
 #if __OS_HAS_AGP
-	if ( !dev_priv->is_pci ) {
-		drm_core_ioremap( dev_priv->cce_ring, dev );
-		drm_core_ioremap( dev_priv->ring_rptr, dev );
-		drm_core_ioremap( dev->agp_buffer_map, dev );
-		if(!dev_priv->cce_ring->handle ||
-		   !dev_priv->ring_rptr->handle ||
-		   !dev->agp_buffer_map->handle) {
+	if (!dev_priv->is_pci) {
+		drm_core_ioremap(dev_priv->cce_ring, dev);
+		drm_core_ioremap(dev_priv->ring_rptr, dev);
+		drm_core_ioremap(dev->agp_buffer_map, dev);
+		if (!dev_priv->cce_ring->handle ||
+		    !dev_priv->ring_rptr->handle ||
+		    !dev->agp_buffer_map->handle) {
 			DRM_ERROR("Could not ioremap agp regions!\n");
 			dev->dev_private = (void *)dev_priv;
-			r128_do_cleanup_cce( dev );
+			r128_do_cleanup_cce(dev);
 			return DRM_ERR(ENOMEM);
 		}
 	} else
 #endif
 	{
-		dev_priv->cce_ring->handle =
-			(void *)dev_priv->cce_ring->offset;
+		dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset;
 		dev_priv->ring_rptr->handle =
-			(void *)dev_priv->ring_rptr->offset;
-		dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;
+		    (void *)dev_priv->ring_rptr->offset;
+		dev->agp_buffer_map->handle =
+		    (void *)dev->agp_buffer_map->offset;
 	}
 
 #if __OS_HAS_AGP
-	if ( !dev_priv->is_pci )
+	if (!dev_priv->is_pci)
 		dev_priv->cce_buffers_offset = dev->agp->base;
 	else
 #endif
 		dev_priv->cce_buffers_offset = dev->sg->handle;
 
-	dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle;
-	dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle
+	dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
+	dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
 			      + init->ring_size / sizeof(u32));
 	dev_priv->ring.size = init->ring_size;
-	dev_priv->ring.size_l2qw = get_order( init->ring_size / 8 );
+	dev_priv->ring.size_l2qw = get_order(init->ring_size / 8);
 
-	dev_priv->ring.tail_mask =
-		(dev_priv->ring.size / sizeof(u32)) - 1;
+	dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
 
 	dev_priv->ring.high_mark = 128;
 
 	dev_priv->sarea_priv->last_frame = 0;
-	R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame );
+	R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 
 	dev_priv->sarea_priv->last_dispatch = 0;
-	R128_WRITE( R128_LAST_DISPATCH_REG,
-		    dev_priv->sarea_priv->last_dispatch );
+	R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
 
 #if __OS_HAS_AGP
-	if ( dev_priv->is_pci ) {
+	if (dev_priv->is_pci) {
 #endif
-		if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart,
-     					    &dev_priv->bus_pci_gart) ) {
-			DRM_ERROR( "failed to init PCI GART!\n" );
+		if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart,
+					  &dev_priv->bus_pci_gart)) {
+			DRM_ERROR("failed to init PCI GART!\n");
 			dev->dev_private = (void *)dev_priv;
-			r128_do_cleanup_cce( dev );
+			r128_do_cleanup_cce(dev);
 			return DRM_ERR(ENOMEM);
 		}
-		R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart );
+		R128_WRITE(R128_PCI_GART_PAGE, dev_priv->bus_pci_gart);
 #if __OS_HAS_AGP
 	}
 #endif
 
-	r128_cce_init_ring_buffer( dev, dev_priv );
-	r128_cce_load_microcode( dev_priv );
+	r128_cce_init_ring_buffer(dev, dev_priv);
+	r128_cce_load_microcode(dev_priv);
 
 	dev->dev_private = (void *)dev_priv;
 
-	r128_do_engine_reset( dev );
+	r128_do_engine_reset(dev);
 
 	return 0;
 }
 
-int r128_do_cleanup_cce( drm_device_t *dev )
+int r128_do_cleanup_cce(drm_device_t * dev)
 {
 
 	/* Make sure interrupts are disabled here because the uninstall ioctl
 	 * may not have been called from userspace and after dev_private
 	 * is freed, it's too late.
 	 */
-	if ( dev->irq_enabled ) drm_irq_uninstall(dev);
+	if (dev->irq_enabled)
+		drm_irq_uninstall(dev);
 
-	if ( dev->dev_private ) {
+	if (dev->dev_private) {
 		drm_r128_private_t *dev_priv = dev->dev_private;
 
 #if __OS_HAS_AGP
-		if ( !dev_priv->is_pci ) {
-			if ( dev_priv->cce_ring != NULL )
-				drm_core_ioremapfree( dev_priv->cce_ring, dev );
-			if ( dev_priv->ring_rptr != NULL )
-				drm_core_ioremapfree( dev_priv->ring_rptr, dev );
-			if ( dev->agp_buffer_map != NULL ) {
-				drm_core_ioremapfree( dev->agp_buffer_map, dev );
+		if (!dev_priv->is_pci) {
+			if (dev_priv->cce_ring != NULL)
+				drm_core_ioremapfree(dev_priv->cce_ring, dev);
+			if (dev_priv->ring_rptr != NULL)
+				drm_core_ioremapfree(dev_priv->ring_rptr, dev);
+			if (dev->agp_buffer_map != NULL) {
+				drm_core_ioremapfree(dev->agp_buffer_map, dev);
 				dev->agp_buffer_map = NULL;
 			}
 		} else
 #endif
 		{
-			if (!drm_ati_pcigart_cleanup( dev,
-						dev_priv->phys_pci_gart,
-						dev_priv->bus_pci_gart ))
-				DRM_ERROR( "failed to cleanup PCI GART!\n" );
+			if (!drm_ati_pcigart_cleanup(dev,
+						     dev_priv->phys_pci_gart,
+						     dev_priv->bus_pci_gart))
+				DRM_ERROR("failed to cleanup PCI GART!\n");
 		}
 
-		drm_free( dev->dev_private, sizeof(drm_r128_private_t),
-			   DRM_MEM_DRIVER );
+		drm_free(dev->dev_private, sizeof(drm_r128_private_t),
+			 DRM_MEM_DRIVER);
 		dev->dev_private = NULL;
 	}
 
 	return 0;
 }
 
-int r128_cce_init( DRM_IOCTL_ARGS )
+int r128_cce_init(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_init_t init;
 
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t __user *)data, sizeof(init) );
+	DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data,
+				 sizeof(init));
 
-	switch ( init.func ) {
+	switch (init.func) {
 	case R128_INIT_CCE:
-		return r128_do_init_cce( dev, &init );
+		return r128_do_init_cce(dev, &init);
 	case R128_CLEANUP_CCE:
-		return r128_do_cleanup_cce( dev );
+		return r128_do_cleanup_cce(dev);
 	}
 
 	return DRM_ERR(EINVAL);
 }
 
-int r128_cce_start( DRM_IOCTL_ARGS )
+int r128_cce_start(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) {
-		DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ );
+	if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
+		DRM_DEBUG("%s while CCE running\n", __FUNCTION__);
 		return 0;
 	}
 
-	r128_do_cce_start( dev_priv );
+	r128_do_cce_start(dev_priv);
 
 	return 0;
 }
@@ -663,61 +661,63 @@ int r128_cce_start( DRM_IOCTL_ARGS )
 /* Stop the CCE.  The engine must have been idled before calling this
  * routine.
  */
-int r128_cce_stop( DRM_IOCTL_ARGS )
+int r128_cce_stop(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_cce_stop_t stop;
 	int ret;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *)data, sizeof(stop) );
+	DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data,
+				 sizeof(stop));
 
 	/* Flush any pending CCE commands.  This ensures any outstanding
 	 * commands are exectuted by the engine before we turn it off.
 	 */
-	if ( stop.flush ) {
-		r128_do_cce_flush( dev_priv );
+	if (stop.flush) {
+		r128_do_cce_flush(dev_priv);
 	}
 
 	/* If we fail to make the engine go idle, we return an error
 	 * code so that the DRM ioctl wrapper can try again.
 	 */
-	if ( stop.idle ) {
-		ret = r128_do_cce_idle( dev_priv );
-		if ( ret ) return ret;
+	if (stop.idle) {
+		ret = r128_do_cce_idle(dev_priv);
+		if (ret)
+			return ret;
 	}
 
 	/* Finally, we can turn off the CCE.  If the engine isn't idle,
 	 * we will get some dropped triangles as they won't be fully
 	 * rendered before the CCE is shut down.
 	 */
-	r128_do_cce_stop( dev_priv );
+	r128_do_cce_stop(dev_priv);
 
 	/* Reset the engine */
-	r128_do_engine_reset( dev );
+	r128_do_engine_reset(dev);
 
 	return 0;
 }
 
 /* Just reset the CCE ring.  Called as part of an X Server engine reset.
  */
-int r128_cce_reset( DRM_IOCTL_ARGS )
+int r128_cce_reset(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_DEBUG("%s called before init done\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	r128_do_cce_reset( dev_priv );
+	r128_do_cce_reset(dev_priv);
 
 	/* The CCE is no longer running after an engine reset */
 	dev_priv->cce_running = 0;
@@ -725,37 +725,36 @@ int r128_cce_reset( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-int r128_cce_idle( DRM_IOCTL_ARGS )
+int r128_cce_idle(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( dev_priv->cce_running ) {
-		r128_do_cce_flush( dev_priv );
+	if (dev_priv->cce_running) {
+		r128_do_cce_flush(dev_priv);
 	}
 
-	return r128_do_cce_idle( dev_priv );
+	return r128_do_cce_idle(dev_priv);
 }
 
-int r128_engine_reset( DRM_IOCTL_ARGS )
+int r128_engine_reset(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	return r128_do_engine_reset( dev );
+	return r128_do_engine_reset(dev);
 }
 
-int r128_fullscreen( DRM_IOCTL_ARGS )
+int r128_fullscreen(DRM_IOCTL_ARGS)
 {
 	return DRM_ERR(EINVAL);
 }
 
-
 /* ================================================================
  * Freelist management
  */
@@ -763,7 +762,7 @@ int r128_fullscreen( DRM_IOCTL_ARGS )
 #define R128_BUFFER_FREE	0
 
 #if 0
-static int r128_freelist_init( drm_device_t *dev )
+static int r128_freelist_init(drm_device_t * dev)
 {
 	drm_device_dma_t *dma = dev->dma;
 	drm_r128_private_t *dev_priv = dev->dev_private;
@@ -772,27 +771,26 @@ static int r128_freelist_init( drm_device_t *dev )
 	drm_r128_freelist_t *entry;
 	int i;
 
-	dev_priv->head = drm_alloc( sizeof(drm_r128_freelist_t),
-				     DRM_MEM_DRIVER );
-	if ( dev_priv->head == NULL )
+	dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
+	if (dev_priv->head == NULL)
 		return DRM_ERR(ENOMEM);
 
-	memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) );
+	memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
 	dev_priv->head->age = R128_BUFFER_USED;
 
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+	for (i = 0; i < dma->buf_count; i++) {
 		buf = dma->buflist[i];
 		buf_priv = buf->dev_private;
 
-		entry = drm_alloc( sizeof(drm_r128_freelist_t),
-				    DRM_MEM_DRIVER );
-		if ( !entry ) return DRM_ERR(ENOMEM);
+		entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
+		if (!entry)
+			return DRM_ERR(ENOMEM);
 
 		entry->age = R128_BUFFER_FREE;
 		entry->buf = buf;
 		entry->prev = dev_priv->head;
 		entry->next = dev_priv->head->next;
-		if ( !entry->next )
+		if (!entry->next)
 			dev_priv->tail = entry;
 
 		buf_priv->discard = 0;
@@ -801,7 +799,7 @@ static int r128_freelist_init( drm_device_t *dev )
 
 		dev_priv->head->next = entry;
 
-		if ( dev_priv->head->next )
+		if (dev_priv->head->next)
 			dev_priv->head->next->prev = entry;
 	}
 
@@ -810,7 +808,7 @@ static int r128_freelist_init( drm_device_t *dev )
 }
 #endif
 
-drm_buf_t *r128_freelist_get( drm_device_t *dev )
+drm_buf_t *r128_freelist_get(drm_device_t * dev)
 {
 	drm_device_dma_t *dma = dev->dma;
 	drm_r128_private_t *dev_priv = dev->dev_private;
@@ -820,20 +818,20 @@ drm_buf_t *r128_freelist_get( drm_device_t *dev )
 
 	/* FIXME: Optimize -- use freelist code */
 
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+	for (i = 0; i < dma->buf_count; i++) {
 		buf = dma->buflist[i];
 		buf_priv = buf->dev_private;
-		if ( buf->filp == 0 )
+		if (buf->filp == 0)
 			return buf;
 	}
 
-	for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
-		u32 done_age = R128_READ( R128_LAST_DISPATCH_REG );
+	for (t = 0; t < dev_priv->usec_timeout; t++) {
+		u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
 
-		for ( i = 0 ; i < dma->buf_count ; i++ ) {
+		for (i = 0; i < dma->buf_count; i++) {
 			buf = dma->buflist[i];
 			buf_priv = buf->dev_private;
-			if ( buf->pending && buf_priv->age <= done_age ) {
+			if (buf->pending && buf_priv->age <= done_age) {
 				/* The buffer has been processed, so it
 				 * can now be used.
 				 */
@@ -841,63 +839,63 @@ drm_buf_t *r128_freelist_get( drm_device_t *dev )
 				return buf;
 			}
 		}
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
-	DRM_DEBUG( "returning NULL!\n" );
+	DRM_DEBUG("returning NULL!\n");
 	return NULL;
 }
 
-void r128_freelist_reset( drm_device_t *dev )
+void r128_freelist_reset(drm_device_t * dev)
 {
 	drm_device_dma_t *dma = dev->dma;
 	int i;
 
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+	for (i = 0; i < dma->buf_count; i++) {
 		drm_buf_t *buf = dma->buflist[i];
 		drm_r128_buf_priv_t *buf_priv = buf->dev_private;
 		buf_priv->age = 0;
 	}
 }
 
-
 /* ================================================================
  * CCE command submission
  */
 
-int r128_wait_ring( drm_r128_private_t *dev_priv, int n )
+int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
 {
 	drm_r128_ring_buffer_t *ring = &dev_priv->ring;
 	int i;
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		r128_update_ring_snapshot( dev_priv );
-		if ( ring->space >= n )
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		r128_update_ring_snapshot(dev_priv);
+		if (ring->space >= n)
 			return 0;
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
 	/* FIXME: This is being ignored... */
-	DRM_ERROR( "failed!\n" );
+	DRM_ERROR("failed!\n");
 	return DRM_ERR(EBUSY);
 }
 
-static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
+static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
 {
 	int i;
 	drm_buf_t *buf;
 
-	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
-		buf = r128_freelist_get( dev );
-		if ( !buf ) return DRM_ERR(EAGAIN);
+	for (i = d->granted_count; i < d->request_count; i++) {
+		buf = r128_freelist_get(dev);
+		if (!buf)
+			return DRM_ERR(EAGAIN);
 
 		buf->filp = filp;
 
-		if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
-				   sizeof(buf->idx) ) )
+		if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
+				     sizeof(buf->idx)))
 			return DRM_ERR(EFAULT);
-		if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
-				   sizeof(buf->total) ) )
+		if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
+				     sizeof(buf->total)))
 			return DRM_ERR(EFAULT);
 
 		d->granted_count++;
@@ -905,7 +903,7 @@ static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
 	return 0;
 }
 
-int r128_cce_buffers( DRM_IOCTL_ARGS )
+int r128_cce_buffers(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_device_dma_t *dma = dev->dma;
@@ -913,33 +911,33 @@ int r128_cce_buffers( DRM_IOCTL_ARGS )
 	drm_dma_t __user *argp = (void __user *)data;
 	drm_dma_t d;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
+	DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
 
 	/* Please don't send us buffers.
 	 */
-	if ( d.send_count != 0 ) {
-		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
-			   DRM_CURRENTPID, d.send_count );
+	if (d.send_count != 0) {
+		DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
+			  DRM_CURRENTPID, d.send_count);
 		return DRM_ERR(EINVAL);
 	}
 
 	/* We'll send you buffers.
 	 */
-	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
-		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
-			   DRM_CURRENTPID, d.request_count, dma->buf_count );
+	if (d.request_count < 0 || d.request_count > dma->buf_count) {
+		DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
+			  DRM_CURRENTPID, d.request_count, dma->buf_count);
 		return DRM_ERR(EINVAL);
 	}
 
 	d.granted_count = 0;
 
-	if ( d.request_count ) {
-		ret = r128_cce_get_buffers( filp, dev, &d );
+	if (d.request_count) {
+		ret = r128_cce_get_buffers(filp, dev, &d);
 	}
 
-	DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d) );
+	DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
 
 	return ret;
 }
diff --git a/shared-core/r128_drm.h b/shared-core/r128_drm.h
index 0cba17d1..607836ab 100644
--- a/shared-core/r128_drm.h
+++ b/shared-core/r128_drm.h
@@ -93,7 +93,7 @@
 #define R128_MAX_TEXTURE_LEVELS		11
 #define R128_MAX_TEXTURE_UNITS		2
 
-#endif /* __R128_SAREA_DEFINES__ */
+#endif				/* __R128_SAREA_DEFINES__ */
 
 typedef struct {
 	/* Context state - can be written in one large chunk */
@@ -140,7 +140,6 @@ typedef struct {
 	unsigned int tex_border_color;
 } drm_r128_texture_regs_t;
 
-
 typedef struct drm_r128_sarea {
 	/* The channel for communication of state information to the kernel
 	 * on firing a vertex buffer.
@@ -161,14 +160,13 @@ typedef struct drm_r128_sarea {
 	unsigned int last_frame;
 	unsigned int last_dispatch;
 
-	drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1];
+	drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
 	unsigned int tex_age[R128_NR_TEX_HEAPS];
 	int ctx_owner;
-	int pfAllowPageFlip;        /* number of 3d windows (0,1,2 or more) */
-	int pfCurrentPage;	    /* which buffer is being displayed? */
+	int pfAllowPageFlip;	/* number of 3d windows (0,1,2 or more) */
+	int pfCurrentPage;	/* which buffer is being displayed? */
 } drm_r128_sarea_t;
 
-
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (xf86drmR128.h)
  */
@@ -220,7 +218,7 @@ typedef struct drm_r128_sarea {
 
 typedef struct drm_r128_init {
 	enum {
-		R128_INIT_CCE    = 0x01,
+		R128_INIT_CCE = 0x01,
 		R128_CLEANUP_CCE = 0x02
 	} func;
 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
@@ -278,9 +276,9 @@ typedef struct drm_r128_clear {
 
 typedef struct drm_r128_vertex {
 	int prim;
-	int idx;			/* Index of vertex buffer */
-	int count;			/* Number of vertices in buffer */
-	int discard;			/* Client finished with buffer? */
+	int idx;		/* Index of vertex buffer */
+	int count;		/* Number of vertices in buffer */
+	int discard;		/* Client finished with buffer? */
 } drm_r128_vertex_t;
 
 typedef struct drm_r128_indices {
@@ -288,7 +286,7 @@ typedef struct drm_r128_indices {
 	int idx;
 	int start;
 	int end;
-	int discard;			/* Client finished with buffer? */
+	int discard;		/* Client finished with buffer? */
 } drm_r128_indices_t;
 
 typedef struct drm_r128_blit {
@@ -302,10 +300,10 @@ typedef struct drm_r128_blit {
 
 typedef struct drm_r128_depth {
 	enum {
-		R128_WRITE_SPAN		= 0x01,
-		R128_WRITE_PIXELS	= 0x02,
-		R128_READ_SPAN		= 0x03,
-		R128_READ_PIXELS	= 0x04
+		R128_WRITE_SPAN = 0x01,
+		R128_WRITE_PIXELS = 0x02,
+		R128_READ_SPAN = 0x03,
+		R128_READ_PIXELS = 0x04
 	} func;
 	int n;
 	int __user *x;
@@ -327,13 +325,13 @@ typedef struct drm_r128_indirect {
 
 typedef struct drm_r128_fullscreen {
 	enum {
-		R128_INIT_FULLSCREEN    = 0x01,
+		R128_INIT_FULLSCREEN = 0x01,
 		R128_CLEANUP_FULLSCREEN = 0x02
 	} func;
 } drm_r128_fullscreen_t;
 
 /* 2.3: An ioctl to get parameters that aren't available to the 3d
- * client any other way.  
+ * client any other way.
  */
 #define R128_PARAM_IRQ_NR            1
 
diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h
index 9cec2f3e..ed259498 100644
--- a/shared-core/r128_drv.h
+++ b/shared-core/r128_drv.h
@@ -46,14 +46,13 @@
 #define DRIVER_MINOR		5
 #define DRIVER_PATCHLEVEL	0
 
-
 #define GET_RING_HEAD(dev_priv)		R128_READ( R128_PM4_BUFFER_DL_RPTR )
 
 typedef struct drm_r128_freelist {
-   	unsigned int age;
-   	drm_buf_t *buf;
-   	struct drm_r128_freelist *next;
-   	struct drm_r128_freelist *prev;
+	unsigned int age;
+	drm_buf_t *buf;
+	struct drm_r128_freelist *next;
+	struct drm_r128_freelist *prev;
 } drm_r128_freelist_t;
 
 typedef struct drm_r128_ring_buffer {
@@ -77,8 +76,8 @@ typedef struct drm_r128_private {
 	int cce_fifo_size;
 	int cce_running;
 
-   	drm_r128_freelist_t *head;
-   	drm_r128_freelist_t *tail;
+	drm_r128_freelist_t *head;
+	drm_r128_freelist_t *tail;
 
 	int usec_timeout;
 	int is_pci;
@@ -121,48 +120,48 @@ typedef struct drm_r128_buf_priv {
 	int prim;
 	int discard;
 	int dispatched;
-   	drm_r128_freelist_t *list_entry;
+	drm_r128_freelist_t *list_entry;
 } drm_r128_buf_priv_t;
 
 				/* r128_cce.c */
-extern int r128_cce_init( DRM_IOCTL_ARGS );
-extern int r128_cce_start( DRM_IOCTL_ARGS );
-extern int r128_cce_stop( DRM_IOCTL_ARGS );
-extern int r128_cce_reset( DRM_IOCTL_ARGS );
-extern int r128_cce_idle( DRM_IOCTL_ARGS );
-extern int r128_engine_reset( DRM_IOCTL_ARGS );
-extern int r128_fullscreen( DRM_IOCTL_ARGS );
-extern int r128_cce_buffers( DRM_IOCTL_ARGS );
-extern int r128_getparam( DRM_IOCTL_ARGS );
+extern int r128_cce_init(DRM_IOCTL_ARGS);
+extern int r128_cce_start(DRM_IOCTL_ARGS);
+extern int r128_cce_stop(DRM_IOCTL_ARGS);
+extern int r128_cce_reset(DRM_IOCTL_ARGS);
+extern int r128_cce_idle(DRM_IOCTL_ARGS);
+extern int r128_engine_reset(DRM_IOCTL_ARGS);
+extern int r128_fullscreen(DRM_IOCTL_ARGS);
+extern int r128_cce_buffers(DRM_IOCTL_ARGS);
+extern int r128_getparam(DRM_IOCTL_ARGS);
 
-extern void r128_freelist_reset( drm_device_t *dev );
-extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
+extern void r128_freelist_reset(drm_device_t * dev);
+extern drm_buf_t *r128_freelist_get(drm_device_t * dev);
 
-extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
+extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n);
 
-extern int r128_do_cce_idle( drm_r128_private_t *dev_priv );
-extern int r128_do_cleanup_cce( drm_device_t *dev );
-extern int r128_do_cleanup_pageflip( drm_device_t *dev );
+extern int r128_do_cce_idle(drm_r128_private_t * dev_priv);
+extern int r128_do_cleanup_cce(drm_device_t * dev);
+extern int r128_do_cleanup_pageflip(drm_device_t * dev);
 
 				/* r128_state.c */
-extern int r128_cce_clear( DRM_IOCTL_ARGS );
-extern int r128_cce_swap( DRM_IOCTL_ARGS );
-extern int r128_cce_flip( DRM_IOCTL_ARGS );
-extern int r128_cce_vertex( DRM_IOCTL_ARGS );
-extern int r128_cce_indices( DRM_IOCTL_ARGS );
-extern int r128_cce_blit( DRM_IOCTL_ARGS );
-extern int r128_cce_depth( DRM_IOCTL_ARGS );
-extern int r128_cce_stipple( DRM_IOCTL_ARGS );
-extern int r128_cce_indirect( DRM_IOCTL_ARGS );
-
-extern int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
-
-extern irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS );
-extern void r128_driver_irq_preinstall( drm_device_t *dev );
-extern void r128_driver_irq_postinstall( drm_device_t *dev );
-extern void r128_driver_irq_uninstall( drm_device_t *dev );
-extern void r128_driver_pretakedown(drm_device_t *dev);
-extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp);
+extern int r128_cce_clear(DRM_IOCTL_ARGS);
+extern int r128_cce_swap(DRM_IOCTL_ARGS);
+extern int r128_cce_flip(DRM_IOCTL_ARGS);
+extern int r128_cce_vertex(DRM_IOCTL_ARGS);
+extern int r128_cce_indices(DRM_IOCTL_ARGS);
+extern int r128_cce_blit(DRM_IOCTL_ARGS);
+extern int r128_cce_depth(DRM_IOCTL_ARGS);
+extern int r128_cce_stipple(DRM_IOCTL_ARGS);
+extern int r128_cce_indirect(DRM_IOCTL_ARGS);
+
+extern int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence);
+
+extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS);
+extern void r128_driver_irq_preinstall(drm_device_t * dev);
+extern void r128_driver_irq_postinstall(drm_device_t * dev);
+extern void r128_driver_irq_uninstall(drm_device_t * dev);
+extern void r128_driver_pretakedown(drm_device_t * dev);
+extern void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp);
 
 /* Register definitions, register access macros and drmAddMap constants
  * for Rage 128 kernel driver.
@@ -271,7 +270,6 @@ extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp);
 #	define R128_EVENT_CRTC_OFFSET		(1 << 0)
 #define R128_WINDOW_XY_OFFSET		0x1bcc
 
-
 /* CCE registers
  */
 #define R128_PM4_BUFFER_OFFSET		0x0700
@@ -322,7 +320,6 @@ extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp);
 #define R128_PM4_FIFO_DATA_EVEN		0x1000
 #define R128_PM4_FIFO_DATA_ODD		0x1004
 
-
 /* CCE command packets
  */
 #define R128_CCE_PACKET0		0x00000000
@@ -400,8 +397,7 @@ do {									\
 	R128_WRITE(R128_CLOCK_CNTL_DATA, (val));			\
 } while (0)
 
-extern int R128_READ_PLL(drm_device_t *dev, int addr);
-
+extern int R128_READ_PLL(drm_device_t * dev, int addr);
 
 #define CCE_PACKET0( reg, n )		(R128_CCE_PACKET0 |		\
 					 ((n) << 16) | ((reg) >> 2))
@@ -411,13 +407,11 @@ extern int R128_READ_PLL(drm_device_t *dev, int addr);
 #define CCE_PACKET3( pkt, n )		(R128_CCE_PACKET3 |		\
 					 (pkt) | ((n) << 16))
 
-
-static __inline__ void
-r128_update_ring_snapshot( drm_r128_private_t *dev_priv )
+static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv)
 {
 	drm_r128_ring_buffer_t *ring = &dev_priv->ring;
-	ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32);
-	if ( ring->space <= 0 )
+	ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32);
+	if (ring->space <= 0)
 		ring->space += ring->size;
 }
 
@@ -458,7 +452,6 @@ do {									\
 	OUT_RING( R128_EVENT_CRTC_OFFSET );				\
 } while (0)
 
-
 /* ================================================================
  * Ring control
  */
@@ -528,4 +521,4 @@ do {									\
 	write &= tail_mask;						\
 } while (0)
 
-#endif /* __R128_DRV_H__ */
+#endif				/* __R128_DRV_H__ */
diff --git a/shared-core/r128_irq.c b/shared-core/r128_irq.c
index 643a3078..27eb0e31 100644
--- a/shared-core/r128_irq.c
+++ b/shared-core/r128_irq.c
@@ -1,7 +1,7 @@
 /* r128_irq.c -- IRQ handling for radeon -*- linux-c -*-
  *
  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
- * 
+ *
  * The Weather Channel (TM) funded Tungsten Graphics to develop the
  * initial release of the Radeon 8500 driver under the XFree86 license.
  * This notice must be preserved.
@@ -35,68 +35,67 @@
 #include "r128_drm.h"
 #include "r128_drv.h"
 
-irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS )
+irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS)
 {
 	drm_device_t *dev = (drm_device_t *) arg;
-	drm_r128_private_t *dev_priv = 
-	   (drm_r128_private_t *)dev->dev_private;
+	drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
 	int status;
 
-	status = R128_READ( R128_GEN_INT_STATUS );
-	
+	status = R128_READ(R128_GEN_INT_STATUS);
+
 	/* VBLANK interrupt */
-	if ( status & R128_CRTC_VBLANK_INT ) {
-		R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK );
+	if (status & R128_CRTC_VBLANK_INT) {
+		R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
 		atomic_inc(&dev->vbl_received);
 		DRM_WAKEUP(&dev->vbl_queue);
-		drm_vbl_send_signals( dev );
+		drm_vbl_send_signals(dev);
 		return IRQ_HANDLED;
 	}
 	return IRQ_NONE;
 }
 
-int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
+int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
 {
 	unsigned int cur_vblank;
 	int ret = 0;
 
 	/* Assume that the user has missed the current sequence number
 	 * by about a day rather than she wants to wait for years
-	 * using vertical blanks... 
+	 * using vertical blanks...
 	 */
-	DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, 
-		     ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
-			 - *sequence ) <= (1<<23) ) );
+	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
+		    (((cur_vblank = atomic_read(&dev->vbl_received))
+		      - *sequence) <= (1 << 23)));
 
 	*sequence = cur_vblank;
 
 	return ret;
 }
 
-void r128_driver_irq_preinstall( drm_device_t *dev ) {
-  	drm_r128_private_t *dev_priv = 
-	   (drm_r128_private_t *)dev->dev_private;
+void r128_driver_irq_preinstall(drm_device_t * dev)
+{
+	drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
 
 	/* Disable *all* interrupts */
-      	R128_WRITE( R128_GEN_INT_CNTL, 0 );
+	R128_WRITE(R128_GEN_INT_CNTL, 0);
 	/* Clear vblank bit if it's already high */
-   	R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK );
+	R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
 }
 
-void r128_driver_irq_postinstall( drm_device_t *dev ) {
-  	drm_r128_private_t *dev_priv = 
-	   (drm_r128_private_t *)dev->dev_private;
+void r128_driver_irq_postinstall(drm_device_t * dev)
+{
+	drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
 
 	/* Turn on VBL interrupt */
-   	R128_WRITE( R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN );
+	R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN);
 }
 
-void r128_driver_irq_uninstall( drm_device_t *dev ) {
-  	drm_r128_private_t *dev_priv = 
-	   (drm_r128_private_t *)dev->dev_private;
+void r128_driver_irq_uninstall(drm_device_t * dev)
+{
+	drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
 	if (!dev_priv)
 		return;
 
 	/* Disable *all* interrupts */
-	R128_WRITE( R128_GEN_INT_CNTL, 0 );
+	R128_WRITE(R128_GEN_INT_CNTL, 0);
 }
diff --git a/shared-core/r128_state.c b/shared-core/r128_state.c
index ed643682..155fe936 100644
--- a/shared-core/r128_state.c
+++ b/shared-core/r128_state.c
@@ -32,235 +32,233 @@
 #include "r128_drm.h"
 #include "r128_drv.h"
 
-
 /* ================================================================
  * CCE hardware state programming functions
  */
 
-static void r128_emit_clip_rects( drm_r128_private_t *dev_priv,
-				  drm_clip_rect_t *boxes, int count )
+static void r128_emit_clip_rects(drm_r128_private_t * dev_priv,
+				 drm_clip_rect_t * boxes, int count)
 {
 	u32 aux_sc_cntl = 0x00000000;
 	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+	DRM_DEBUG("    %s\n", __FUNCTION__);
 
-	BEGIN_RING( (count < 3? count: 3) * 5 + 2 );
+	BEGIN_RING((count < 3 ? count : 3) * 5 + 2);
 
-	if ( count >= 1 ) {
-		OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) );
-		OUT_RING( boxes[0].x1 );
-		OUT_RING( boxes[0].x2 - 1 );
-		OUT_RING( boxes[0].y1 );
-		OUT_RING( boxes[0].y2 - 1 );
+	if (count >= 1) {
+		OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
+		OUT_RING(boxes[0].x1);
+		OUT_RING(boxes[0].x2 - 1);
+		OUT_RING(boxes[0].y1);
+		OUT_RING(boxes[0].y2 - 1);
 
 		aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
 	}
-	if ( count >= 2 ) {
-		OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) );
-		OUT_RING( boxes[1].x1 );
-		OUT_RING( boxes[1].x2 - 1 );
-		OUT_RING( boxes[1].y1 );
-		OUT_RING( boxes[1].y2 - 1 );
+	if (count >= 2) {
+		OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
+		OUT_RING(boxes[1].x1);
+		OUT_RING(boxes[1].x2 - 1);
+		OUT_RING(boxes[1].y1);
+		OUT_RING(boxes[1].y2 - 1);
 
 		aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
 	}
-	if ( count >= 3 ) {
-		OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) );
-		OUT_RING( boxes[2].x1 );
-		OUT_RING( boxes[2].x2 - 1 );
-		OUT_RING( boxes[2].y1 );
-		OUT_RING( boxes[2].y2 - 1 );
+	if (count >= 3) {
+		OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3));
+		OUT_RING(boxes[2].x1);
+		OUT_RING(boxes[2].x2 - 1);
+		OUT_RING(boxes[2].y1);
+		OUT_RING(boxes[2].y2 - 1);
 
 		aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
 	}
 
-	OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) );
-	OUT_RING( aux_sc_cntl );
+	OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0));
+	OUT_RING(aux_sc_cntl);
 
 	ADVANCE_RING();
 }
 
-static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv )
+static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv)
 {
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+	DRM_DEBUG("    %s\n", __FUNCTION__);
 
-	BEGIN_RING( 2 );
+	BEGIN_RING(2);
 
-	OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) );
-	OUT_RING( ctx->scale_3d_cntl );
+	OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0));
+	OUT_RING(ctx->scale_3d_cntl);
 
 	ADVANCE_RING();
 }
 
-static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv )
+static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv)
 {
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 13 );
-
-	OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) );
-	OUT_RING( ctx->dst_pitch_offset_c );
-	OUT_RING( ctx->dp_gui_master_cntl_c );
-	OUT_RING( ctx->sc_top_left_c );
-	OUT_RING( ctx->sc_bottom_right_c );
-	OUT_RING( ctx->z_offset_c );
-	OUT_RING( ctx->z_pitch_c );
-	OUT_RING( ctx->z_sten_cntl_c );
-	OUT_RING( ctx->tex_cntl_c );
-	OUT_RING( ctx->misc_3d_state_cntl_reg );
-	OUT_RING( ctx->texture_clr_cmp_clr_c );
-	OUT_RING( ctx->texture_clr_cmp_msk_c );
-	OUT_RING( ctx->fog_color_c );
+	DRM_DEBUG("    %s\n", __FUNCTION__);
+
+	BEGIN_RING(13);
+
+	OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11));
+	OUT_RING(ctx->dst_pitch_offset_c);
+	OUT_RING(ctx->dp_gui_master_cntl_c);
+	OUT_RING(ctx->sc_top_left_c);
+	OUT_RING(ctx->sc_bottom_right_c);
+	OUT_RING(ctx->z_offset_c);
+	OUT_RING(ctx->z_pitch_c);
+	OUT_RING(ctx->z_sten_cntl_c);
+	OUT_RING(ctx->tex_cntl_c);
+	OUT_RING(ctx->misc_3d_state_cntl_reg);
+	OUT_RING(ctx->texture_clr_cmp_clr_c);
+	OUT_RING(ctx->texture_clr_cmp_msk_c);
+	OUT_RING(ctx->fog_color_c);
 
 	ADVANCE_RING();
 }
 
-static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv )
+static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv)
 {
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+	DRM_DEBUG("    %s\n", __FUNCTION__);
 
-	BEGIN_RING( 3 );
+	BEGIN_RING(3);
 
-	OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) );
-	OUT_RING( ctx->setup_cntl );
-	OUT_RING( ctx->pm4_vc_fpu_setup );
+	OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP));
+	OUT_RING(ctx->setup_cntl);
+	OUT_RING(ctx->pm4_vc_fpu_setup);
 
 	ADVANCE_RING();
 }
 
-static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv )
+static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv)
 {
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+	DRM_DEBUG("    %s\n", __FUNCTION__);
 
-	BEGIN_RING( 5 );
+	BEGIN_RING(5);
 
-	OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
-	OUT_RING( ctx->dp_write_mask );
+	OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
+	OUT_RING(ctx->dp_write_mask);
 
-	OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) );
-	OUT_RING( ctx->sten_ref_mask_c );
-	OUT_RING( ctx->plane_3d_mask_c );
+	OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1));
+	OUT_RING(ctx->sten_ref_mask_c);
+	OUT_RING(ctx->plane_3d_mask_c);
 
 	ADVANCE_RING();
 }
 
-static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv )
+static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv)
 {
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+	DRM_DEBUG("    %s\n", __FUNCTION__);
 
-	BEGIN_RING( 2 );
+	BEGIN_RING(2);
 
-	OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) );
-	OUT_RING( ctx->window_xy_offset );
+	OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0));
+	OUT_RING(ctx->window_xy_offset);
 
 	ADVANCE_RING();
 }
 
-static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv )
+static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv)
 {
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 	drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
 	int i;
 	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+	DRM_DEBUG("    %s\n", __FUNCTION__);
 
-	BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS );
+	BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS);
 
-	OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C,
-			       2 + R128_MAX_TEXTURE_LEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	OUT_RING( ctx->tex_size_pitch_c );
-	for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
+	OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C,
+			     2 + R128_MAX_TEXTURE_LEVELS));
+	OUT_RING(tex->tex_cntl);
+	OUT_RING(tex->tex_combine_cntl);
+	OUT_RING(ctx->tex_size_pitch_c);
+	for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
+		OUT_RING(tex->tex_offset[i]);
 	}
 
-	OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) );
-	OUT_RING( ctx->constant_color_c );
-	OUT_RING( tex->tex_border_color );
+	OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1));
+	OUT_RING(ctx->constant_color_c);
+	OUT_RING(tex->tex_border_color);
 
 	ADVANCE_RING();
 }
 
-static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv )
+static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv)
 {
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
 	int i;
 	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
+	DRM_DEBUG("    %s\n", __FUNCTION__);
 
-	BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS );
+	BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS);
 
-	OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C,
-			       1 + R128_MAX_TEXTURE_LEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
+	OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS));
+	OUT_RING(tex->tex_cntl);
+	OUT_RING(tex->tex_combine_cntl);
+	for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
+		OUT_RING(tex->tex_offset[i]);
 	}
 
-	OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
-	OUT_RING( tex->tex_border_color );
+	OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0));
+	OUT_RING(tex->tex_border_color);
 
 	ADVANCE_RING();
 }
 
-static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv )
+static __inline__ void r128_emit_state(drm_r128_private_t * dev_priv)
 {
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	unsigned int dirty = sarea_priv->dirty;
 
-	DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
+	DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty);
 
-	if ( dirty & R128_UPLOAD_CORE ) {
-		r128_emit_core( dev_priv );
+	if (dirty & R128_UPLOAD_CORE) {
+		r128_emit_core(dev_priv);
 		sarea_priv->dirty &= ~R128_UPLOAD_CORE;
 	}
 
-	if ( dirty & R128_UPLOAD_CONTEXT ) {
-		r128_emit_context( dev_priv );
+	if (dirty & R128_UPLOAD_CONTEXT) {
+		r128_emit_context(dev_priv);
 		sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
 	}
 
-	if ( dirty & R128_UPLOAD_SETUP ) {
-		r128_emit_setup( dev_priv );
+	if (dirty & R128_UPLOAD_SETUP) {
+		r128_emit_setup(dev_priv);
 		sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
 	}
 
-	if ( dirty & R128_UPLOAD_MASKS ) {
-		r128_emit_masks( dev_priv );
+	if (dirty & R128_UPLOAD_MASKS) {
+		r128_emit_masks(dev_priv);
 		sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
 	}
 
-	if ( dirty & R128_UPLOAD_WINDOW ) {
-		r128_emit_window( dev_priv );
+	if (dirty & R128_UPLOAD_WINDOW) {
+		r128_emit_window(dev_priv);
 		sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
 	}
 
-	if ( dirty & R128_UPLOAD_TEX0 ) {
-		r128_emit_tex0( dev_priv );
+	if (dirty & R128_UPLOAD_TEX0) {
+		r128_emit_tex0(dev_priv);
 		sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
 	}
 
-	if ( dirty & R128_UPLOAD_TEX1 ) {
-		r128_emit_tex1( dev_priv );
+	if (dirty & R128_UPLOAD_TEX1) {
+		r128_emit_tex1(dev_priv);
 		sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
 	}
 
@@ -270,26 +268,23 @@ static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv )
 	sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
 }
 
-
 #if R128_PERFORMANCE_BOXES
 /* ================================================================
  * Performance monitoring functions
  */
 
-static void r128_clear_box( drm_r128_private_t *dev_priv,
-			    int x, int y, int w, int h,
-			    int r, int g, int b )
+static void r128_clear_box(drm_r128_private_t * dev_priv,
+			   int x, int y, int w, int h, int r, int g, int b)
 {
 	u32 pitch, offset;
 	u32 fb_bpp, color;
 	RING_LOCALS;
 
-	switch ( dev_priv->fb_bpp ) {
+	switch (dev_priv->fb_bpp) {
 	case 16:
 		fb_bpp = R128_GMC_DST_16BPP;
 		color = (((r & 0xf8) << 8) |
-			 ((g & 0xfc) << 3) |
-			 ((b & 0xf8) >> 3));
+			 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
 		break;
 	case 24:
 		fb_bpp = R128_GMC_DST_24BPP;
@@ -297,7 +292,7 @@ static void r128_clear_box( drm_r128_private_t *dev_priv,
 		break;
 	case 32:
 		fb_bpp = R128_GMC_DST_32BPP;
-		color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
+		color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
 		break;
 	default:
 		return;
@@ -306,60 +301,58 @@ static void r128_clear_box( drm_r128_private_t *dev_priv,
 	offset = dev_priv->back_offset;
 	pitch = dev_priv->back_pitch >> 3;
 
-	BEGIN_RING( 6 );
+	BEGIN_RING(6);
 
-	OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-	OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-		  R128_GMC_BRUSH_SOLID_COLOR |
-		  fb_bpp |
-		  R128_GMC_SRC_DATATYPE_COLOR |
-		  R128_ROP3_P |
-		  R128_GMC_CLR_CMP_CNTL_DIS |
-		  R128_GMC_AUX_CLIP_DIS );
+	OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
+	OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
+		 R128_GMC_BRUSH_SOLID_COLOR |
+		 fb_bpp |
+		 R128_GMC_SRC_DATATYPE_COLOR |
+		 R128_ROP3_P |
+		 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS);
 
-	OUT_RING( (pitch << 21) | (offset >> 5) );
-	OUT_RING( color );
+	OUT_RING((pitch << 21) | (offset >> 5));
+	OUT_RING(color);
 
-	OUT_RING( (x << 16) | y );
-	OUT_RING( (w << 16) | h );
+	OUT_RING((x << 16) | y);
+	OUT_RING((w << 16) | h);
 
 	ADVANCE_RING();
 }
 
-static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv )
+static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv)
 {
-	if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
-		r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
+	if (atomic_read(&dev_priv->idle_count) == 0) {
+		r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
 	} else {
-		atomic_set( &dev_priv->idle_count, 0 );
+		atomic_set(&dev_priv->idle_count, 0);
 	}
 }
 
 #endif
 
-
 /* ================================================================
  * CCE command dispatch functions
  */
 
-static void r128_print_dirty( const char *msg, unsigned int flags )
+static void r128_print_dirty(const char *msg, unsigned int flags)
 {
-	DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
-		  msg,
-		  flags,
-		  (flags & R128_UPLOAD_CORE)        ? "core, " : "",
-		  (flags & R128_UPLOAD_CONTEXT)     ? "context, " : "",
-		  (flags & R128_UPLOAD_SETUP)       ? "setup, " : "",
-		  (flags & R128_UPLOAD_TEX0)        ? "tex0, " : "",
-		  (flags & R128_UPLOAD_TEX1)        ? "tex1, " : "",
-		  (flags & R128_UPLOAD_MASKS)       ? "masks, " : "",
-		  (flags & R128_UPLOAD_WINDOW)      ? "window, " : "",
-		  (flags & R128_UPLOAD_CLIPRECTS)   ? "cliprects, " : "",
-		  (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" );
+	DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
+		 msg,
+		 flags,
+		 (flags & R128_UPLOAD_CORE) ? "core, " : "",
+		 (flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
+		 (flags & R128_UPLOAD_SETUP) ? "setup, " : "",
+		 (flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
+		 (flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
+		 (flags & R128_UPLOAD_MASKS) ? "masks, " : "",
+		 (flags & R128_UPLOAD_WINDOW) ? "window, " : "",
+		 (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
+		 (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "");
 }
 
-static void r128_cce_dispatch_clear( drm_device_t *dev,
-				     drm_r128_clear_t *clear )
+static void r128_cce_dispatch_clear(drm_device_t * dev,
+				    drm_r128_clear_t * clear)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -368,102 +361,103 @@ static void r128_cce_dispatch_clear( drm_device_t *dev,
 	unsigned int flags = clear->flags;
 	int i;
 	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
+	if (dev_priv->page_flipping && dev_priv->current_page == 1) {
 		unsigned int tmp = flags;
 
 		flags &= ~(R128_FRONT | R128_BACK);
-		if ( tmp & R128_FRONT ) flags |= R128_BACK;
-		if ( tmp & R128_BACK )  flags |= R128_FRONT;
+		if (tmp & R128_FRONT)
+			flags |= R128_BACK;
+		if (tmp & R128_BACK)
+			flags |= R128_FRONT;
 	}
 
-	for ( i = 0 ; i < nbox ; i++ ) {
+	for (i = 0; i < nbox; i++) {
 		int x = pbox[i].x1;
 		int y = pbox[i].y1;
 		int w = pbox[i].x2 - x;
 		int h = pbox[i].y2 - y;
 
-		DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
-			   pbox[i].x1, pbox[i].y1, pbox[i].x2,
-			   pbox[i].y2, flags );
+		DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
+			  pbox[i].x1, pbox[i].y1, pbox[i].x2,
+			  pbox[i].y2, flags);
 
-		if ( flags & (R128_FRONT | R128_BACK) ) {
-			BEGIN_RING( 2 );
+		if (flags & (R128_FRONT | R128_BACK)) {
+			BEGIN_RING(2);
 
-			OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
-			OUT_RING( clear->color_mask );
+			OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
+			OUT_RING(clear->color_mask);
 
 			ADVANCE_RING();
 		}
 
-		if ( flags & R128_FRONT ) {
-			BEGIN_RING( 6 );
+		if (flags & R128_FRONT) {
+			BEGIN_RING(6);
 
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->color_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_AUX_CLIP_DIS );
+			OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
+			OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
+				 R128_GMC_BRUSH_SOLID_COLOR |
+				 (dev_priv->color_fmt << 8) |
+				 R128_GMC_SRC_DATATYPE_COLOR |
+				 R128_ROP3_P |
+				 R128_GMC_CLR_CMP_CNTL_DIS |
+				 R128_GMC_AUX_CLIP_DIS);
 
-			OUT_RING( dev_priv->front_pitch_offset_c );
-			OUT_RING( clear->clear_color );
+			OUT_RING(dev_priv->front_pitch_offset_c);
+			OUT_RING(clear->clear_color);
 
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
+			OUT_RING((x << 16) | y);
+			OUT_RING((w << 16) | h);
 
 			ADVANCE_RING();
 		}
 
-		if ( flags & R128_BACK ) {
-			BEGIN_RING( 6 );
+		if (flags & R128_BACK) {
+			BEGIN_RING(6);
 
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->color_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_AUX_CLIP_DIS );
+			OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
+			OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
+				 R128_GMC_BRUSH_SOLID_COLOR |
+				 (dev_priv->color_fmt << 8) |
+				 R128_GMC_SRC_DATATYPE_COLOR |
+				 R128_ROP3_P |
+				 R128_GMC_CLR_CMP_CNTL_DIS |
+				 R128_GMC_AUX_CLIP_DIS);
 
-			OUT_RING( dev_priv->back_pitch_offset_c );
-			OUT_RING( clear->clear_color );
+			OUT_RING(dev_priv->back_pitch_offset_c);
+			OUT_RING(clear->clear_color);
 
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
+			OUT_RING((x << 16) | y);
+			OUT_RING((w << 16) | h);
 
 			ADVANCE_RING();
 		}
 
-		if ( flags & R128_DEPTH ) {
-			BEGIN_RING( 6 );
+		if (flags & R128_DEPTH) {
+			BEGIN_RING(6);
 
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->depth_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_AUX_CLIP_DIS |
-				  R128_GMC_WR_MSK_DIS );
+			OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
+			OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
+				 R128_GMC_BRUSH_SOLID_COLOR |
+				 (dev_priv->depth_fmt << 8) |
+				 R128_GMC_SRC_DATATYPE_COLOR |
+				 R128_ROP3_P |
+				 R128_GMC_CLR_CMP_CNTL_DIS |
+				 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
 
-			OUT_RING( dev_priv->depth_pitch_offset_c );
-			OUT_RING( clear->clear_depth );
+			OUT_RING(dev_priv->depth_pitch_offset_c);
+			OUT_RING(clear->clear_depth);
 
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
+			OUT_RING((x << 16) | y);
+			OUT_RING((w << 16) | h);
 
 			ADVANCE_RING();
 		}
 	}
 }
 
-static void r128_cce_dispatch_swap( drm_device_t *dev )
+static void r128_cce_dispatch_swap(drm_device_t * dev)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -471,48 +465,46 @@ static void r128_cce_dispatch_swap( drm_device_t *dev )
 	drm_clip_rect_t *pbox = sarea_priv->boxes;
 	int i;
 	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
 #if R128_PERFORMANCE_BOXES
 	/* Do some trivial performance monitoring...
 	 */
-	r128_cce_performance_boxes( dev_priv );
+	r128_cce_performance_boxes(dev_priv);
 #endif
 
-	for ( i = 0 ; i < nbox ; i++ ) {
+	for (i = 0; i < nbox; i++) {
 		int x = pbox[i].x1;
 		int y = pbox[i].y1;
 		int w = pbox[i].x2 - x;
 		int h = pbox[i].y2 - y;
 
-		BEGIN_RING( 7 );
+		BEGIN_RING(7);
 
-		OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
-		OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
-			  R128_GMC_DST_PITCH_OFFSET_CNTL |
-			  R128_GMC_BRUSH_NONE |
-			  (dev_priv->color_fmt << 8) |
-			  R128_GMC_SRC_DATATYPE_COLOR |
-			  R128_ROP3_S |
-			  R128_DP_SRC_SOURCE_MEMORY |
-			  R128_GMC_CLR_CMP_CNTL_DIS |
-			  R128_GMC_AUX_CLIP_DIS |
-			  R128_GMC_WR_MSK_DIS );
+		OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
+		OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
+			 R128_GMC_DST_PITCH_OFFSET_CNTL |
+			 R128_GMC_BRUSH_NONE |
+			 (dev_priv->color_fmt << 8) |
+			 R128_GMC_SRC_DATATYPE_COLOR |
+			 R128_ROP3_S |
+			 R128_DP_SRC_SOURCE_MEMORY |
+			 R128_GMC_CLR_CMP_CNTL_DIS |
+			 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
 
 		/* Make this work even if front & back are flipped:
 		 */
 		if (dev_priv->current_page == 0) {
-			OUT_RING( dev_priv->back_pitch_offset_c );
-			OUT_RING( dev_priv->front_pitch_offset_c );
-		} 
-		else {
-			OUT_RING( dev_priv->front_pitch_offset_c );
-			OUT_RING( dev_priv->back_pitch_offset_c );
+			OUT_RING(dev_priv->back_pitch_offset_c);
+			OUT_RING(dev_priv->front_pitch_offset_c);
+		} else {
+			OUT_RING(dev_priv->front_pitch_offset_c);
+			OUT_RING(dev_priv->back_pitch_offset_c);
 		}
 
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (w << 16) | h );
+		OUT_RING((x << 16) | y);
+		OUT_RING((x << 16) | y);
+		OUT_RING((w << 16) | h);
 
 		ADVANCE_RING();
 	}
@@ -523,38 +515,37 @@ static void r128_cce_dispatch_swap( drm_device_t *dev )
 	 */
 	dev_priv->sarea_priv->last_frame++;
 
-	BEGIN_RING( 2 );
+	BEGIN_RING(2);
 
-	OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) );
-	OUT_RING( dev_priv->sarea_priv->last_frame );
+	OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
+	OUT_RING(dev_priv->sarea_priv->last_frame);
 
 	ADVANCE_RING();
 }
 
-static void r128_cce_dispatch_flip( drm_device_t *dev )
+static void r128_cce_dispatch_flip(drm_device_t * dev)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	RING_LOCALS;
-	DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", 
-		__FUNCTION__,
-		dev_priv->current_page,
-		dev_priv->sarea_priv->pfCurrentPage);
+	DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
+		  __FUNCTION__,
+		  dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
 
 #if R128_PERFORMANCE_BOXES
 	/* Do some trivial performance monitoring...
 	 */
-	r128_cce_performance_boxes( dev_priv );
+	r128_cce_performance_boxes(dev_priv);
 #endif
 
-	BEGIN_RING( 4 );
+	BEGIN_RING(4);
 
 	R128_WAIT_UNTIL_PAGE_FLIPPED();
-	OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) );
+	OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0));
 
-	if ( dev_priv->current_page == 0 ) {
-		OUT_RING( dev_priv->back_offset );
+	if (dev_priv->current_page == 0) {
+		OUT_RING(dev_priv->back_offset);
 	} else {
-		OUT_RING( dev_priv->front_offset );
+		OUT_RING(dev_priv->front_offset);
 	}
 
 	ADVANCE_RING();
@@ -565,18 +556,17 @@ static void r128_cce_dispatch_flip( drm_device_t *dev )
 	 */
 	dev_priv->sarea_priv->last_frame++;
 	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
-					      1 - dev_priv->current_page;
+	    1 - dev_priv->current_page;
 
-	BEGIN_RING( 2 );
+	BEGIN_RING(2);
 
-	OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) );
-	OUT_RING( dev_priv->sarea_priv->last_frame );
+	OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
+	OUT_RING(dev_priv->sarea_priv->last_frame);
 
 	ADVANCE_RING();
 }
 
-static void r128_cce_dispatch_vertex( drm_device_t *dev,
-				      drm_buf_t *buf )
+static void r128_cce_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
@@ -587,50 +577,50 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
 	int prim = buf_priv->prim;
 	int i = 0;
 	RING_LOCALS;
-	DRM_DEBUG( "buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox );
+	DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox);
 
-	if ( 0 )
-		r128_print_dirty( "dispatch_vertex", sarea_priv->dirty );
+	if (0)
+		r128_print_dirty("dispatch_vertex", sarea_priv->dirty);
 
-	if ( buf->used ) {
+	if (buf->used) {
 		buf_priv->dispatched = 1;
 
-		if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) {
-			r128_emit_state( dev_priv );
+		if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
+			r128_emit_state(dev_priv);
 		}
 
 		do {
 			/* Emit the next set of up to three cliprects */
-			if ( i < sarea_priv->nbox ) {
-				r128_emit_clip_rects( dev_priv,
-						      &sarea_priv->boxes[i],
-						      sarea_priv->nbox - i );
+			if (i < sarea_priv->nbox) {
+				r128_emit_clip_rects(dev_priv,
+						     &sarea_priv->boxes[i],
+						     sarea_priv->nbox - i);
 			}
 
 			/* Emit the vertex buffer rendering commands */
-			BEGIN_RING( 5 );
+			BEGIN_RING(5);
 
-			OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) );
-			OUT_RING( offset );
-			OUT_RING( size );
-			OUT_RING( format );
-			OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
-				  (size << R128_CCE_VC_CNTL_NUM_SHIFT) );
+			OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3));
+			OUT_RING(offset);
+			OUT_RING(size);
+			OUT_RING(format);
+			OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
+				 (size << R128_CCE_VC_CNTL_NUM_SHIFT));
 
 			ADVANCE_RING();
 
 			i += 3;
-		} while ( i < sarea_priv->nbox );
+		} while (i < sarea_priv->nbox);
 	}
 
-	if ( buf_priv->discard ) {
+	if (buf_priv->discard) {
 		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 
 		/* Emit the vertex buffer age */
-		BEGIN_RING( 2 );
+		BEGIN_RING(2);
 
-		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
-		OUT_RING( buf_priv->age );
+		OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
+		OUT_RING(buf_priv->age);
 
 		ADVANCE_RING();
 
@@ -646,17 +636,15 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
 	sarea_priv->nbox = 0;
 }
 
-static void r128_cce_dispatch_indirect( drm_device_t *dev,
-					drm_buf_t *buf,
-					int start, int end )
+static void r128_cce_dispatch_indirect(drm_device_t * dev,
+				       drm_buf_t * buf, int start, int end)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
 	RING_LOCALS;
-	DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
-		   buf->idx, start, end );
+	DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
 
-	if ( start != end ) {
+	if (start != end) {
 		int offset = buf->bus_address + start;
 		int dwords = (end - start + 3) / sizeof(u32);
 
@@ -664,33 +652,33 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev,
 		 * dwords, so if we've been given an odd number we must
 		 * pad the data with a Type-2 CCE packet.
 		 */
-		if ( dwords & 1 ) {
+		if (dwords & 1) {
 			u32 *data = (u32 *)
-				((char *)dev->agp_buffer_map->handle
-				 + buf->offset + start);
-			data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 );
+			    ((char *)dev->agp_buffer_map->handle
+			     + buf->offset + start);
+			data[dwords++] = cpu_to_le32(R128_CCE_PACKET2);
 		}
 
 		buf_priv->dispatched = 1;
 
 		/* Fire off the indirect buffer */
-		BEGIN_RING( 3 );
+		BEGIN_RING(3);
 
-		OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) );
-		OUT_RING( offset );
-		OUT_RING( dwords );
+		OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1));
+		OUT_RING(offset);
+		OUT_RING(dwords);
 
 		ADVANCE_RING();
 	}
 
-	if ( buf_priv->discard ) {
+	if (buf_priv->discard) {
 		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 
 		/* Emit the indirect buffer age */
-		BEGIN_RING( 2 );
+		BEGIN_RING(2);
 
-		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
-		OUT_RING( buf_priv->age );
+		OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
+		OUT_RING(buf_priv->age);
 
 		ADVANCE_RING();
 
@@ -703,10 +691,9 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev,
 	dev_priv->sarea_priv->last_dispatch++;
 }
 
-static void r128_cce_dispatch_indices( drm_device_t *dev,
-				       drm_buf_t *buf,
-				       int start, int end,
-				       int count )
+static void r128_cce_dispatch_indices(drm_device_t * dev,
+				      drm_buf_t * buf,
+				      int start, int end, int count)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
@@ -718,62 +705,62 @@ static void r128_cce_dispatch_indices( drm_device_t *dev,
 	int dwords;
 	int i = 0;
 	RING_LOCALS;
-	DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count );
+	DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count);
 
-	if ( 0 )
-		r128_print_dirty( "dispatch_indices", sarea_priv->dirty );
+	if (0)
+		r128_print_dirty("dispatch_indices", sarea_priv->dirty);
 
-	if ( start != end ) {
+	if (start != end) {
 		buf_priv->dispatched = 1;
 
-		if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) {
-			r128_emit_state( dev_priv );
+		if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
+			r128_emit_state(dev_priv);
 		}
 
 		dwords = (end - start + 3) / sizeof(u32);
 
-		data = (u32 *)((char *)dev->agp_buffer_map->handle
-			       + buf->offset + start);
+		data = (u32 *) ((char *)dev->agp_buffer_map->handle
+				+ buf->offset + start);
 
-		data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM,
-						    dwords-2 ) );
+		data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM,
+						  dwords - 2));
 
-		data[1] = cpu_to_le32( offset );
-		data[2] = cpu_to_le32( R128_MAX_VB_VERTS );
-		data[3] = cpu_to_le32( format );
-		data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
-					(count << 16)) );
+		data[1] = cpu_to_le32(offset);
+		data[2] = cpu_to_le32(R128_MAX_VB_VERTS);
+		data[3] = cpu_to_le32(format);
+		data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
+				       (count << 16)));
 
-		if ( count & 0x1 ) {
+		if (count & 0x1) {
 #ifdef __LITTLE_ENDIAN
-			data[dwords-1] &= 0x0000ffff;
+			data[dwords - 1] &= 0x0000ffff;
 #else
-			data[dwords-1] &= 0xffff0000;
+			data[dwords - 1] &= 0xffff0000;
 #endif
 		}
 
 		do {
 			/* Emit the next set of up to three cliprects */
-			if ( i < sarea_priv->nbox ) {
-				r128_emit_clip_rects( dev_priv,
-						      &sarea_priv->boxes[i],
-						      sarea_priv->nbox - i );
+			if (i < sarea_priv->nbox) {
+				r128_emit_clip_rects(dev_priv,
+						     &sarea_priv->boxes[i],
+						     sarea_priv->nbox - i);
 			}
 
-			r128_cce_dispatch_indirect( dev, buf, start, end );
+			r128_cce_dispatch_indirect(dev, buf, start, end);
 
 			i += 3;
-		} while ( i < sarea_priv->nbox );
+		} while (i < sarea_priv->nbox);
 	}
 
-	if ( buf_priv->discard ) {
+	if (buf_priv->discard) {
 		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 
 		/* Emit the vertex buffer age */
-		BEGIN_RING( 2 );
+		BEGIN_RING(2);
 
-		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
-		OUT_RING( buf_priv->age );
+		OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
+		OUT_RING(buf_priv->age);
 
 		ADVANCE_RING();
 
@@ -788,9 +775,8 @@ static void r128_cce_dispatch_indices( drm_device_t *dev,
 	sarea_priv->nbox = 0;
 }
 
-static int r128_cce_dispatch_blit( DRMFILE filp,
-				   drm_device_t *dev,
-				   drm_r128_blit_t *blit )
+static int r128_cce_dispatch_blit(DRMFILE filp,
+				  drm_device_t * dev, drm_r128_blit_t * blit)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_device_dma_t *dma = dev->dma;
@@ -799,13 +785,13 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
 	u32 *data;
 	int dword_shift, dwords;
 	RING_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	/* The compiler won't optimize away a division by a variable,
 	 * even if the only legal values are powers of two.  Thus, we'll
 	 * use a shift instead.
 	 */
-	switch ( blit->format ) {
+	switch (blit->format) {
 	case R128_DATATYPE_ARGB8888:
 		dword_shift = 0;
 		break;
@@ -821,7 +807,7 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
 		dword_shift = 2;
 		break;
 	default:
-		DRM_ERROR( "invalid blit format %d\n", blit->format );
+		DRM_ERROR("invalid blit format %d\n", blit->format);
 		return DRM_ERR(EINVAL);
 	}
 
@@ -830,10 +816,10 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
 	 * data from the host data blit, otherwise part of the texture
 	 * image may be corrupted.
 	 */
-	BEGIN_RING( 2 );
+	BEGIN_RING(2);
 
-	OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
-	OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI );
+	OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
+	OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI);
 
 	ADVANCE_RING();
 
@@ -842,13 +828,13 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
 	buf = dma->buflist[blit->idx];
 	buf_priv = buf->dev_private;
 
-	if ( buf->filp != filp ) {
-		DRM_ERROR( "process %d using buffer owned by %p\n",
-			   DRM_CURRENTPID, buf->filp );
+	if (buf->filp != filp) {
+		DRM_ERROR("process %d using buffer owned by %p\n",
+			  DRM_CURRENTPID, buf->filp);
 		return DRM_ERR(EINVAL);
 	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", blit->idx );
+	if (buf->pending) {
+		DRM_ERROR("sending pending buffer %d\n", blit->idx);
 		return DRM_ERR(EINVAL);
 	}
 
@@ -856,45 +842,43 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
 
 	dwords = (blit->width * blit->height) >> dword_shift;
 
-	data = (u32 *)((char *)dev->agp_buffer_map->handle + buf->offset);
-
-	data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) );
-	data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL |
-				R128_GMC_BRUSH_NONE |
-				(blit->format << 8) |
-				R128_GMC_SRC_DATATYPE_COLOR |
-				R128_ROP3_S |
-				R128_DP_SRC_SOURCE_HOST_DATA |
-				R128_GMC_CLR_CMP_CNTL_DIS |
-				R128_GMC_AUX_CLIP_DIS |
-				R128_GMC_WR_MSK_DIS) );
-
-	data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) );
-	data[3] = cpu_to_le32( 0xffffffff );
-	data[4] = cpu_to_le32( 0xffffffff );
-	data[5] = cpu_to_le32( (blit->y << 16) | blit->x );
-	data[6] = cpu_to_le32( (blit->height << 16) | blit->width );
-	data[7] = cpu_to_le32( dwords );
+	data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
+
+	data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6));
+	data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL |
+			       R128_GMC_BRUSH_NONE |
+			       (blit->format << 8) |
+			       R128_GMC_SRC_DATATYPE_COLOR |
+			       R128_ROP3_S |
+			       R128_DP_SRC_SOURCE_HOST_DATA |
+			       R128_GMC_CLR_CMP_CNTL_DIS |
+			       R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS));
+
+	data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5));
+	data[3] = cpu_to_le32(0xffffffff);
+	data[4] = cpu_to_le32(0xffffffff);
+	data[5] = cpu_to_le32((blit->y << 16) | blit->x);
+	data[6] = cpu_to_le32((blit->height << 16) | blit->width);
+	data[7] = cpu_to_le32(dwords);
 
 	buf->used = (dwords + 8) * sizeof(u32);
 
-	r128_cce_dispatch_indirect( dev, buf, 0, buf->used );
+	r128_cce_dispatch_indirect(dev, buf, 0, buf->used);
 
 	/* Flush the pixel cache after the blit completes.  This ensures
 	 * the texture data is written out to memory before rendering
 	 * continues.
 	 */
-	BEGIN_RING( 2 );
+	BEGIN_RING(2);
 
-	OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
-	OUT_RING( R128_PC_FLUSH_GUI );
+	OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
+	OUT_RING(R128_PC_FLUSH_GUI);
 
 	ADVANCE_RING();
 
 	return 0;
 }
 
-
 /* ================================================================
  * Tiled depth buffer management
  *
@@ -902,8 +886,8 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
  * have hardware stencil support.
  */
 
-static int r128_cce_dispatch_write_span( drm_device_t *dev,
-					 drm_r128_depth_t *depth )
+static int r128_cce_dispatch_write_span(drm_device_t * dev,
+					drm_r128_depth_t * depth)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	int count, x, y;
@@ -911,95 +895,95 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev,
 	u8 *mask;
 	int i, buffer_size, mask_size;
 	RING_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	count = depth->n;
 	if (count > 4096 || count <= 0)
 		return DRM_ERR(EMSGSIZE);
 
-	if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
+	if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
 		return DRM_ERR(EFAULT);
 	}
-	if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) {
+	if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
 		return DRM_ERR(EFAULT);
 	}
 
 	buffer_size = depth->n * sizeof(u32);
-	buffer = drm_alloc( buffer_size, DRM_MEM_BUFS );
-	if ( buffer == NULL )
+	buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
+	if (buffer == NULL)
 		return DRM_ERR(ENOMEM);
-	if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) {
-		drm_free( buffer, buffer_size, DRM_MEM_BUFS);
+	if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
+		drm_free(buffer, buffer_size, DRM_MEM_BUFS);
 		return DRM_ERR(EFAULT);
 	}
 
 	mask_size = depth->n * sizeof(u8);
-	if ( depth->mask ) {
-		mask = drm_alloc( mask_size, DRM_MEM_BUFS );
-		if ( mask == NULL ) {
-			drm_free( buffer, buffer_size, DRM_MEM_BUFS );
+	if (depth->mask) {
+		mask = drm_alloc(mask_size, DRM_MEM_BUFS);
+		if (mask == NULL) {
+			drm_free(buffer, buffer_size, DRM_MEM_BUFS);
 			return DRM_ERR(ENOMEM);
 		}
-		if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) {
-			drm_free( buffer, buffer_size, DRM_MEM_BUFS );
-			drm_free( mask, mask_size, DRM_MEM_BUFS );
+		if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
+			drm_free(buffer, buffer_size, DRM_MEM_BUFS);
+			drm_free(mask, mask_size, DRM_MEM_BUFS);
 			return DRM_ERR(EFAULT);
 		}
 
-		for ( i = 0 ; i < count ; i++, x++ ) {
-			if ( mask[i] ) {
-				BEGIN_RING( 6 );
+		for (i = 0; i < count; i++, x++) {
+			if (mask[i]) {
+				BEGIN_RING(6);
 
-				OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-				OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-					  R128_GMC_BRUSH_SOLID_COLOR |
-					  (dev_priv->depth_fmt << 8) |
-					  R128_GMC_SRC_DATATYPE_COLOR |
-					  R128_ROP3_P |
-					  R128_GMC_CLR_CMP_CNTL_DIS |
-					  R128_GMC_WR_MSK_DIS );
+				OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
+				OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
+					 R128_GMC_BRUSH_SOLID_COLOR |
+					 (dev_priv->depth_fmt << 8) |
+					 R128_GMC_SRC_DATATYPE_COLOR |
+					 R128_ROP3_P |
+					 R128_GMC_CLR_CMP_CNTL_DIS |
+					 R128_GMC_WR_MSK_DIS);
 
-				OUT_RING( dev_priv->depth_pitch_offset_c );
-				OUT_RING( buffer[i] );
+				OUT_RING(dev_priv->depth_pitch_offset_c);
+				OUT_RING(buffer[i]);
 
-				OUT_RING( (x << 16) | y );
-				OUT_RING( (1 << 16) | 1 );
+				OUT_RING((x << 16) | y);
+				OUT_RING((1 << 16) | 1);
 
 				ADVANCE_RING();
 			}
 		}
 
-		drm_free( mask, mask_size, DRM_MEM_BUFS );
+		drm_free(mask, mask_size, DRM_MEM_BUFS);
 	} else {
-		for ( i = 0 ; i < count ; i++, x++ ) {
-			BEGIN_RING( 6 );
+		for (i = 0; i < count; i++, x++) {
+			BEGIN_RING(6);
 
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->depth_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_WR_MSK_DIS );
+			OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
+			OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
+				 R128_GMC_BRUSH_SOLID_COLOR |
+				 (dev_priv->depth_fmt << 8) |
+				 R128_GMC_SRC_DATATYPE_COLOR |
+				 R128_ROP3_P |
+				 R128_GMC_CLR_CMP_CNTL_DIS |
+				 R128_GMC_WR_MSK_DIS);
 
-			OUT_RING( dev_priv->depth_pitch_offset_c );
-			OUT_RING( buffer[i] );
+			OUT_RING(dev_priv->depth_pitch_offset_c);
+			OUT_RING(buffer[i]);
 
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (1 << 16) | 1 );
+			OUT_RING((x << 16) | y);
+			OUT_RING((1 << 16) | 1);
 
 			ADVANCE_RING();
 		}
 	}
 
-	drm_free( buffer, buffer_size, DRM_MEM_BUFS );
+	drm_free(buffer, buffer_size, DRM_MEM_BUFS);
 
 	return 0;
 }
 
-static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
-					   drm_r128_depth_t *depth )
+static int r128_cce_dispatch_write_pixels(drm_device_t * dev,
+					  drm_r128_depth_t * depth)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	int count, *x, *y;
@@ -1007,7 +991,7 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
 	u8 *mask;
 	int i, xbuf_size, ybuf_size, buffer_size, mask_size;
 	RING_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	count = depth->n;
 	if (count > 4096 || count <= 0)
@@ -1015,270 +999,266 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
 
 	xbuf_size = count * sizeof(*x);
 	ybuf_size = count * sizeof(*y);
-	x = drm_alloc( xbuf_size, DRM_MEM_BUFS );
-	if ( x == NULL ) {
+	x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
+	if (x == NULL) {
 		return DRM_ERR(ENOMEM);
 	}
-	y = drm_alloc( ybuf_size, DRM_MEM_BUFS );
-	if ( y == NULL ) {
-		drm_free( x, xbuf_size, DRM_MEM_BUFS );
+	y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
+	if (y == NULL) {
+		drm_free(x, xbuf_size, DRM_MEM_BUFS);
 		return DRM_ERR(ENOMEM);
 	}
-	if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) {
-		drm_free( x, xbuf_size, DRM_MEM_BUFS );
-		drm_free( y, ybuf_size, DRM_MEM_BUFS );
+	if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
+		drm_free(x, xbuf_size, DRM_MEM_BUFS);
+		drm_free(y, ybuf_size, DRM_MEM_BUFS);
 		return DRM_ERR(EFAULT);
 	}
-	if ( DRM_COPY_FROM_USER( y, depth->y, xbuf_size ) ) {
-		drm_free( x, xbuf_size, DRM_MEM_BUFS );
-		drm_free( y, ybuf_size, DRM_MEM_BUFS );
+	if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) {
+		drm_free(x, xbuf_size, DRM_MEM_BUFS);
+		drm_free(y, ybuf_size, DRM_MEM_BUFS);
 		return DRM_ERR(EFAULT);
 	}
 
 	buffer_size = depth->n * sizeof(u32);
-	buffer = drm_alloc( buffer_size, DRM_MEM_BUFS );
-	if ( buffer == NULL ) {
-		drm_free( x, xbuf_size, DRM_MEM_BUFS );
-		drm_free( y, ybuf_size, DRM_MEM_BUFS );
+	buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
+	if (buffer == NULL) {
+		drm_free(x, xbuf_size, DRM_MEM_BUFS);
+		drm_free(y, ybuf_size, DRM_MEM_BUFS);
 		return DRM_ERR(ENOMEM);
 	}
-	if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) {
-		drm_free( x, xbuf_size, DRM_MEM_BUFS );
-		drm_free( y, ybuf_size, DRM_MEM_BUFS );
-		drm_free( buffer, buffer_size, DRM_MEM_BUFS );
+	if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
+		drm_free(x, xbuf_size, DRM_MEM_BUFS);
+		drm_free(y, ybuf_size, DRM_MEM_BUFS);
+		drm_free(buffer, buffer_size, DRM_MEM_BUFS);
 		return DRM_ERR(EFAULT);
 	}
 
-	if ( depth->mask ) {
+	if (depth->mask) {
 		mask_size = depth->n * sizeof(u8);
-		mask = drm_alloc( mask_size, DRM_MEM_BUFS );
-		if ( mask == NULL ) {
-			drm_free( x, xbuf_size, DRM_MEM_BUFS );
-			drm_free( y, ybuf_size, DRM_MEM_BUFS );
-			drm_free( buffer, buffer_size, DRM_MEM_BUFS );
+		mask = drm_alloc(mask_size, DRM_MEM_BUFS);
+		if (mask == NULL) {
+			drm_free(x, xbuf_size, DRM_MEM_BUFS);
+			drm_free(y, ybuf_size, DRM_MEM_BUFS);
+			drm_free(buffer, buffer_size, DRM_MEM_BUFS);
 			return DRM_ERR(ENOMEM);
 		}
-		if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) {
-			drm_free( x, xbuf_size, DRM_MEM_BUFS  );
-			drm_free( y, ybuf_size, DRM_MEM_BUFS  );
-			drm_free( buffer, buffer_size, DRM_MEM_BUFS  );
-			drm_free( mask, mask_size, DRM_MEM_BUFS  );
+		if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
+			drm_free(x, xbuf_size, DRM_MEM_BUFS);
+			drm_free(y, ybuf_size, DRM_MEM_BUFS);
+			drm_free(buffer, buffer_size, DRM_MEM_BUFS);
+			drm_free(mask, mask_size, DRM_MEM_BUFS);
 			return DRM_ERR(EFAULT);
 		}
 
-		for ( i = 0 ; i < count ; i++ ) {
-			if ( mask[i] ) {
-				BEGIN_RING( 6 );
+		for (i = 0; i < count; i++) {
+			if (mask[i]) {
+				BEGIN_RING(6);
 
-				OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-				OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-					  R128_GMC_BRUSH_SOLID_COLOR |
-					  (dev_priv->depth_fmt << 8) |
-					  R128_GMC_SRC_DATATYPE_COLOR |
-					  R128_ROP3_P |
-					  R128_GMC_CLR_CMP_CNTL_DIS |
-					  R128_GMC_WR_MSK_DIS );
+				OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
+				OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
+					 R128_GMC_BRUSH_SOLID_COLOR |
+					 (dev_priv->depth_fmt << 8) |
+					 R128_GMC_SRC_DATATYPE_COLOR |
+					 R128_ROP3_P |
+					 R128_GMC_CLR_CMP_CNTL_DIS |
+					 R128_GMC_WR_MSK_DIS);
 
-				OUT_RING( dev_priv->depth_pitch_offset_c );
-				OUT_RING( buffer[i] );
+				OUT_RING(dev_priv->depth_pitch_offset_c);
+				OUT_RING(buffer[i]);
 
-				OUT_RING( (x[i] << 16) | y[i] );
-				OUT_RING( (1 << 16) | 1 );
+				OUT_RING((x[i] << 16) | y[i]);
+				OUT_RING((1 << 16) | 1);
 
 				ADVANCE_RING();
 			}
 		}
 
-		drm_free( mask, mask_size, DRM_MEM_BUFS );
+		drm_free(mask, mask_size, DRM_MEM_BUFS);
 	} else {
-		for ( i = 0 ; i < count ; i++ ) {
-			BEGIN_RING( 6 );
+		for (i = 0; i < count; i++) {
+			BEGIN_RING(6);
 
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->depth_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_WR_MSK_DIS );
+			OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
+			OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
+				 R128_GMC_BRUSH_SOLID_COLOR |
+				 (dev_priv->depth_fmt << 8) |
+				 R128_GMC_SRC_DATATYPE_COLOR |
+				 R128_ROP3_P |
+				 R128_GMC_CLR_CMP_CNTL_DIS |
+				 R128_GMC_WR_MSK_DIS);
 
-			OUT_RING( dev_priv->depth_pitch_offset_c );
-			OUT_RING( buffer[i] );
+			OUT_RING(dev_priv->depth_pitch_offset_c);
+			OUT_RING(buffer[i]);
 
-			OUT_RING( (x[i] << 16) | y[i] );
-			OUT_RING( (1 << 16) | 1 );
+			OUT_RING((x[i] << 16) | y[i]);
+			OUT_RING((1 << 16) | 1);
 
 			ADVANCE_RING();
 		}
 	}
 
-	drm_free( x, xbuf_size, DRM_MEM_BUFS );
-	drm_free( y, ybuf_size, DRM_MEM_BUFS );
-	drm_free( buffer, buffer_size, DRM_MEM_BUFS );
+	drm_free(x, xbuf_size, DRM_MEM_BUFS);
+	drm_free(y, ybuf_size, DRM_MEM_BUFS);
+	drm_free(buffer, buffer_size, DRM_MEM_BUFS);
 
 	return 0;
 }
 
-static int r128_cce_dispatch_read_span( drm_device_t *dev,
-					drm_r128_depth_t *depth )
+static int r128_cce_dispatch_read_span(drm_device_t * dev,
+				       drm_r128_depth_t * depth)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	int count, x, y;
 	RING_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	count = depth->n;
 	if (count > 4096 || count <= 0)
 		return DRM_ERR(EMSGSIZE);
 
-	if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
+	if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
 		return DRM_ERR(EFAULT);
 	}
-	if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) {
+	if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
 		return DRM_ERR(EFAULT);
 	}
 
-	BEGIN_RING( 7 );
+	BEGIN_RING(7);
 
-	OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
-	OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
-		  R128_GMC_DST_PITCH_OFFSET_CNTL |
-		  R128_GMC_BRUSH_NONE |
-		  (dev_priv->depth_fmt << 8) |
-		  R128_GMC_SRC_DATATYPE_COLOR |
-		  R128_ROP3_S |
-		  R128_DP_SRC_SOURCE_MEMORY |
-		  R128_GMC_CLR_CMP_CNTL_DIS |
-		  R128_GMC_WR_MSK_DIS );
+	OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
+	OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
+		 R128_GMC_DST_PITCH_OFFSET_CNTL |
+		 R128_GMC_BRUSH_NONE |
+		 (dev_priv->depth_fmt << 8) |
+		 R128_GMC_SRC_DATATYPE_COLOR |
+		 R128_ROP3_S |
+		 R128_DP_SRC_SOURCE_MEMORY |
+		 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
 
-	OUT_RING( dev_priv->depth_pitch_offset_c );
-	OUT_RING( dev_priv->span_pitch_offset_c );
+	OUT_RING(dev_priv->depth_pitch_offset_c);
+	OUT_RING(dev_priv->span_pitch_offset_c);
 
-	OUT_RING( (x << 16) | y );
-	OUT_RING( (0 << 16) | 0 );
-	OUT_RING( (count << 16) | 1 );
+	OUT_RING((x << 16) | y);
+	OUT_RING((0 << 16) | 0);
+	OUT_RING((count << 16) | 1);
 
 	ADVANCE_RING();
 
 	return 0;
 }
 
-static int r128_cce_dispatch_read_pixels( drm_device_t *dev,
-					  drm_r128_depth_t *depth )
+static int r128_cce_dispatch_read_pixels(drm_device_t * dev,
+					 drm_r128_depth_t * depth)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	int count, *x, *y;
 	int i, xbuf_size, ybuf_size;
 	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
 	count = depth->n;
 	if (count > 4096 || count <= 0)
 		return DRM_ERR(EMSGSIZE);
 
-	if ( count > dev_priv->depth_pitch ) {
+	if (count > dev_priv->depth_pitch) {
 		count = dev_priv->depth_pitch;
 	}
 
 	xbuf_size = count * sizeof(*x);
 	ybuf_size = count * sizeof(*y);
-	x = drm_alloc( xbuf_size, DRM_MEM_BUFS );
-	if ( x == NULL ) {
+	x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
+	if (x == NULL) {
 		return DRM_ERR(ENOMEM);
 	}
-	y = drm_alloc( ybuf_size, DRM_MEM_BUFS );
-	if ( y == NULL ) {
-		drm_free( x, xbuf_size, DRM_MEM_BUFS );
+	y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
+	if (y == NULL) {
+		drm_free(x, xbuf_size, DRM_MEM_BUFS);
 		return DRM_ERR(ENOMEM);
 	}
-	if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) {
-		drm_free( x, xbuf_size, DRM_MEM_BUFS );
-		drm_free( y, ybuf_size, DRM_MEM_BUFS );
+	if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
+		drm_free(x, xbuf_size, DRM_MEM_BUFS);
+		drm_free(y, ybuf_size, DRM_MEM_BUFS);
 		return DRM_ERR(EFAULT);
 	}
-	if ( DRM_COPY_FROM_USER( y, depth->y, ybuf_size ) ) {
-		drm_free( x, xbuf_size, DRM_MEM_BUFS );
-		drm_free( y, ybuf_size, DRM_MEM_BUFS );
+	if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) {
+		drm_free(x, xbuf_size, DRM_MEM_BUFS);
+		drm_free(y, ybuf_size, DRM_MEM_BUFS);
 		return DRM_ERR(EFAULT);
 	}
 
-	for ( i = 0 ; i < count ; i++ ) {
-		BEGIN_RING( 7 );
+	for (i = 0; i < count; i++) {
+		BEGIN_RING(7);
 
-		OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
-		OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
-			  R128_GMC_DST_PITCH_OFFSET_CNTL |
-			  R128_GMC_BRUSH_NONE |
-			  (dev_priv->depth_fmt << 8) |
-			  R128_GMC_SRC_DATATYPE_COLOR |
-			  R128_ROP3_S |
-			  R128_DP_SRC_SOURCE_MEMORY |
-			  R128_GMC_CLR_CMP_CNTL_DIS |
-			  R128_GMC_WR_MSK_DIS );
+		OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
+		OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
+			 R128_GMC_DST_PITCH_OFFSET_CNTL |
+			 R128_GMC_BRUSH_NONE |
+			 (dev_priv->depth_fmt << 8) |
+			 R128_GMC_SRC_DATATYPE_COLOR |
+			 R128_ROP3_S |
+			 R128_DP_SRC_SOURCE_MEMORY |
+			 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
 
-		OUT_RING( dev_priv->depth_pitch_offset_c );
-		OUT_RING( dev_priv->span_pitch_offset_c );
+		OUT_RING(dev_priv->depth_pitch_offset_c);
+		OUT_RING(dev_priv->span_pitch_offset_c);
 
-		OUT_RING( (x[i] << 16) | y[i] );
-		OUT_RING( (i << 16) | 0 );
-		OUT_RING( (1 << 16) | 1 );
+		OUT_RING((x[i] << 16) | y[i]);
+		OUT_RING((i << 16) | 0);
+		OUT_RING((1 << 16) | 1);
 
 		ADVANCE_RING();
 	}
 
-	drm_free( x, xbuf_size, DRM_MEM_BUFS );
-	drm_free( y, ybuf_size, DRM_MEM_BUFS );
+	drm_free(x, xbuf_size, DRM_MEM_BUFS);
+	drm_free(y, ybuf_size, DRM_MEM_BUFS);
 
 	return 0;
 }
 
-
 /* ================================================================
  * Polygon stipple
  */
 
-static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple )
+static void r128_cce_dispatch_stipple(drm_device_t * dev, u32 * stipple)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	int i;
 	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	BEGIN_RING( 33 );
+	BEGIN_RING(33);
 
-	OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) );
-	for ( i = 0 ; i < 32 ; i++ ) {
-		OUT_RING( stipple[i] );
+	OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31));
+	for (i = 0; i < 32; i++) {
+		OUT_RING(stipple[i]);
 	}
 
 	ADVANCE_RING();
 }
 
-
 /* ================================================================
  * IOCTL functions
  */
 
-int r128_cce_clear( DRM_IOCTL_ARGS )
+int r128_cce_clear(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_r128_clear_t clear;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( clear, (drm_r128_clear_t __user *) data,
-			     sizeof(clear) );
+	DRM_COPY_FROM_USER_IOCTL(clear, (drm_r128_clear_t __user *) data,
+				 sizeof(clear));
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
-	if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
+	if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
 
-	r128_cce_dispatch_clear( dev, &clear );
+	r128_cce_dispatch_clear(dev, &clear);
 	COMMIT_RING();
 
 	/* Make sure we restore the 3D state next time.
@@ -1288,17 +1268,17 @@ int r128_cce_clear( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-static int r128_do_init_pageflip( drm_device_t *dev )
+static int r128_do_init_pageflip(drm_device_t * dev)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	dev_priv->crtc_offset =      R128_READ( R128_CRTC_OFFSET );
-	dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL );
+	dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
+	dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);
 
-	R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset );
-	R128_WRITE( R128_CRTC_OFFSET_CNTL,
-		    dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL );
+	R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
+	R128_WRITE(R128_CRTC_OFFSET_CNTL,
+		   dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL);
 
 	dev_priv->page_flipping = 1;
 	dev_priv->current_page = 0;
@@ -1307,16 +1287,16 @@ static int r128_do_init_pageflip( drm_device_t *dev )
 	return 0;
 }
 
-int r128_do_cleanup_pageflip( drm_device_t *dev )
+int r128_do_cleanup_pageflip(drm_device_t * dev)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	R128_WRITE( R128_CRTC_OFFSET,      dev_priv->crtc_offset );
-	R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
+	R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
+	R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
 
 	if (dev_priv->current_page != 0) {
-		r128_cce_dispatch_flip( dev );
+		r128_cce_dispatch_flip(dev);
 		COMMIT_RING();
 	}
 
@@ -1325,43 +1305,43 @@ int r128_do_cleanup_pageflip( drm_device_t *dev )
 }
 
 /* Swapping and flipping are different operations, need different ioctls.
- * They can & should be intermixed to support multiple 3d windows.  
+ * They can & should be intermixed to support multiple 3d windows.
  */
 
-int r128_cce_flip( DRM_IOCTL_ARGS )
+int r128_cce_flip(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
-	if (!dev_priv->page_flipping) 
-		r128_do_init_pageflip( dev );
+	if (!dev_priv->page_flipping)
+		r128_do_init_pageflip(dev);
 
-	r128_cce_dispatch_flip( dev );
+	r128_cce_dispatch_flip(dev);
 
 	COMMIT_RING();
 	return 0;
 }
 
-int r128_cce_swap( DRM_IOCTL_ARGS )
+int r128_cce_swap(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
-	if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
+	if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
 
-	r128_cce_dispatch_swap( dev );
+	r128_cce_dispatch_swap(dev);
 	dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
 					R128_UPLOAD_MASKS);
 
@@ -1369,7 +1349,7 @@ int r128_cce_swap( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-int r128_cce_vertex( DRM_IOCTL_ARGS )
+int r128_cce_vertex(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
@@ -1378,44 +1358,43 @@ int r128_cce_vertex( DRM_IOCTL_ARGS )
 	drm_r128_buf_priv_t *buf_priv;
 	drm_r128_vertex_t vertex;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( vertex, (drm_r128_vertex_t __user *) data,
-			     sizeof(vertex) );
+	DRM_COPY_FROM_USER_IOCTL(vertex, (drm_r128_vertex_t __user *) data,
+				 sizeof(vertex));
 
-	DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n",
-		   DRM_CURRENTPID,
-		   vertex.idx, vertex.count, vertex.discard );
+	DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
+		  DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
 
-	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   vertex.idx, dma->buf_count - 1 );
+	if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
+		DRM_ERROR("buffer index %d (of %d max)\n",
+			  vertex.idx, dma->buf_count - 1);
 		return DRM_ERR(EINVAL);
 	}
-	if ( vertex.prim < 0 ||
-	     vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
-		DRM_ERROR( "buffer prim %d\n", vertex.prim );
+	if (vertex.prim < 0 ||
+	    vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
+		DRM_ERROR("buffer prim %d\n", vertex.prim);
 		return DRM_ERR(EINVAL);
 	}
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
+	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
 	buf = dma->buflist[vertex.idx];
 	buf_priv = buf->dev_private;
 
-	if ( buf->filp != filp ) {
-		DRM_ERROR( "process %d using buffer owned by %p\n",
-			   DRM_CURRENTPID, buf->filp );
+	if (buf->filp != filp) {
+		DRM_ERROR("process %d using buffer owned by %p\n",
+			  DRM_CURRENTPID, buf->filp);
 		return DRM_ERR(EINVAL);
 	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
+	if (buf->pending) {
+		DRM_ERROR("sending pending buffer %d\n", vertex.idx);
 		return DRM_ERR(EINVAL);
 	}
 
@@ -1423,13 +1402,13 @@ int r128_cce_vertex( DRM_IOCTL_ARGS )
 	buf_priv->prim = vertex.prim;
 	buf_priv->discard = vertex.discard;
 
-	r128_cce_dispatch_vertex( dev, buf );
+	r128_cce_dispatch_vertex(dev, buf);
 
 	COMMIT_RING();
 	return 0;
 }
 
-int r128_cce_indices( DRM_IOCTL_ARGS )
+int r128_cce_indices(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
@@ -1439,55 +1418,54 @@ int r128_cce_indices( DRM_IOCTL_ARGS )
 	drm_r128_indices_t elts;
 	int count;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( elts, (drm_r128_indices_t __user *) data,
-			     sizeof(elts) );
+	DRM_COPY_FROM_USER_IOCTL(elts, (drm_r128_indices_t __user *) data,
+				 sizeof(elts));
 
-	DRM_DEBUG( "pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
-		   elts.idx, elts.start, elts.end, elts.discard );
+	DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
+		  elts.idx, elts.start, elts.end, elts.discard);
 
-	if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   elts.idx, dma->buf_count - 1 );
+	if (elts.idx < 0 || elts.idx >= dma->buf_count) {
+		DRM_ERROR("buffer index %d (of %d max)\n",
+			  elts.idx, dma->buf_count - 1);
 		return DRM_ERR(EINVAL);
 	}
-	if ( elts.prim < 0 ||
-	     elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
-		DRM_ERROR( "buffer prim %d\n", elts.prim );
+	if (elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
+		DRM_ERROR("buffer prim %d\n", elts.prim);
 		return DRM_ERR(EINVAL);
 	}
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
+	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
 	buf = dma->buflist[elts.idx];
 	buf_priv = buf->dev_private;
 
-	if ( buf->filp != filp ) {
-		DRM_ERROR( "process %d using buffer owned by %p\n",
-			   DRM_CURRENTPID, buf->filp );
+	if (buf->filp != filp) {
+		DRM_ERROR("process %d using buffer owned by %p\n",
+			  DRM_CURRENTPID, buf->filp);
 		return DRM_ERR(EINVAL);
 	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", elts.idx );
+	if (buf->pending) {
+		DRM_ERROR("sending pending buffer %d\n", elts.idx);
 		return DRM_ERR(EINVAL);
 	}
 
 	count = (elts.end - elts.start) / sizeof(u16);
 	elts.start -= R128_INDEX_PRIM_OFFSET;
 
-	if ( elts.start & 0x7 ) {
-		DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
+	if (elts.start & 0x7) {
+		DRM_ERROR("misaligned buffer 0x%x\n", elts.start);
 		return DRM_ERR(EINVAL);
 	}
-	if ( elts.start < buf->used ) {
-		DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
+	if (elts.start < buf->used) {
+		DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used);
 		return DRM_ERR(EINVAL);
 	}
 
@@ -1495,13 +1473,13 @@ int r128_cce_indices( DRM_IOCTL_ARGS )
 	buf_priv->prim = elts.prim;
 	buf_priv->discard = elts.discard;
 
-	r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count );
+	r128_cce_dispatch_indices(dev, buf, elts.start, elts.end, count);
 
 	COMMIT_RING();
 	return 0;
 }
 
-int r128_cce_blit( DRM_IOCTL_ARGS )
+int r128_cce_blit(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_device_dma_t *dma = dev->dma;
@@ -1509,83 +1487,82 @@ int r128_cce_blit( DRM_IOCTL_ARGS )
 	drm_r128_blit_t blit;
 	int ret;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( blit, (drm_r128_blit_t __user *) data,
-			     sizeof(blit) );
+	DRM_COPY_FROM_USER_IOCTL(blit, (drm_r128_blit_t __user *) data,
+				 sizeof(blit));
 
-	DRM_DEBUG( "pid=%d index=%d\n", DRM_CURRENTPID, blit.idx );
+	DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit.idx);
 
-	if ( blit.idx < 0 || blit.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   blit.idx, dma->buf_count - 1 );
+	if (blit.idx < 0 || blit.idx >= dma->buf_count) {
+		DRM_ERROR("buffer index %d (of %d max)\n",
+			  blit.idx, dma->buf_count - 1);
 		return DRM_ERR(EINVAL);
 	}
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
+	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
-	ret = r128_cce_dispatch_blit( filp, dev, &blit );
+	ret = r128_cce_dispatch_blit(filp, dev, &blit);
 
 	COMMIT_RING();
 	return ret;
 }
 
-int r128_cce_depth( DRM_IOCTL_ARGS )
+int r128_cce_depth(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_depth_t depth;
 	int ret;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( depth, (drm_r128_depth_t __user *) data,
-			     sizeof(depth) );
+	DRM_COPY_FROM_USER_IOCTL(depth, (drm_r128_depth_t __user *) data,
+				 sizeof(depth));
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
 	ret = DRM_ERR(EINVAL);
-	switch ( depth.func ) {
+	switch (depth.func) {
 	case R128_WRITE_SPAN:
-		ret = r128_cce_dispatch_write_span( dev, &depth );
+		ret = r128_cce_dispatch_write_span(dev, &depth);
 	case R128_WRITE_PIXELS:
-		ret = r128_cce_dispatch_write_pixels( dev, &depth );
+		ret = r128_cce_dispatch_write_pixels(dev, &depth);
 	case R128_READ_SPAN:
-		ret = r128_cce_dispatch_read_span( dev, &depth );
+		ret = r128_cce_dispatch_read_span(dev, &depth);
 	case R128_READ_PIXELS:
-		ret = r128_cce_dispatch_read_pixels( dev, &depth );
+		ret = r128_cce_dispatch_read_pixels(dev, &depth);
 	}
 
 	COMMIT_RING();
 	return ret;
 }
 
-int r128_cce_stipple( DRM_IOCTL_ARGS )
+int r128_cce_stipple(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_stipple_t stipple;
 	u32 mask[32];
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( stipple, (drm_r128_stipple_t __user *) data,
-			     sizeof(stipple) );
+	DRM_COPY_FROM_USER_IOCTL(stipple, (drm_r128_stipple_t __user *) data,
+				 sizeof(stipple));
 
-	if ( DRM_COPY_FROM_USER( &mask, stipple.mask,
-			     32 * sizeof(u32) ) )
-		return DRM_ERR( EFAULT );
+	if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32)))
+		return DRM_ERR(EFAULT);
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
-	r128_cce_dispatch_stipple( dev, mask );
+	r128_cce_dispatch_stipple(dev, mask);
 
 	COMMIT_RING();
 	return 0;
 }
 
-int r128_cce_indirect( DRM_IOCTL_ARGS )
+int r128_cce_indirect(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
@@ -1597,47 +1574,46 @@ int r128_cce_indirect( DRM_IOCTL_ARGS )
 	RING_LOCALS;
 #endif
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( indirect, (drm_r128_indirect_t __user *) data,
-			     sizeof(indirect) );
+	DRM_COPY_FROM_USER_IOCTL(indirect, (drm_r128_indirect_t __user *) data,
+				 sizeof(indirect));
 
-	DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
-		   indirect.idx, indirect.start,
-		   indirect.end, indirect.discard );
+	DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
+		  indirect.idx, indirect.start, indirect.end, indirect.discard);
 
-	if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   indirect.idx, dma->buf_count - 1 );
+	if (indirect.idx < 0 || indirect.idx >= dma->buf_count) {
+		DRM_ERROR("buffer index %d (of %d max)\n",
+			  indirect.idx, dma->buf_count - 1);
 		return DRM_ERR(EINVAL);
 	}
 
 	buf = dma->buflist[indirect.idx];
 	buf_priv = buf->dev_private;
 
-	if ( buf->filp != filp ) {
-		DRM_ERROR( "process %d using buffer owned by %p\n",
-			   DRM_CURRENTPID, buf->filp );
+	if (buf->filp != filp) {
+		DRM_ERROR("process %d using buffer owned by %p\n",
+			  DRM_CURRENTPID, buf->filp);
 		return DRM_ERR(EINVAL);
 	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
+	if (buf->pending) {
+		DRM_ERROR("sending pending buffer %d\n", indirect.idx);
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( indirect.start < buf->used ) {
-		DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
-			   indirect.start, buf->used );
+	if (indirect.start < buf->used) {
+		DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
+			  indirect.start, buf->used);
 		return DRM_ERR(EINVAL);
 	}
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
+	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
 	buf->used = indirect.end;
 	buf_priv->discard = indirect.discard;
@@ -1646,7 +1622,7 @@ int r128_cce_indirect( DRM_IOCTL_ARGS )
 	/* Wait for the 3D stream to idle before the indirect buffer
 	 * containing 2D acceleration commands is processed.
 	 */
-	BEGIN_RING( 2 );
+	BEGIN_RING(2);
 	RADEON_WAIT_UNTIL_3D_IDLE();
 	ADVANCE_RING();
 #endif
@@ -1655,30 +1631,30 @@ int r128_cce_indirect( DRM_IOCTL_ARGS )
 	 * X server.  This is insecure and is thus only available to
 	 * privileged clients.
 	 */
-	r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end );
+	r128_cce_dispatch_indirect(dev, buf, indirect.start, indirect.end);
 
 	COMMIT_RING();
 	return 0;
 }
 
-int r128_getparam( DRM_IOCTL_ARGS )
+int r128_getparam(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_r128_private_t *dev_priv = dev->dev_private;
 	drm_r128_getparam_t param;
 	int value;
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( param, (drm_r128_getparam_t __user *)data,
-			     sizeof(param) );
+	DRM_COPY_FROM_USER_IOCTL(param, (drm_r128_getparam_t __user *) data,
+				 sizeof(param));
 
-	DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
+	DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
 
-	switch( param.param ) {
+	switch (param.param) {
 	case R128_PARAM_IRQ_NR:
 		value = dev->irq;
 		break;
@@ -1686,25 +1662,25 @@ int r128_getparam( DRM_IOCTL_ARGS )
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
-		DRM_ERROR( "copy_to_user\n" );
+	if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
+		DRM_ERROR("copy_to_user\n");
 		return DRM_ERR(EFAULT);
 	}
-	
+
 	return 0;
 }
 
-void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp)
+void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp)
 {
-	if ( dev->dev_private ) {
+	if (dev->dev_private) {
 		drm_r128_private_t *dev_priv = dev->dev_private;
-		if ( dev_priv->page_flipping ) {
-			r128_do_cleanup_pageflip( dev );
+		if (dev_priv->page_flipping) {
+			r128_do_cleanup_pageflip(dev);
 		}
-	}			
+	}
 }
 
-void r128_driver_pretakedown(drm_device_t *dev)
+void r128_driver_pretakedown(drm_device_t * dev)
 {
-	r128_do_cleanup_cce( dev );
+	r128_do_cleanup_cce(dev);
 }
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 98bc4c46..33a10ab5 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -37,526 +37,524 @@
 
 /* CP microcode (from ATI) */
 static u32 R200_cp_microcode[][2] = {
-	{ 0x21007000, 0000000000 },        
-	{ 0x20007000, 0000000000 }, 
-	{ 0x000000ab, 0x00000004 },
-	{ 0x000000af, 0x00000004 },
-	{ 0x66544a49, 0000000000 },
-	{ 0x49494174, 0000000000 },
-	{ 0x54517d83, 0000000000 },
-	{ 0x498d8b64, 0000000000 },
-	{ 0x49494949, 0000000000 },
-	{ 0x49da493c, 0000000000 },
-	{ 0x49989898, 0000000000 },
-	{ 0xd34949d5, 0000000000 },
-	{ 0x9dc90e11, 0000000000 },
-	{ 0xce9b9b9b, 0000000000 },
-	{ 0x000f0000, 0x00000016 },
-	{ 0x352e232c, 0000000000 },
-	{ 0x00000013, 0x00000004 },
-	{ 0x000f0000, 0x00000016 },
-	{ 0x352e272c, 0000000000 },
-	{ 0x000f0001, 0x00000016 },
-	{ 0x3239362f, 0000000000 },
-	{ 0x000077ef, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000020, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000020, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000020, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00000016, 0x00000004 },
-	{ 0x0003802a, 0x00000002 },
-	{ 0x040067e0, 0x00000002 },
-	{ 0x00000016, 0x00000004 },
-	{ 0x000077e0, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x000037e1, 0x00000002 },
-	{ 0x040067e1, 0x00000006 },
-	{ 0x000077e0, 0x00000002 },
-	{ 0x000077e1, 0x00000002 },
-	{ 0x000077e1, 0x00000006 },
-	{ 0xffffffff, 0000000000 },
-	{ 0x10000000, 0000000000 },
-	{ 0x0003802a, 0x00000002 },
-	{ 0x040067e0, 0x00000006 },
-	{ 0x00007675, 0x00000002 },
-	{ 0x00007676, 0x00000002 },
-	{ 0x00007677, 0x00000002 },
-	{ 0x00007678, 0x00000006 },
-	{ 0x0003802b, 0x00000002 },
-	{ 0x04002676, 0x00000002 },
-	{ 0x00007677, 0x00000002 },
-	{ 0x00007678, 0x00000006 },
-	{ 0x0000002e, 0x00000018 },
-	{ 0x0000002e, 0x00000018 },
-	{ 0000000000, 0x00000006 },
-	{ 0x0000002f, 0x00000018 },
-	{ 0x0000002f, 0x00000018 },
-	{ 0000000000, 0x00000006 },
-	{ 0x01605000, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x00098000, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x64c0603d, 0x00000004 },
-	{ 0x00080000, 0x00000016 },
-	{ 0000000000, 0000000000 },
-	{ 0x0400251d, 0x00000002 },
-	{ 0x00007580, 0x00000002 },
-	{ 0x00067581, 0x00000002 },
-	{ 0x04002580, 0x00000002 },
-	{ 0x00067581, 0x00000002 },
-	{ 0x00000046, 0x00000004 },
-	{ 0x00005000, 0000000000 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x0000750e, 0x00000002 },
-	{ 0x00019000, 0x00000002 },
-	{ 0x00011055, 0x00000014 },
-	{ 0x00000055, 0x00000012 },
-	{ 0x0400250f, 0x00000002 },
-	{ 0x0000504a, 0x00000004 },
-	{ 0x00007565, 0x00000002 },
-	{ 0x00007566, 0x00000002 },
-	{ 0x00000051, 0x00000004 },
-	{ 0x01e655b4, 0x00000002 },
-	{ 0x4401b0dc, 0x00000002 },
-	{ 0x01c110dc, 0x00000002 },
-	{ 0x2666705d, 0x00000018 },
-	{ 0x040c2565, 0x00000002 },
-	{ 0x0000005d, 0x00000018 },
-	{ 0x04002564, 0x00000002 },
-	{ 0x00007566, 0x00000002 },
-	{ 0x00000054, 0x00000004 },
-	{ 0x00401060, 0x00000008 },
-	{ 0x00101000, 0x00000002 },
-	{ 0x000d80ff, 0x00000002 },
-	{ 0x00800063, 0x00000008 },
-	{ 0x000f9000, 0x00000002 },
-	{ 0x000e00ff, 0x00000002 },
-	{ 0000000000, 0x00000006 },
-	{ 0x00000080, 0x00000018 },
-	{ 0x00000054, 0x00000004 },
-	{ 0x00007576, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x00009000, 0x00000002 },
-	{ 0x00041000, 0x00000002 },
-	{ 0x0c00350e, 0x00000002 },
-	{ 0x00049000, 0x00000002 },
-	{ 0x00051000, 0x00000002 },
-	{ 0x01e785f8, 0x00000002 },
-	{ 0x00200000, 0x00000002 },
-	{ 0x00600073, 0x0000000c },
-	{ 0x00007563, 0x00000002 },
-	{ 0x006075f0, 0x00000021 },
-	{ 0x20007068, 0x00000004 },
-	{ 0x00005068, 0x00000004 },
-	{ 0x00007576, 0x00000002 },
-	{ 0x00007577, 0x00000002 },
-	{ 0x0000750e, 0x00000002 },
-	{ 0x0000750f, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00600076, 0x0000000c },
-	{ 0x006075f0, 0x00000021 },
-	{ 0x000075f8, 0x00000002 },
-	{ 0x00000076, 0x00000004 },
-	{ 0x000a750e, 0x00000002 },
-	{ 0x0020750f, 0x00000002 },
-	{ 0x00600079, 0x00000004 },
-	{ 0x00007570, 0x00000002 },
-	{ 0x00007571, 0x00000002 },
-	{ 0x00007572, 0x00000006 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00007568, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000084, 0x0000000c },
-	{ 0x00058000, 0x00000002 },
-	{ 0x0c607562, 0x00000002 },
-	{ 0x00000086, 0x00000004 },
-	{ 0x00600085, 0x00000004 },
-	{ 0x400070dd, 0000000000 },
-	{ 0x000380dd, 0x00000002 },
-	{ 0x00000093, 0x0000001c },
-	{ 0x00065095, 0x00000018 },
-	{ 0x040025bb, 0x00000002 },
-	{ 0x00061096, 0x00000018 },
-	{ 0x040075bc, 0000000000 },
-	{ 0x000075bb, 0x00000002 },
-	{ 0x000075bc, 0000000000 },
-	{ 0x00090000, 0x00000006 },
-	{ 0x00090000, 0x00000002 },
-	{ 0x000d8002, 0x00000006 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x00007821, 0x00000002 },
-	{ 0x00007800, 0000000000 },
-	{ 0x00007821, 0x00000002 },
-	{ 0x00007800, 0000000000 },
-	{ 0x01665000, 0x00000002 },
-	{ 0x000a0000, 0x00000002 },
-	{ 0x000671cc, 0x00000002 },
-	{ 0x0286f1cd, 0x00000002 },
-	{ 0x000000a3, 0x00000010 },
-	{ 0x21007000, 0000000000 },
-	{ 0x000000aa, 0x0000001c },
-	{ 0x00065000, 0x00000002 },
-	{ 0x000a0000, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x000b0000, 0x00000002 },
-	{ 0x38067000, 0x00000002 },
-	{ 0x000a00a6, 0x00000004 },
-	{ 0x20007000, 0000000000 },
-	{ 0x01200000, 0x00000002 },
-	{ 0x20077000, 0x00000002 },
-	{ 0x01200000, 0x00000002 },
-	{ 0x20007000, 0000000000 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x0120751b, 0x00000002 },
-	{ 0x8040750a, 0x00000002 },
-	{ 0x8040750b, 0x00000002 },
-	{ 0x00110000, 0x00000002 },
-	{ 0x000380dd, 0x00000002 },
-	{ 0x000000bd, 0x0000001c },
-	{ 0x00061096, 0x00000018 },
-	{ 0x844075bd, 0x00000002 },
-	{ 0x00061095, 0x00000018 },
-	{ 0x840075bb, 0x00000002 },
-	{ 0x00061096, 0x00000018 },
-	{ 0x844075bc, 0x00000002 },
-	{ 0x000000c0, 0x00000004 },
-	{ 0x804075bd, 0x00000002 },
-	{ 0x800075bb, 0x00000002 },
-	{ 0x804075bc, 0x00000002 },
-	{ 0x00108000, 0x00000002 },
-	{ 0x01400000, 0x00000002 },
-	{ 0x006000c4, 0x0000000c },
-	{ 0x20c07000, 0x00000020 },
-	{ 0x000000c6, 0x00000012 },
-	{ 0x00800000, 0x00000006 },
-	{ 0x0080751d, 0x00000006 },
-	{ 0x000025bb, 0x00000002 },
-	{ 0x000040c0, 0x00000004 },
-	{ 0x0000775c, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00661000, 0x00000002 },
-	{ 0x0460275d, 0x00000020 },
-	{ 0x00004000, 0000000000 },
-	{ 0x00007999, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00661000, 0x00000002 },
-	{ 0x0460299b, 0x00000020 },
-	{ 0x00004000, 0000000000 },
-	{ 0x01e00830, 0x00000002 },
-	{ 0x21007000, 0000000000 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x00038042, 0x00000002 },
-	{ 0x040025e0, 0x00000002 },
-	{ 0x000075e1, 0000000000 },
-	{ 0x00000001, 0000000000 },
-	{ 0x000380d9, 0x00000002 },
-	{ 0x04007394, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
+	{0x21007000, 0000000000},
+	{0x20007000, 0000000000},
+	{0x000000ab, 0x00000004},
+	{0x000000af, 0x00000004},
+	{0x66544a49, 0000000000},
+	{0x49494174, 0000000000},
+	{0x54517d83, 0000000000},
+	{0x498d8b64, 0000000000},
+	{0x49494949, 0000000000},
+	{0x49da493c, 0000000000},
+	{0x49989898, 0000000000},
+	{0xd34949d5, 0000000000},
+	{0x9dc90e11, 0000000000},
+	{0xce9b9b9b, 0000000000},
+	{0x000f0000, 0x00000016},
+	{0x352e232c, 0000000000},
+	{0x00000013, 0x00000004},
+	{0x000f0000, 0x00000016},
+	{0x352e272c, 0000000000},
+	{0x000f0001, 0x00000016},
+	{0x3239362f, 0000000000},
+	{0x000077ef, 0x00000002},
+	{0x00061000, 0x00000002},
+	{0x00000020, 0x0000001a},
+	{0x00004000, 0x0000001e},
+	{0x00061000, 0x00000002},
+	{0x00000020, 0x0000001a},
+	{0x00004000, 0x0000001e},
+	{0x00061000, 0x00000002},
+	{0x00000020, 0x0000001a},
+	{0x00004000, 0x0000001e},
+	{0x00000016, 0x00000004},
+	{0x0003802a, 0x00000002},
+	{0x040067e0, 0x00000002},
+	{0x00000016, 0x00000004},
+	{0x000077e0, 0x00000002},
+	{0x00065000, 0x00000002},
+	{0x000037e1, 0x00000002},
+	{0x040067e1, 0x00000006},
+	{0x000077e0, 0x00000002},
+	{0x000077e1, 0x00000002},
+	{0x000077e1, 0x00000006},
+	{0xffffffff, 0000000000},
+	{0x10000000, 0000000000},
+	{0x0003802a, 0x00000002},
+	{0x040067e0, 0x00000006},
+	{0x00007675, 0x00000002},
+	{0x00007676, 0x00000002},
+	{0x00007677, 0x00000002},
+	{0x00007678, 0x00000006},
+	{0x0003802b, 0x00000002},
+	{0x04002676, 0x00000002},
+	{0x00007677, 0x00000002},
+	{0x00007678, 0x00000006},
+	{0x0000002e, 0x00000018},
+	{0x0000002e, 0x00000018},
+	{0000000000, 0x00000006},
+	{0x0000002f, 0x00000018},
+	{0x0000002f, 0x00000018},
+	{0000000000, 0x00000006},
+	{0x01605000, 0x00000002},
+	{0x00065000, 0x00000002},
+	{0x00098000, 0x00000002},
+	{0x00061000, 0x00000002},
+	{0x64c0603d, 0x00000004},
+	{0x00080000, 0x00000016},
+	{0000000000, 0000000000},
+	{0x0400251d, 0x00000002},
+	{0x00007580, 0x00000002},
+	{0x00067581, 0x00000002},
+	{0x04002580, 0x00000002},
+	{0x00067581, 0x00000002},
+	{0x00000046, 0x00000004},
+	{0x00005000, 0000000000},
+	{0x00061000, 0x00000002},
+	{0x0000750e, 0x00000002},
+	{0x00019000, 0x00000002},
+	{0x00011055, 0x00000014},
+	{0x00000055, 0x00000012},
+	{0x0400250f, 0x00000002},
+	{0x0000504a, 0x00000004},
+	{0x00007565, 0x00000002},
+	{0x00007566, 0x00000002},
+	{0x00000051, 0x00000004},
+	{0x01e655b4, 0x00000002},
+	{0x4401b0dc, 0x00000002},
+	{0x01c110dc, 0x00000002},
+	{0x2666705d, 0x00000018},
+	{0x040c2565, 0x00000002},
+	{0x0000005d, 0x00000018},
+	{0x04002564, 0x00000002},
+	{0x00007566, 0x00000002},
+	{0x00000054, 0x00000004},
+	{0x00401060, 0x00000008},
+	{0x00101000, 0x00000002},
+	{0x000d80ff, 0x00000002},
+	{0x00800063, 0x00000008},
+	{0x000f9000, 0x00000002},
+	{0x000e00ff, 0x00000002},
+	{0000000000, 0x00000006},
+	{0x00000080, 0x00000018},
+	{0x00000054, 0x00000004},
+	{0x00007576, 0x00000002},
+	{0x00065000, 0x00000002},
+	{0x00009000, 0x00000002},
+	{0x00041000, 0x00000002},
+	{0x0c00350e, 0x00000002},
+	{0x00049000, 0x00000002},
+	{0x00051000, 0x00000002},
+	{0x01e785f8, 0x00000002},
+	{0x00200000, 0x00000002},
+	{0x00600073, 0x0000000c},
+	{0x00007563, 0x00000002},
+	{0x006075f0, 0x00000021},
+	{0x20007068, 0x00000004},
+	{0x00005068, 0x00000004},
+	{0x00007576, 0x00000002},
+	{0x00007577, 0x00000002},
+	{0x0000750e, 0x00000002},
+	{0x0000750f, 0x00000002},
+	{0x00a05000, 0x00000002},
+	{0x00600076, 0x0000000c},
+	{0x006075f0, 0x00000021},
+	{0x000075f8, 0x00000002},
+	{0x00000076, 0x00000004},
+	{0x000a750e, 0x00000002},
+	{0x0020750f, 0x00000002},
+	{0x00600079, 0x00000004},
+	{0x00007570, 0x00000002},
+	{0x00007571, 0x00000002},
+	{0x00007572, 0x00000006},
+	{0x00005000, 0x00000002},
+	{0x00a05000, 0x00000002},
+	{0x00007568, 0x00000002},
+	{0x00061000, 0x00000002},
+	{0x00000084, 0x0000000c},
+	{0x00058000, 0x00000002},
+	{0x0c607562, 0x00000002},
+	{0x00000086, 0x00000004},
+	{0x00600085, 0x00000004},
+	{0x400070dd, 0000000000},
+	{0x000380dd, 0x00000002},
+	{0x00000093, 0x0000001c},
+	{0x00065095, 0x00000018},
+	{0x040025bb, 0x00000002},
+	{0x00061096, 0x00000018},
+	{0x040075bc, 0000000000},
+	{0x000075bb, 0x00000002},
+	{0x000075bc, 0000000000},
+	{0x00090000, 0x00000006},
+	{0x00090000, 0x00000002},
+	{0x000d8002, 0x00000006},
+	{0x00005000, 0x00000002},
+	{0x00007821, 0x00000002},
+	{0x00007800, 0000000000},
+	{0x00007821, 0x00000002},
+	{0x00007800, 0000000000},
+	{0x01665000, 0x00000002},
+	{0x000a0000, 0x00000002},
+	{0x000671cc, 0x00000002},
+	{0x0286f1cd, 0x00000002},
+	{0x000000a3, 0x00000010},
+	{0x21007000, 0000000000},
+	{0x000000aa, 0x0000001c},
+	{0x00065000, 0x00000002},
+	{0x000a0000, 0x00000002},
+	{0x00061000, 0x00000002},
+	{0x000b0000, 0x00000002},
+	{0x38067000, 0x00000002},
+	{0x000a00a6, 0x00000004},
+	{0x20007000, 0000000000},
+	{0x01200000, 0x00000002},
+	{0x20077000, 0x00000002},
+	{0x01200000, 0x00000002},
+	{0x20007000, 0000000000},
+	{0x00061000, 0x00000002},
+	{0x0120751b, 0x00000002},
+	{0x8040750a, 0x00000002},
+	{0x8040750b, 0x00000002},
+	{0x00110000, 0x00000002},
+	{0x000380dd, 0x00000002},
+	{0x000000bd, 0x0000001c},
+	{0x00061096, 0x00000018},
+	{0x844075bd, 0x00000002},
+	{0x00061095, 0x00000018},
+	{0x840075bb, 0x00000002},
+	{0x00061096, 0x00000018},
+	{0x844075bc, 0x00000002},
+	{0x000000c0, 0x00000004},
+	{0x804075bd, 0x00000002},
+	{0x800075bb, 0x00000002},
+	{0x804075bc, 0x00000002},
+	{0x00108000, 0x00000002},
+	{0x01400000, 0x00000002},
+	{0x006000c4, 0x0000000c},
+	{0x20c07000, 0x00000020},
+	{0x000000c6, 0x00000012},
+	{0x00800000, 0x00000006},
+	{0x0080751d, 0x00000006},
+	{0x000025bb, 0x00000002},
+	{0x000040c0, 0x00000004},
+	{0x0000775c, 0x00000002},
+	{0x00a05000, 0x00000002},
+	{0x00661000, 0x00000002},
+	{0x0460275d, 0x00000020},
+	{0x00004000, 0000000000},
+	{0x00007999, 0x00000002},
+	{0x00a05000, 0x00000002},
+	{0x00661000, 0x00000002},
+	{0x0460299b, 0x00000020},
+	{0x00004000, 0000000000},
+	{0x01e00830, 0x00000002},
+	{0x21007000, 0000000000},
+	{0x00005000, 0x00000002},
+	{0x00038042, 0x00000002},
+	{0x040025e0, 0x00000002},
+	{0x000075e1, 0000000000},
+	{0x00000001, 0000000000},
+	{0x000380d9, 0x00000002},
+	{0x04007394, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
 };
 
-
 static u32 radeon_cp_microcode[][2] = {
-	{ 0x21007000, 0000000000 },
-	{ 0x20007000, 0000000000 },
-	{ 0x000000b4, 0x00000004 },
-	{ 0x000000b8, 0x00000004 },
-	{ 0x6f5b4d4c, 0000000000 },
-	{ 0x4c4c427f, 0000000000 },
-	{ 0x5b568a92, 0000000000 },
-	{ 0x4ca09c6d, 0000000000 },
-	{ 0xad4c4c4c, 0000000000 },
-	{ 0x4ce1af3d, 0000000000 },
-	{ 0xd8afafaf, 0000000000 },
-	{ 0xd64c4cdc, 0000000000 },
-	{ 0x4cd10d10, 0000000000 },
-	{ 0x000f0000, 0x00000016 },
-	{ 0x362f242d, 0000000000 },
-	{ 0x00000012, 0x00000004 },
-	{ 0x000f0000, 0x00000016 },
-	{ 0x362f282d, 0000000000 },
-	{ 0x000380e7, 0x00000002 },
-	{ 0x04002c97, 0x00000002 },
-	{ 0x000f0001, 0x00000016 },
-	{ 0x333a3730, 0000000000 },
-	{ 0x000077ef, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000021, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000021, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000021, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00000017, 0x00000004 },
-	{ 0x0003802b, 0x00000002 },
-	{ 0x040067e0, 0x00000002 },
-	{ 0x00000017, 0x00000004 },
-	{ 0x000077e0, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x000037e1, 0x00000002 },
-	{ 0x040067e1, 0x00000006 },
-	{ 0x000077e0, 0x00000002 },
-	{ 0x000077e1, 0x00000002 },
-	{ 0x000077e1, 0x00000006 },
-	{ 0xffffffff, 0000000000 },
-	{ 0x10000000, 0000000000 },
-	{ 0x0003802b, 0x00000002 },
-	{ 0x040067e0, 0x00000006 },
-	{ 0x00007675, 0x00000002 },
-	{ 0x00007676, 0x00000002 },
-	{ 0x00007677, 0x00000002 },
-	{ 0x00007678, 0x00000006 },
-	{ 0x0003802c, 0x00000002 },
-	{ 0x04002676, 0x00000002 },
-	{ 0x00007677, 0x00000002 },
-	{ 0x00007678, 0x00000006 },
-	{ 0x0000002f, 0x00000018 },
-	{ 0x0000002f, 0x00000018 },
-	{ 0000000000, 0x00000006 },
-	{ 0x00000030, 0x00000018 },
-	{ 0x00000030, 0x00000018 },
-	{ 0000000000, 0x00000006 },
-	{ 0x01605000, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x00098000, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x64c0603e, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00080000, 0x00000016 },
-	{ 0000000000, 0000000000 },
-	{ 0x0400251d, 0x00000002 },
-	{ 0x00007580, 0x00000002 },
-	{ 0x00067581, 0x00000002 },
-	{ 0x04002580, 0x00000002 },
-	{ 0x00067581, 0x00000002 },
-	{ 0x00000049, 0x00000004 },
-	{ 0x00005000, 0000000000 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x0000750e, 0x00000002 },
-	{ 0x00019000, 0x00000002 },
-	{ 0x00011055, 0x00000014 },
-	{ 0x00000055, 0x00000012 },
-	{ 0x0400250f, 0x00000002 },
-	{ 0x0000504f, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00007565, 0x00000002 },
-	{ 0x00007566, 0x00000002 },
-	{ 0x00000058, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x01e655b4, 0x00000002 },
-	{ 0x4401b0e4, 0x00000002 },
-	{ 0x01c110e4, 0x00000002 },
-	{ 0x26667066, 0x00000018 },
-	{ 0x040c2565, 0x00000002 },
-	{ 0x00000066, 0x00000018 },
-	{ 0x04002564, 0x00000002 },
-	{ 0x00007566, 0x00000002 },
-	{ 0x0000005d, 0x00000004 },
-	{ 0x00401069, 0x00000008 },
-	{ 0x00101000, 0x00000002 },
-	{ 0x000d80ff, 0x00000002 },
-	{ 0x0080006c, 0x00000008 },
-	{ 0x000f9000, 0x00000002 },
-	{ 0x000e00ff, 0x00000002 },
-	{ 0000000000, 0x00000006 },
-	{ 0x0000008f, 0x00000018 },
-	{ 0x0000005b, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00007576, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x00009000, 0x00000002 },
-	{ 0x00041000, 0x00000002 },
-	{ 0x0c00350e, 0x00000002 },
-	{ 0x00049000, 0x00000002 },
-	{ 0x00051000, 0x00000002 },
-	{ 0x01e785f8, 0x00000002 },
-	{ 0x00200000, 0x00000002 },
-	{ 0x0060007e, 0x0000000c },
-	{ 0x00007563, 0x00000002 },
-	{ 0x006075f0, 0x00000021 },
-	{ 0x20007073, 0x00000004 },
-	{ 0x00005073, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00007576, 0x00000002 },
-	{ 0x00007577, 0x00000002 },
-	{ 0x0000750e, 0x00000002 },
-	{ 0x0000750f, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00600083, 0x0000000c },
-	{ 0x006075f0, 0x00000021 },
-	{ 0x000075f8, 0x00000002 },
-	{ 0x00000083, 0x00000004 },
-	{ 0x000a750e, 0x00000002 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x0020750f, 0x00000002 },
-	{ 0x00600086, 0x00000004 },
-	{ 0x00007570, 0x00000002 },
-	{ 0x00007571, 0x00000002 },
-	{ 0x00007572, 0x00000006 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00007568, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000095, 0x0000000c },
-	{ 0x00058000, 0x00000002 },
-	{ 0x0c607562, 0x00000002 },
-	{ 0x00000097, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00600096, 0x00000004 },
-	{ 0x400070e5, 0000000000 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x000380e5, 0x00000002 },
-	{ 0x000000a8, 0x0000001c },
-	{ 0x000650aa, 0x00000018 },
-	{ 0x040025bb, 0x00000002 },
-	{ 0x000610ab, 0x00000018 },
-	{ 0x040075bc, 0000000000 },
-	{ 0x000075bb, 0x00000002 },
-	{ 0x000075bc, 0000000000 },
-	{ 0x00090000, 0x00000006 },
-	{ 0x00090000, 0x00000002 },
-	{ 0x000d8002, 0x00000006 },
-	{ 0x00007832, 0x00000002 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x000380e7, 0x00000002 },
-	{ 0x04002c97, 0x00000002 },
-	{ 0x00007820, 0x00000002 },
-	{ 0x00007821, 0x00000002 },
-	{ 0x00007800, 0000000000 },
-	{ 0x01200000, 0x00000002 },
-	{ 0x20077000, 0x00000002 },
-	{ 0x01200000, 0x00000002 },
-	{ 0x20007000, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x0120751b, 0x00000002 },
-	{ 0x8040750a, 0x00000002 },
-	{ 0x8040750b, 0x00000002 },
-	{ 0x00110000, 0x00000002 },
-	{ 0x000380e5, 0x00000002 },
-	{ 0x000000c6, 0x0000001c },
-	{ 0x000610ab, 0x00000018 },
-	{ 0x844075bd, 0x00000002 },
-	{ 0x000610aa, 0x00000018 },
-	{ 0x840075bb, 0x00000002 },
-	{ 0x000610ab, 0x00000018 },
-	{ 0x844075bc, 0x00000002 },
-	{ 0x000000c9, 0x00000004 },
-	{ 0x804075bd, 0x00000002 },
-	{ 0x800075bb, 0x00000002 },
-	{ 0x804075bc, 0x00000002 },
-	{ 0x00108000, 0x00000002 },
-	{ 0x01400000, 0x00000002 },
-	{ 0x006000cd, 0x0000000c },
-	{ 0x20c07000, 0x00000020 },
-	{ 0x000000cf, 0x00000012 },
-	{ 0x00800000, 0x00000006 },
-	{ 0x0080751d, 0x00000006 },
-	{ 0000000000, 0000000000 },
-	{ 0x0000775c, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00661000, 0x00000002 },
-	{ 0x0460275d, 0x00000020 },
-	{ 0x00004000, 0000000000 },
-	{ 0x01e00830, 0x00000002 },
-	{ 0x21007000, 0000000000 },
-	{ 0x6464614d, 0000000000 },
-	{ 0x69687420, 0000000000 },
-	{ 0x00000073, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x000380d0, 0x00000002 },
-	{ 0x040025e0, 0x00000002 },
-	{ 0x000075e1, 0000000000 },
-	{ 0x00000001, 0000000000 },
-	{ 0x000380e0, 0x00000002 },
-	{ 0x04002394, 0x00000002 },
-	{ 0x00005000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0x00000008, 0000000000 },
-	{ 0x00000004, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
+	{0x21007000, 0000000000},
+	{0x20007000, 0000000000},
+	{0x000000b4, 0x00000004},
+	{0x000000b8, 0x00000004},
+	{0x6f5b4d4c, 0000000000},
+	{0x4c4c427f, 0000000000},
+	{0x5b568a92, 0000000000},
+	{0x4ca09c6d, 0000000000},
+	{0xad4c4c4c, 0000000000},
+	{0x4ce1af3d, 0000000000},
+	{0xd8afafaf, 0000000000},
+	{0xd64c4cdc, 0000000000},
+	{0x4cd10d10, 0000000000},
+	{0x000f0000, 0x00000016},
+	{0x362f242d, 0000000000},
+	{0x00000012, 0x00000004},
+	{0x000f0000, 0x00000016},
+	{0x362f282d, 0000000000},
+	{0x000380e7, 0x00000002},
+	{0x04002c97, 0x00000002},
+	{0x000f0001, 0x00000016},
+	{0x333a3730, 0000000000},
+	{0x000077ef, 0x00000002},
+	{0x00061000, 0x00000002},
+	{0x00000021, 0x0000001a},
+	{0x00004000, 0x0000001e},
+	{0x00061000, 0x00000002},
+	{0x00000021, 0x0000001a},
+	{0x00004000, 0x0000001e},
+	{0x00061000, 0x00000002},
+	{0x00000021, 0x0000001a},
+	{0x00004000, 0x0000001e},
+	{0x00000017, 0x00000004},
+	{0x0003802b, 0x00000002},
+	{0x040067e0, 0x00000002},
+	{0x00000017, 0x00000004},
+	{0x000077e0, 0x00000002},
+	{0x00065000, 0x00000002},
+	{0x000037e1, 0x00000002},
+	{0x040067e1, 0x00000006},
+	{0x000077e0, 0x00000002},
+	{0x000077e1, 0x00000002},
+	{0x000077e1, 0x00000006},
+	{0xffffffff, 0000000000},
+	{0x10000000, 0000000000},
+	{0x0003802b, 0x00000002},
+	{0x040067e0, 0x00000006},
+	{0x00007675, 0x00000002},
+	{0x00007676, 0x00000002},
+	{0x00007677, 0x00000002},
+	{0x00007678, 0x00000006},
+	{0x0003802c, 0x00000002},
+	{0x04002676, 0x00000002},
+	{0x00007677, 0x00000002},
+	{0x00007678, 0x00000006},
+	{0x0000002f, 0x00000018},
+	{0x0000002f, 0x00000018},
+	{0000000000, 0x00000006},
+	{0x00000030, 0x00000018},
+	{0x00000030, 0x00000018},
+	{0000000000, 0x00000006},
+	{0x01605000, 0x00000002},
+	{0x00065000, 0x00000002},
+	{0x00098000, 0x00000002},
+	{0x00061000, 0x00000002},
+	{0x64c0603e, 0x00000004},
+	{0x000380e6, 0x00000002},
+	{0x040025c5, 0x00000002},
+	{0x00080000, 0x00000016},
+	{0000000000, 0000000000},
+	{0x0400251d, 0x00000002},
+	{0x00007580, 0x00000002},
+	{0x00067581, 0x00000002},
+	{0x04002580, 0x00000002},
+	{0x00067581, 0x00000002},
+	{0x00000049, 0x00000004},
+	{0x00005000, 0000000000},
+	{0x000380e6, 0x00000002},
+	{0x040025c5, 0x00000002},
+	{0x00061000, 0x00000002},
+	{0x0000750e, 0x00000002},
+	{0x00019000, 0x00000002},
+	{0x00011055, 0x00000014},
+	{0x00000055, 0x00000012},
+	{0x0400250f, 0x00000002},
+	{0x0000504f, 0x00000004},
+	{0x000380e6, 0x00000002},
+	{0x040025c5, 0x00000002},
+	{0x00007565, 0x00000002},
+	{0x00007566, 0x00000002},
+	{0x00000058, 0x00000004},
+	{0x000380e6, 0x00000002},
+	{0x040025c5, 0x00000002},
+	{0x01e655b4, 0x00000002},
+	{0x4401b0e4, 0x00000002},
+	{0x01c110e4, 0x00000002},
+	{0x26667066, 0x00000018},
+	{0x040c2565, 0x00000002},
+	{0x00000066, 0x00000018},
+	{0x04002564, 0x00000002},
+	{0x00007566, 0x00000002},
+	{0x0000005d, 0x00000004},
+	{0x00401069, 0x00000008},
+	{0x00101000, 0x00000002},
+	{0x000d80ff, 0x00000002},
+	{0x0080006c, 0x00000008},
+	{0x000f9000, 0x00000002},
+	{0x000e00ff, 0x00000002},
+	{0000000000, 0x00000006},
+	{0x0000008f, 0x00000018},
+	{0x0000005b, 0x00000004},
+	{0x000380e6, 0x00000002},
+	{0x040025c5, 0x00000002},
+	{0x00007576, 0x00000002},
+	{0x00065000, 0x00000002},
+	{0x00009000, 0x00000002},
+	{0x00041000, 0x00000002},
+	{0x0c00350e, 0x00000002},
+	{0x00049000, 0x00000002},
+	{0x00051000, 0x00000002},
+	{0x01e785f8, 0x00000002},
+	{0x00200000, 0x00000002},
+	{0x0060007e, 0x0000000c},
+	{0x00007563, 0x00000002},
+	{0x006075f0, 0x00000021},
+	{0x20007073, 0x00000004},
+	{0x00005073, 0x00000004},
+	{0x000380e6, 0x00000002},
+	{0x040025c5, 0x00000002},
+	{0x00007576, 0x00000002},
+	{0x00007577, 0x00000002},
+	{0x0000750e, 0x00000002},
+	{0x0000750f, 0x00000002},
+	{0x00a05000, 0x00000002},
+	{0x00600083, 0x0000000c},
+	{0x006075f0, 0x00000021},
+	{0x000075f8, 0x00000002},
+	{0x00000083, 0x00000004},
+	{0x000a750e, 0x00000002},
+	{0x000380e6, 0x00000002},
+	{0x040025c5, 0x00000002},
+	{0x0020750f, 0x00000002},
+	{0x00600086, 0x00000004},
+	{0x00007570, 0x00000002},
+	{0x00007571, 0x00000002},
+	{0x00007572, 0x00000006},
+	{0x000380e6, 0x00000002},
+	{0x040025c5, 0x00000002},
+	{0x00005000, 0x00000002},
+	{0x00a05000, 0x00000002},
+	{0x00007568, 0x00000002},
+	{0x00061000, 0x00000002},
+	{0x00000095, 0x0000000c},
+	{0x00058000, 0x00000002},
+	{0x0c607562, 0x00000002},
+	{0x00000097, 0x00000004},
+	{0x000380e6, 0x00000002},
+	{0x040025c5, 0x00000002},
+	{0x00600096, 0x00000004},
+	{0x400070e5, 0000000000},
+	{0x000380e6, 0x00000002},
+	{0x040025c5, 0x00000002},
+	{0x000380e5, 0x00000002},
+	{0x000000a8, 0x0000001c},
+	{0x000650aa, 0x00000018},
+	{0x040025bb, 0x00000002},
+	{0x000610ab, 0x00000018},
+	{0x040075bc, 0000000000},
+	{0x000075bb, 0x00000002},
+	{0x000075bc, 0000000000},
+	{0x00090000, 0x00000006},
+	{0x00090000, 0x00000002},
+	{0x000d8002, 0x00000006},
+	{0x00007832, 0x00000002},
+	{0x00005000, 0x00000002},
+	{0x000380e7, 0x00000002},
+	{0x04002c97, 0x00000002},
+	{0x00007820, 0x00000002},
+	{0x00007821, 0x00000002},
+	{0x00007800, 0000000000},
+	{0x01200000, 0x00000002},
+	{0x20077000, 0x00000002},
+	{0x01200000, 0x00000002},
+	{0x20007000, 0x00000002},
+	{0x00061000, 0x00000002},
+	{0x0120751b, 0x00000002},
+	{0x8040750a, 0x00000002},
+	{0x8040750b, 0x00000002},
+	{0x00110000, 0x00000002},
+	{0x000380e5, 0x00000002},
+	{0x000000c6, 0x0000001c},
+	{0x000610ab, 0x00000018},
+	{0x844075bd, 0x00000002},
+	{0x000610aa, 0x00000018},
+	{0x840075bb, 0x00000002},
+	{0x000610ab, 0x00000018},
+	{0x844075bc, 0x00000002},
+	{0x000000c9, 0x00000004},
+	{0x804075bd, 0x00000002},
+	{0x800075bb, 0x00000002},
+	{0x804075bc, 0x00000002},
+	{0x00108000, 0x00000002},
+	{0x01400000, 0x00000002},
+	{0x006000cd, 0x0000000c},
+	{0x20c07000, 0x00000020},
+	{0x000000cf, 0x00000012},
+	{0x00800000, 0x00000006},
+	{0x0080751d, 0x00000006},
+	{0000000000, 0000000000},
+	{0x0000775c, 0x00000002},
+	{0x00a05000, 0x00000002},
+	{0x00661000, 0x00000002},
+	{0x0460275d, 0x00000020},
+	{0x00004000, 0000000000},
+	{0x01e00830, 0x00000002},
+	{0x21007000, 0000000000},
+	{0x6464614d, 0000000000},
+	{0x69687420, 0000000000},
+	{0x00000073, 0000000000},
+	{0000000000, 0000000000},
+	{0x00005000, 0x00000002},
+	{0x000380d0, 0x00000002},
+	{0x040025e0, 0x00000002},
+	{0x000075e1, 0000000000},
+	{0x00000001, 0000000000},
+	{0x000380e0, 0x00000002},
+	{0x04002394, 0x00000002},
+	{0x00005000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0x00000008, 0000000000},
+	{0x00000004, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
+	{0000000000, 0000000000},
 };
 
-
-int RADEON_READ_PLL(drm_device_t *dev, int addr)
+int RADEON_READ_PLL(drm_device_t * dev, int addr)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
@@ -565,138 +563,133 @@ int RADEON_READ_PLL(drm_device_t *dev, int addr)
 }
 
 #if RADEON_FIFO_DEBUG
-static void radeon_status( drm_radeon_private_t *dev_priv )
+static void radeon_status(drm_radeon_private_t * dev_priv)
 {
-	printk( "%s:\n", __FUNCTION__ );
-	printk( "RBBM_STATUS = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
-	printk( "CP_RB_RTPR = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
-	printk( "CP_RB_WTPR = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
-	printk( "AIC_CNTL = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
-	printk( "AIC_STAT = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
-	printk( "AIC_PT_BASE = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
-	printk( "TLB_ADDR = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
-	printk( "TLB_DATA = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
+	printk("%s:\n", __FUNCTION__);
+	printk("RBBM_STATUS = 0x%08x\n",
+	       (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
+	printk("CP_RB_RTPR = 0x%08x\n",
+	       (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
+	printk("CP_RB_WTPR = 0x%08x\n",
+	       (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
+	printk("AIC_CNTL = 0x%08x\n",
+	       (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
+	printk("AIC_STAT = 0x%08x\n",
+	       (unsigned int)RADEON_READ(RADEON_AIC_STAT));
+	printk("AIC_PT_BASE = 0x%08x\n",
+	       (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
+	printk("TLB_ADDR = 0x%08x\n",
+	       (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
+	printk("TLB_DATA = 0x%08x\n",
+	       (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 }
 #endif
 
-
 /* ================================================================
  * Engine, FIFO control
  */
 
-static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
+static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 {
 	u32 tmp;
 	int i;
 
 	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
-	tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
+	tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
 	tmp |= RADEON_RB2D_DC_FLUSH_ALL;
-	RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
+	RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
-		       & RADEON_RB2D_DC_BUSY) ) {
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
+		      & RADEON_RB2D_DC_BUSY)) {
 			return 0;
 		}
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
 #if RADEON_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	radeon_status( dev_priv );
+	DRM_ERROR("failed!\n");
+	radeon_status(dev_priv);
 #endif
 	return DRM_ERR(EBUSY);
 }
 
-static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
-				    int entries )
+static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 {
 	int i;
 
 	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
-			      & RADEON_RBBM_FIFOCNT_MASK );
-		if ( slots >= entries ) return 0;
-		DRM_UDELAY( 1 );
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		int slots = (RADEON_READ(RADEON_RBBM_STATUS)
+			     & RADEON_RBBM_FIFOCNT_MASK);
+		if (slots >= entries)
+			return 0;
+		DRM_UDELAY(1);
 	}
 
 #if RADEON_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	radeon_status( dev_priv );
+	DRM_ERROR("failed!\n");
+	radeon_status(dev_priv);
 #endif
 	return DRM_ERR(EBUSY);
 }
 
-static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
+static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 {
 	int i, ret;
 
 	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
-	ret = radeon_do_wait_for_fifo( dev_priv, 64 );
-	if ( ret ) return ret;
+	ret = radeon_do_wait_for_fifo(dev_priv, 64);
+	if (ret)
+		return ret;
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(RADEON_READ( RADEON_RBBM_STATUS )
-		       & RADEON_RBBM_ACTIVE) ) {
-			radeon_do_pixcache_flush( dev_priv );
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		if (!(RADEON_READ(RADEON_RBBM_STATUS)
+		      & RADEON_RBBM_ACTIVE)) {
+			radeon_do_pixcache_flush(dev_priv);
 			return 0;
 		}
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
 #if RADEON_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	radeon_status( dev_priv );
+	DRM_ERROR("failed!\n");
+	radeon_status(dev_priv);
 #endif
 	return DRM_ERR(EBUSY);
 }
 
-
 /* ================================================================
  * CP control, initialization
  */
 
 /* Load the microcode for the CP */
-static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
+static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 {
 	int i;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	radeon_do_wait_for_idle( dev_priv );
+	radeon_do_wait_for_idle(dev_priv);
 
-	RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
+	RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 
-	if (dev_priv->is_r200)
-	{
+	if (dev_priv->is_r200) {
 		DRM_INFO("Loading R200 Microcode\n");
-		for ( i = 0 ; i < 256 ; i++ ) 
-		{
-			RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
-				      R200_cp_microcode[i][1] );
-			RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
-				      R200_cp_microcode[i][0] );
+		for (i = 0; i < 256; i++) {
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+				     R200_cp_microcode[i][1]);
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+				     R200_cp_microcode[i][0]);
 		}
-	}
-	else
-	{
-		for ( i = 0 ; i < 256 ; i++ ) {
-			RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
-				      radeon_cp_microcode[i][1] );
-			RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
-				      radeon_cp_microcode[i][0] );
+	} else {
+		for (i = 0; i < 256; i++) {
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+				     radeon_cp_microcode[i][1]);
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+				     radeon_cp_microcode[i][0]);
 		}
 	}
 }
@@ -705,25 +698,25 @@ static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
  * prior to a wait for idle, as it informs the engine that the command
  * stream is ending.
  */
-static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
+static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 {
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 #if 0
 	u32 tmp;
 
-	tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
-	RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
+	tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
+	RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 #endif
 }
 
 /* Wait for the CP to go idle.
  */
-int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
+int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 {
 	RING_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	BEGIN_RING( 6 );
+	BEGIN_RING(6);
 
 	RADEON_PURGE_CACHE();
 	RADEON_PURGE_ZCACHE();
@@ -732,23 +725,23 @@ int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 	ADVANCE_RING();
 	COMMIT_RING();
 
-	return radeon_do_wait_for_idle( dev_priv );
+	return radeon_do_wait_for_idle(dev_priv);
 }
 
 /* Start the Command Processor.
  */
-static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
+static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 {
 	RING_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	radeon_do_wait_for_idle( dev_priv );
+	radeon_do_wait_for_idle(dev_priv);
 
-	RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
+	RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 
 	dev_priv->cp_running = 1;
 
-	BEGIN_RING( 6 );
+	BEGIN_RING(6);
 
 	RADEON_PURGE_CACHE();
 	RADEON_PURGE_ZCACHE();
@@ -762,14 +755,14 @@ static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
  * commands, so you must wait for the CP command stream to complete
  * before calling this routine.
  */
-static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
+static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 {
 	u32 cur_read_ptr;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
-	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
-	SET_RING_HEAD( dev_priv, cur_read_ptr );
+	cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
+	RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
+	SET_RING_HEAD(dev_priv, cur_read_ptr);
 	dev_priv->ring.tail = cur_read_ptr;
 }
 
@@ -777,120 +770,116 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
  * commands, so you must flush the command stream and wait for the CP
  * to go idle before calling this routine.
  */
-static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
+static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 {
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
+	RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 
 	dev_priv->cp_running = 0;
 }
 
 /* Reset the engine.  This will stop the CP if it is running.
  */
-static int radeon_do_engine_reset( drm_device_t *dev )
+static int radeon_do_engine_reset(drm_device_t * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
-	DRM_DEBUG( "\n" );
-
-	radeon_do_pixcache_flush( dev_priv );
-
-	clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
-	mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
-
-	RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
-					      RADEON_FORCEON_MCLKA |
-					      RADEON_FORCEON_MCLKB |
- 					      RADEON_FORCEON_YCLKA |
-					      RADEON_FORCEON_YCLKB |
-					      RADEON_FORCEON_MC |
-					      RADEON_FORCEON_AIC ) );
-
-	rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
+	DRM_DEBUG("\n");
 
-	RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
-						RADEON_SOFT_RESET_CP |
+	radeon_do_pixcache_flush(dev_priv);
+
+	clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
+	mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
+
+	RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
+					    RADEON_FORCEON_MCLKA |
+					    RADEON_FORCEON_MCLKB |
+					    RADEON_FORCEON_YCLKA |
+					    RADEON_FORCEON_YCLKB |
+					    RADEON_FORCEON_MC |
+					    RADEON_FORCEON_AIC));
+
+	rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
+					      RADEON_SOFT_RESET_CP |
+					      RADEON_SOFT_RESET_HI |
+					      RADEON_SOFT_RESET_SE |
+					      RADEON_SOFT_RESET_RE |
+					      RADEON_SOFT_RESET_PP |
+					      RADEON_SOFT_RESET_E2 |
+					      RADEON_SOFT_RESET_RB));
+	RADEON_READ(RADEON_RBBM_SOFT_RESET);
+	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
+					      ~(RADEON_SOFT_RESET_CP |
 						RADEON_SOFT_RESET_HI |
 						RADEON_SOFT_RESET_SE |
 						RADEON_SOFT_RESET_RE |
 						RADEON_SOFT_RESET_PP |
 						RADEON_SOFT_RESET_E2 |
-						RADEON_SOFT_RESET_RB ) );
-	RADEON_READ( RADEON_RBBM_SOFT_RESET );
-	RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
-						~( RADEON_SOFT_RESET_CP |
-						   RADEON_SOFT_RESET_HI |
-						   RADEON_SOFT_RESET_SE |
-						   RADEON_SOFT_RESET_RE |
-						   RADEON_SOFT_RESET_PP |
-						   RADEON_SOFT_RESET_E2 |
-						   RADEON_SOFT_RESET_RB ) ) );
-	RADEON_READ( RADEON_RBBM_SOFT_RESET );
-
-
-	RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
-	RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
-	RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
+						RADEON_SOFT_RESET_RB)));
+	RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+	RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
+	RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
+	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 
 	/* Reset the CP ring */
-	radeon_do_cp_reset( dev_priv );
+	radeon_do_cp_reset(dev_priv);
 
 	/* The CP is no longer running after an engine reset */
 	dev_priv->cp_running = 0;
 
 	/* Reset any pending vertex, indirect buffers */
-	radeon_freelist_reset( dev );
+	radeon_freelist_reset(dev);
 
 	return 0;
 }
 
-static void radeon_cp_init_ring_buffer( drm_device_t *dev,
-				        drm_radeon_private_t *dev_priv )
+static void radeon_cp_init_ring_buffer(drm_device_t * dev,
+				       drm_radeon_private_t * dev_priv)
 {
 	u32 ring_start, cur_read_ptr;
 	u32 tmp;
 
 	/* Initialize the memory controller */
-	RADEON_WRITE( RADEON_MC_FB_LOCATION,
-		      ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
-		    | ( dev_priv->fb_location >> 16 ) );
+	RADEON_WRITE(RADEON_MC_FB_LOCATION,
+		     ((dev_priv->gart_vm_start - 1) & 0xffff0000)
+		     | (dev_priv->fb_location >> 16));
 
 #if __OS_HAS_AGP
 	if (dev_priv->flags & CHIP_IS_AGP) {
-		RADEON_WRITE( RADEON_MC_AGP_LOCATION,
-			      (((dev_priv->gart_vm_start - 1 +
-				 dev_priv->gart_size) & 0xffff0000) |
-			       (dev_priv->gart_vm_start >> 16)) );
+		RADEON_WRITE(RADEON_MC_AGP_LOCATION,
+			     (((dev_priv->gart_vm_start - 1 +
+				dev_priv->gart_size) & 0xffff0000) |
+			      (dev_priv->gart_vm_start >> 16)));
 
 		ring_start = (dev_priv->cp_ring->offset
-			      - dev->agp->base
-			      + dev_priv->gart_vm_start);
+			      - dev->agp->base + dev_priv->gart_vm_start);
 	} else
 #endif
 		ring_start = (dev_priv->cp_ring->offset
-			      - dev->sg->handle
-			      + dev_priv->gart_vm_start);
+			      - dev->sg->handle + dev_priv->gart_vm_start);
 
-	RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
+	RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 
 	/* Set the write pointer delay */
-	RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
+	RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 
 	/* Initialize the ring buffer's read and write pointers */
-	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
-	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
-	SET_RING_HEAD( dev_priv, cur_read_ptr );
+	cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
+	RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
+	SET_RING_HEAD(dev_priv, cur_read_ptr);
 	dev_priv->ring.tail = cur_read_ptr;
 
 #if __OS_HAS_AGP
 	if (dev_priv->flags & CHIP_IS_AGP) {
 		/* set RADEON_AGP_BASE here instead of relying on X from user space */
-		RADEON_WRITE( RADEON_AGP_BASE, (unsigned int)dev->agp->base );
-		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
-			      dev_priv->ring_rptr->offset
-			      - dev->agp->base
-			      + dev_priv->gart_vm_start);
+		RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
+		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
+			     dev_priv->ring_rptr->offset
+			     - dev->agp->base + dev_priv->gart_vm_start);
 	} else
 #endif
 	{
@@ -900,11 +889,10 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
 		tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
 		page_ofs = tmp_ofs >> PAGE_SHIFT;
 
-		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
-			     entry->busaddr[page_ofs]);
-		DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
-			   (unsigned long) entry->busaddr[page_ofs],
-			   entry->handle + tmp_ofs );
+		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
+		DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
+			  (unsigned long)entry->busaddr[page_ofs],
+			  entry->handle + tmp_ofs);
 	}
 
 	/* Initialize the scratch register pointer.  This will cause
@@ -914,108 +902,110 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
 	 * We simply put this behind the ring read pointer, this works
 	 * with PCI GART as well as (whatever kind of) AGP GART
 	 */
-	RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
-					 + RADEON_SCRATCH_REG_OFFSET );
+	RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
+		     + RADEON_SCRATCH_REG_OFFSET);
 
 	dev_priv->scratch = ((__volatile__ u32 *)
 			     dev_priv->ring_rptr->handle +
 			     (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 
-	RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
+	RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 
 	/* Writeback doesn't seem to work everywhere, test it first */
-	DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
-	RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
+	DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
+	RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 
-	for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
-		if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
+	for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
+		if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
+		    0xdeadbeef)
 			break;
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
-	if ( tmp < dev_priv->usec_timeout ) {
+	if (tmp < dev_priv->usec_timeout) {
 		dev_priv->writeback_works = 1;
-		DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
+		DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp);
 	} else {
 		dev_priv->writeback_works = 0;
-		DRM_DEBUG( "writeback test failed\n" );
+		DRM_DEBUG("writeback test failed\n");
 	}
 
 	dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
-	RADEON_WRITE( RADEON_LAST_FRAME_REG,
-		      dev_priv->sarea_priv->last_frame );
+	RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 
 	dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
-	RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
-		      dev_priv->sarea_priv->last_dispatch );
+	RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
+		     dev_priv->sarea_priv->last_dispatch);
 
 	dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
-	RADEON_WRITE( RADEON_LAST_CLEAR_REG,
-		      dev_priv->sarea_priv->last_clear );
+	RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
 
 	/* Set ring buffer size */
 #ifdef __BIG_ENDIAN
-	RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
+	RADEON_WRITE(RADEON_CP_RB_CNTL,
+		     dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
 #else
-	RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
+	RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
 #endif
 
-	radeon_do_wait_for_idle( dev_priv );
+	radeon_do_wait_for_idle(dev_priv);
 
 	/* Turn on bus mastering */
-	tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
-	RADEON_WRITE( RADEON_BUS_CNTL, tmp );
+	tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
+	RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 
 	/* Sync everything up */
-	RADEON_WRITE( RADEON_ISYNC_CNTL,
-		      (RADEON_ISYNC_ANY2D_IDLE3D |
-		       RADEON_ISYNC_ANY3D_IDLE2D |
-		       RADEON_ISYNC_WAIT_IDLEGUI |
-		       RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
+	RADEON_WRITE(RADEON_ISYNC_CNTL,
+		     (RADEON_ISYNC_ANY2D_IDLE3D |
+		      RADEON_ISYNC_ANY3D_IDLE2D |
+		      RADEON_ISYNC_WAIT_IDLEGUI |
+		      RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 }
 
 /* Enable or disable PCI GART on the chip */
-static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
+static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 {
-	u32 tmp	= RADEON_READ( RADEON_AIC_CNTL );
+	u32 tmp = RADEON_READ(RADEON_AIC_CNTL);
 
-	if ( on ) {
-		RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
+	if (on) {
+		RADEON_WRITE(RADEON_AIC_CNTL,
+			     tmp | RADEON_PCIGART_TRANSLATE_EN);
 
 		/* set PCI GART page-table base address
 		 */
-		RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
+		RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart);
 
 		/* set address range for PCI address translate
 		 */
-		RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
-		RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
-						  + dev_priv->gart_size - 1);
+		RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
+		RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
+			     + dev_priv->gart_size - 1);
 
 		/* Turn off AGP aperture -- is this required for PCI GART?
 		 */
-		RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
-		RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
+		RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);	/* ?? */
+		RADEON_WRITE(RADEON_AGP_COMMAND, 0);	/* clear AGP_COMMAND */
 	} else {
-		RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
+		RADEON_WRITE(RADEON_AIC_CNTL,
+			     tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 	}
 }
 
-static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
+static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	if ( (!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg ) {
-		DRM_ERROR( "PCI GART memory not allocated!\n" );
+	if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) {
+		DRM_ERROR("PCI GART memory not allocated!\n");
 		radeon_do_cleanup_cp(dev);
 		return DRM_ERR(EINVAL);
 	}
 
 	dev_priv->usec_timeout = init->usec_timeout;
-	if ( dev_priv->usec_timeout < 1 ||
-	     dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
-		DRM_DEBUG( "TIMEOUT problem!\n" );
+	if (dev_priv->usec_timeout < 1 ||
+	    dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
+		DRM_DEBUG("TIMEOUT problem!\n");
 		radeon_do_cleanup_cp(dev);
 		return DRM_ERR(EINVAL);
 	}
@@ -1028,14 +1018,14 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 	 * but the ring can be in either AGP or PCI space for the ring
 	 * read pointer.
 	 */
-	if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
-	     ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
-		DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
+	if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
+	    (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
+		DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
 		radeon_do_cleanup_cp(dev);
 		return DRM_ERR(EINVAL);
 	}
 
-	switch ( init->fb_bpp ) {
+	switch (init->fb_bpp) {
 	case 16:
 		dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 		break;
@@ -1044,12 +1034,12 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 		dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 		break;
 	}
-	dev_priv->front_offset	= init->front_offset;
-	dev_priv->front_pitch	= init->front_pitch;
-	dev_priv->back_offset	= init->back_offset;
-	dev_priv->back_pitch	= init->back_pitch;
+	dev_priv->front_offset = init->front_offset;
+	dev_priv->front_pitch = init->front_pitch;
+	dev_priv->back_offset = init->back_offset;
+	dev_priv->back_pitch = init->back_pitch;
 
-	switch ( init->depth_bpp ) {
+	switch (init->depth_bpp) {
 	case 16:
 		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 		break;
@@ -1058,8 +1048,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 		break;
 	}
-	dev_priv->depth_offset	= init->depth_offset;
-	dev_priv->depth_pitch	= init->depth_pitch;
+	dev_priv->depth_offset = init->depth_offset;
+	dev_priv->depth_pitch = init->depth_pitch;
 
 	/* Hardware state for depth clears.  Remove this if/when we no
 	 * longer clear the depth buffer with a 3D rectangle.  Hard-code
@@ -1068,16 +1058,15 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 	 */
 	dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 					   (dev_priv->color_fmt << 10) |
-					   (1<<15));
+					   (1 << 15));
 
-	dev_priv->depth_clear.rb3d_zstencilcntl = 
-		(dev_priv->depth_fmt |
-		 RADEON_Z_TEST_ALWAYS |
-		 RADEON_STENCIL_TEST_ALWAYS |
-		 RADEON_STENCIL_S_FAIL_REPLACE |
-		 RADEON_STENCIL_ZPASS_REPLACE |
-		 RADEON_STENCIL_ZFAIL_REPLACE |
-		 RADEON_Z_WRITE_ENABLE);
+	dev_priv->depth_clear.rb3d_zstencilcntl =
+	    (dev_priv->depth_fmt |
+	     RADEON_Z_TEST_ALWAYS |
+	     RADEON_STENCIL_TEST_ALWAYS |
+	     RADEON_STENCIL_S_FAIL_REPLACE |
+	     RADEON_STENCIL_ZPASS_REPLACE |
+	     RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
 
 	dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 					 RADEON_BFACE_SOLID |
@@ -1099,41 +1088,42 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 	dev_priv->ring_rptr_offset = init->ring_rptr_offset;
 	dev_priv->buffers_offset = init->buffers_offset;
 	dev_priv->gart_textures_offset = init->gart_textures_offset;
-	
-	if(!dev_priv->sarea) {
+
+	if (!dev_priv->sarea) {
 		DRM_ERROR("could not find sarea!\n");
 		radeon_do_cleanup_cp(dev);
 		return DRM_ERR(EINVAL);
 	}
 
 	dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
-	if(!dev_priv->mmio) {
+	if (!dev_priv->mmio) {
 		DRM_ERROR("could not find mmio region!\n");
 		radeon_do_cleanup_cp(dev);
 		return DRM_ERR(EINVAL);
 	}
 	dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
-	if(!dev_priv->cp_ring) {
+	if (!dev_priv->cp_ring) {
 		DRM_ERROR("could not find cp ring region!\n");
 		radeon_do_cleanup_cp(dev);
 		return DRM_ERR(EINVAL);
 	}
 	dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
-	if(!dev_priv->ring_rptr) {
+	if (!dev_priv->ring_rptr) {
 		DRM_ERROR("could not find ring read pointer!\n");
 		radeon_do_cleanup_cp(dev);
 		return DRM_ERR(EINVAL);
 	}
 	dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
-	if(!dev->agp_buffer_map) {
+	if (!dev->agp_buffer_map) {
 		DRM_ERROR("could not find dma buffer region!\n");
 		radeon_do_cleanup_cp(dev);
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( init->gart_textures_offset ) {
-		dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset);
-		if ( !dev_priv->gart_textures ) {
+	if (init->gart_textures_offset) {
+		dev_priv->gart_textures =
+		    drm_core_findmap(dev, init->gart_textures_offset);
+		if (!dev_priv->gart_textures) {
 			DRM_ERROR("could not find GART texture region!\n");
 			radeon_do_cleanup_cp(dev);
 			return DRM_ERR(EINVAL);
@@ -1141,17 +1131,17 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 	}
 
 	dev_priv->sarea_priv =
-		(drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
-				       init->sarea_priv_offset);
+	    (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
+				    init->sarea_priv_offset);
 
 #if __OS_HAS_AGP
-	if ( dev_priv->flags & CHIP_IS_AGP ) {
-		drm_core_ioremap( dev_priv->cp_ring, dev );
-		drm_core_ioremap( dev_priv->ring_rptr, dev );
-		drm_core_ioremap( dev->agp_buffer_map, dev );
-		if(!dev_priv->cp_ring->handle ||
-		   !dev_priv->ring_rptr->handle ||
-		   !dev->agp_buffer_map->handle) {
+	if (dev_priv->flags & CHIP_IS_AGP) {
+		drm_core_ioremap(dev_priv->cp_ring, dev);
+		drm_core_ioremap(dev_priv->ring_rptr, dev);
+		drm_core_ioremap(dev->agp_buffer_map, dev);
+		if (!dev_priv->cp_ring->handle ||
+		    !dev_priv->ring_rptr->handle ||
+		    !dev->agp_buffer_map->handle) {
 			DRM_ERROR("could not find ioremap agp regions!\n");
 			radeon_do_cleanup_cp(dev);
 			return DRM_ERR(EINVAL);
@@ -1159,129 +1149,126 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 	} else
 #endif
 	{
-		dev_priv->cp_ring->handle =
-			(void *)dev_priv->cp_ring->offset;
+		dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
 		dev_priv->ring_rptr->handle =
-			(void *)dev_priv->ring_rptr->offset;
-		dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;
-
-		DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
-			   dev_priv->cp_ring->handle );
-		DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
-			   dev_priv->ring_rptr->handle );
-		DRM_DEBUG( "dev->agp_buffer_map->handle %p\n",
-			   dev->agp_buffer_map->handle );
+		    (void *)dev_priv->ring_rptr->offset;
+		dev->agp_buffer_map->handle =
+		    (void *)dev->agp_buffer_map->offset;
+
+		DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
+			  dev_priv->cp_ring->handle);
+		DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
+			  dev_priv->ring_rptr->handle);
+		DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
+			  dev->agp_buffer_map->handle);
 	}
 
-	dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
-				& 0xffff ) << 16;
+	dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
+				 & 0xffff) << 16;
 
-	dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
-					( ( dev_priv->front_offset
-					  + dev_priv->fb_location ) >> 10 ) );
+	dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
+					((dev_priv->front_offset
+					  + dev_priv->fb_location) >> 10));
 
-	dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
-				       ( ( dev_priv->back_offset
-					 + dev_priv->fb_location ) >> 10 ) );
-
-	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
-					( ( dev_priv->depth_offset
-					  + dev_priv->fb_location ) >> 10 ) );
+	dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
+				       ((dev_priv->back_offset
+					 + dev_priv->fb_location) >> 10));
 
+	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
+					((dev_priv->depth_offset
+					  + dev_priv->fb_location) >> 10));
 
 	dev_priv->gart_size = init->gart_size;
 	dev_priv->gart_vm_start = dev_priv->fb_location
-				+ RADEON_READ( RADEON_CONFIG_APER_SIZE );
+	    + RADEON_READ(RADEON_CONFIG_APER_SIZE);
 
 #if __OS_HAS_AGP
 	if (dev_priv->flags & CHIP_IS_AGP)
 		dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
-						- dev->agp->base
-						+ dev_priv->gart_vm_start);
+						 - dev->agp->base
+						 + dev_priv->gart_vm_start);
 	else
 #endif
 		dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
-						- dev->sg->handle
-						+ dev_priv->gart_vm_start);
-
-	DRM_DEBUG( "dev_priv->gart_size %d\n",
-		   dev_priv->gart_size );
-	DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
-		   dev_priv->gart_vm_start );
-	DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
-		   dev_priv->gart_buffers_offset );
-
-	dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
-	dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
+						 - dev->sg->handle
+						 + dev_priv->gart_vm_start);
+
+	DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
+	DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
+	DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
+		  dev_priv->gart_buffers_offset);
+
+	dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
+	dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
 			      + init->ring_size / sizeof(u32));
 	dev_priv->ring.size = init->ring_size;
-	dev_priv->ring.size_l2qw = get_order( init->ring_size / 8 );
+	dev_priv->ring.size_l2qw = get_order(init->ring_size / 8);
 
-	dev_priv->ring.tail_mask =
-		(dev_priv->ring.size / sizeof(u32)) - 1;
+	dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
 
 	dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
 
 #if __OS_HAS_AGP
 	if (dev_priv->flags & CHIP_IS_AGP) {
 		/* Turn off PCI GART */
-		radeon_set_pcigart( dev_priv, 0 );
+		radeon_set_pcigart(dev_priv, 0);
 	} else
 #endif
 	{
-		if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart,
-					    &dev_priv->bus_pci_gart)) {
-			DRM_ERROR( "failed to init PCI GART!\n" );
+		if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart,
+					  &dev_priv->bus_pci_gart)) {
+			DRM_ERROR("failed to init PCI GART!\n");
 			radeon_do_cleanup_cp(dev);
 			return DRM_ERR(ENOMEM);
 		}
 
 		/* Turn on PCI GART */
-		radeon_set_pcigart( dev_priv, 1 );
+		radeon_set_pcigart(dev_priv, 1);
 	}
 
-	radeon_cp_load_microcode( dev_priv );
-	radeon_cp_init_ring_buffer( dev, dev_priv );
+	radeon_cp_load_microcode(dev_priv);
+	radeon_cp_init_ring_buffer(dev, dev_priv);
 
 	dev_priv->last_buf = 0;
 
-	radeon_do_engine_reset( dev );
+	radeon_do_engine_reset(dev);
 
 	return 0;
 }
 
-int radeon_do_cleanup_cp( drm_device_t *dev )
+int radeon_do_cleanup_cp(drm_device_t * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	/* Make sure interrupts are disabled here because the uninstall ioctl
 	 * may not have been called from userspace and after dev_private
 	 * is freed, it's too late.
 	 */
-	if ( dev->irq_enabled ) drm_irq_uninstall(dev);
+	if (dev->irq_enabled)
+		drm_irq_uninstall(dev);
 
 #if __OS_HAS_AGP
 	if (dev_priv->flags & CHIP_IS_AGP) {
-		if ( dev_priv->cp_ring != NULL ) {
-			drm_core_ioremapfree( dev_priv->cp_ring, dev );
+		if (dev_priv->cp_ring != NULL) {
+			drm_core_ioremapfree(dev_priv->cp_ring, dev);
 			dev_priv->cp_ring = NULL;
 		}
-		if ( dev_priv->ring_rptr != NULL ) {
-			drm_core_ioremapfree( dev_priv->ring_rptr, dev );
+		if (dev_priv->ring_rptr != NULL) {
+			drm_core_ioremapfree(dev_priv->ring_rptr, dev);
 			dev_priv->ring_rptr = NULL;
 		}
-		if ( dev->agp_buffer_map != NULL ) {
-			drm_core_ioremapfree( dev->agp_buffer_map, dev );
+		if (dev->agp_buffer_map != NULL) {
+			drm_core_ioremapfree(dev->agp_buffer_map, dev);
 			dev->agp_buffer_map = NULL;
 		}
 	} else
 #endif
 	{
-		if (!drm_ati_pcigart_cleanup( dev,
-					       dev_priv->phys_pci_gart,
-					       dev_priv->bus_pci_gart ))
-			DRM_ERROR( "failed to cleanup PCI GART!\n" );
+		if (!drm_ati_pcigart_cleanup(dev,
+					     dev_priv->phys_pci_gart,
+					     dev_priv->bus_pci_gart))
+			DRM_ERROR("failed to cleanup PCI GART!\n");
 	}
 	/* only clear to the start of flags */
 	memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
@@ -1289,20 +1276,20 @@ int radeon_do_cleanup_cp( drm_device_t *dev )
 	return 0;
 }
 
-/* This code will reinit the Radeon CP hardware after a resume from disc.  
- * AFAIK, it would be very difficult to pickle the state at suspend time, so 
+/* This code will reinit the Radeon CP hardware after a resume from disc.
+ * AFAIK, it would be very difficult to pickle the state at suspend time, so
  * here we make sure that all Radeon hardware initialisation is re-done without
  * affecting running applications.
  *
  * Charl P. Botha <http://cpbotha.net>
  */
-static int radeon_do_resume_cp( drm_device_t *dev )
+static int radeon_do_resume_cp(drm_device_t * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "Called with no initialization\n" );
-		return DRM_ERR( EINVAL );
+	if (!dev_priv) {
+		DRM_ERROR("Called with no initialization\n");
+		return DRM_ERR(EINVAL);
 	}
 
 	DRM_DEBUG("Starting radeon_do_resume_cp()\n");
@@ -1310,64 +1297,64 @@ static int radeon_do_resume_cp( drm_device_t *dev )
 #if __OS_HAS_AGP
 	if (dev_priv->flags & CHIP_IS_AGP) {
 		/* Turn off PCI GART */
-		radeon_set_pcigart( dev_priv, 0 );
+		radeon_set_pcigart(dev_priv, 0);
 	} else
 #endif
 	{
 		/* Turn on PCI GART */
-		radeon_set_pcigart( dev_priv, 1 );
+		radeon_set_pcigart(dev_priv, 1);
 	}
 
-	radeon_cp_load_microcode( dev_priv );
-	radeon_cp_init_ring_buffer( dev, dev_priv );
+	radeon_cp_load_microcode(dev_priv);
+	radeon_cp_init_ring_buffer(dev, dev_priv);
 
-	radeon_do_engine_reset( dev );
+	radeon_do_engine_reset(dev);
 
 	DRM_DEBUG("radeon_do_resume_cp() complete\n");
 
 	return 0;
 }
 
-
-int radeon_cp_init( DRM_IOCTL_ARGS )
+int radeon_cp_init(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_init_t init;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) );
+	DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
+				 sizeof(init));
 
-	switch ( init.func ) {
+	switch (init.func) {
 	case RADEON_INIT_CP:
 	case RADEON_INIT_R200_CP:
-		return radeon_do_init_cp( dev, &init );
+		return radeon_do_init_cp(dev, &init);
 	case RADEON_CLEANUP_CP:
-		return radeon_do_cleanup_cp( dev );
+		return radeon_do_cleanup_cp(dev);
 	}
 
 	return DRM_ERR(EINVAL);
 }
 
-int radeon_cp_start( DRM_IOCTL_ARGS )
+int radeon_cp_start(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( dev_priv->cp_running ) {
-		DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
+	if (dev_priv->cp_running) {
+		DRM_DEBUG("%s while CP running\n", __FUNCTION__);
 		return 0;
 	}
-	if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
-		DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
-			   __FUNCTION__, dev_priv->cp_mode );
+	if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
+		DRM_DEBUG("%s called with bogus CP mode (%d)\n",
+			  __FUNCTION__, dev_priv->cp_mode);
 		return 0;
 	}
 
-	radeon_do_cp_start( dev_priv );
+	radeon_do_cp_start(dev_priv);
 
 	return 0;
 }
@@ -1375,17 +1362,18 @@ int radeon_cp_start( DRM_IOCTL_ARGS )
 /* Stop the CP.  The engine must have been idled before calling this
  * routine.
  */
-int radeon_cp_stop( DRM_IOCTL_ARGS )
+int radeon_cp_stop(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_cp_stop_t stop;
 	int ret;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) );
+	DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
+				 sizeof(stop));
 
 	if (!dev_priv->cp_running)
 		return 0;
@@ -1393,32 +1381,32 @@ int radeon_cp_stop( DRM_IOCTL_ARGS )
 	/* Flush any pending CP commands.  This ensures any outstanding
 	 * commands are exectuted by the engine before we turn it off.
 	 */
-	if ( stop.flush ) {
-		radeon_do_cp_flush( dev_priv );
+	if (stop.flush) {
+		radeon_do_cp_flush(dev_priv);
 	}
 
 	/* If we fail to make the engine go idle, we return an error
 	 * code so that the DRM ioctl wrapper can try again.
 	 */
-	if ( stop.idle ) {
-		ret = radeon_do_cp_idle( dev_priv );
-		if ( ret ) return ret;
+	if (stop.idle) {
+		ret = radeon_do_cp_idle(dev_priv);
+		if (ret)
+			return ret;
 	}
 
 	/* Finally, we can turn off the CP.  If the engine isn't idle,
 	 * we will get some dropped triangles as they won't be fully
 	 * rendered before the CP is shut down.
 	 */
-	radeon_do_cp_stop( dev_priv );
+	radeon_do_cp_stop(dev_priv);
 
 	/* Reset the engine */
-	radeon_do_engine_reset( dev );
+	radeon_do_engine_reset(dev);
 
 	return 0;
 }
 
-
-void radeon_do_release( drm_device_t *dev )
+void radeon_do_release(drm_device_t * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	int ret;
@@ -1427,7 +1415,7 @@ void radeon_do_release( drm_device_t *dev )
 
 		if (dev_priv->cp_running) {
 			/* Stop the cp */
-			while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
+			while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
 				DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
 #ifdef __linux__
 				schedule();
@@ -1435,39 +1423,39 @@ void radeon_do_release( drm_device_t *dev )
 				tsleep(&ret, PZERO, "rdnrel", 1);
 #endif
 			}
-			radeon_do_cp_stop( dev_priv );
-			radeon_do_engine_reset( dev );
+			radeon_do_cp_stop(dev_priv);
+			radeon_do_engine_reset(dev);
 		}
 
 		/* Disable *all* interrupts */
-		if (dev_priv->mmio) /* remove this after permanent addmaps */
-			RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
+		if (dev_priv->mmio)	/* remove this after permanent addmaps */
+			RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 
 		/* Free memory heap structures */
-		radeon_mem_takedown( &(dev_priv->gart_heap) );
-		radeon_mem_takedown( &(dev_priv->fb_heap) );
+		radeon_mem_takedown(&(dev_priv->gart_heap));
+		radeon_mem_takedown(&(dev_priv->fb_heap));
 
 		/* deallocate kernel resources */
-		radeon_do_cleanup_cp( dev );
+		radeon_do_cleanup_cp(dev);
 	}
 }
 
 /* Just reset the CP ring.  Called as part of an X Server engine reset.
  */
-int radeon_cp_reset( DRM_IOCTL_ARGS )
+int radeon_cp_reset(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_DEBUG("%s called before init done\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	radeon_do_cp_reset( dev_priv );
+	radeon_do_cp_reset(dev_priv);
 
 	/* The CP is no longer running after an engine reset */
 	dev_priv->cp_running = 0;
@@ -1475,50 +1463,47 @@ int radeon_cp_reset( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-int radeon_cp_idle( DRM_IOCTL_ARGS )
+int radeon_cp_idle(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	return radeon_do_cp_idle( dev_priv );
+	return radeon_do_cp_idle(dev_priv);
 }
 
 /* Added by Charl P. Botha to call radeon_do_resume_cp().
  */
-int radeon_cp_resume( DRM_IOCTL_ARGS )
+int radeon_cp_resume(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 
 	return radeon_do_resume_cp(dev);
 }
 
-
-int radeon_engine_reset( DRM_IOCTL_ARGS )
+int radeon_engine_reset(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	return radeon_do_engine_reset( dev );
+	return radeon_do_engine_reset(dev);
 }
 
-
 /* ================================================================
  * Fullscreen mode
  */
 
 /* KW: Deprecated to say the least:
  */
-int radeon_fullscreen( DRM_IOCTL_ARGS )
+int radeon_fullscreen(DRM_IOCTL_ARGS)
 {
 	return 0;
 }
 
-
 /* ================================================================
  * Freelist management
  */
@@ -1527,20 +1512,20 @@ int radeon_fullscreen( DRM_IOCTL_ARGS )
  *   bufs until freelist code is used.  Note this hides a problem with
  *   the scratch register * (used to keep track of last buffer
  *   completed) being written to before * the last buffer has actually
- *   completed rendering.  
+ *   completed rendering.
  *
  * KW:  It's also a good way to find free buffers quickly.
  *
  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
  * sleep.  However, bugs in older versions of radeon_accel.c mean that
  * we essentially have to do this, else old clients will break.
- * 
+ *
  * However, it does leave open a potential deadlock where all the
  * buffers are held by other clients, which can't release them because
- * they can't get the lock.  
+ * they can't get the lock.
  */
 
-drm_buf_t *radeon_freelist_get( drm_device_t *dev )
+drm_buf_t *radeon_freelist_get(drm_device_t * dev)
 {
 	drm_device_dma_t *dma = dev->dma;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1549,19 +1534,19 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 	int i, t;
 	int start;
 
-	if ( ++dev_priv->last_buf >= dma->buf_count )
+	if (++dev_priv->last_buf >= dma->buf_count)
 		dev_priv->last_buf = 0;
 
 	start = dev_priv->last_buf;
 
-	for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
-		u32 done_age = GET_SCRATCH( 1 );
-		DRM_DEBUG("done_age = %d\n",done_age);
-		for ( i = start ; i < dma->buf_count ; i++ ) {
+	for (t = 0; t < dev_priv->usec_timeout; t++) {
+		u32 done_age = GET_SCRATCH(1);
+		DRM_DEBUG("done_age = %d\n", done_age);
+		for (i = start; i < dma->buf_count; i++) {
 			buf = dma->buflist[i];
 			buf_priv = buf->dev_private;
-			if ( buf->filp == 0 || (buf->pending && 
-					       buf_priv->age <= done_age) ) {
+			if (buf->filp == 0 || (buf->pending &&
+					       buf_priv->age <= done_age)) {
 				dev_priv->stats.requested_bufs++;
 				buf->pending = 0;
 				return buf;
@@ -1570,16 +1555,17 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 		}
 
 		if (t) {
-			DRM_UDELAY( 1 );
+			DRM_UDELAY(1);
 			dev_priv->stats.freelist_loops++;
 		}
 	}
 
-	DRM_DEBUG( "returning NULL!\n" );
+	DRM_DEBUG("returning NULL!\n");
 	return NULL;
 }
+
 #if 0
-drm_buf_t *radeon_freelist_get( drm_device_t *dev )
+drm_buf_t *radeon_freelist_get(drm_device_t * dev)
 {
 	drm_device_dma_t *dma = dev->dma;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1589,18 +1575,18 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 	int start;
 	u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
 
-	if ( ++dev_priv->last_buf >= dma->buf_count )
+	if (++dev_priv->last_buf >= dma->buf_count)
 		dev_priv->last_buf = 0;
 
 	start = dev_priv->last_buf;
 	dev_priv->stats.freelist_loops++;
-	
-	for ( t = 0 ; t < 2 ; t++ ) {
-		for ( i = start ; i < dma->buf_count ; i++ ) {
+
+	for (t = 0; t < 2; t++) {
+		for (i = start; i < dma->buf_count; i++) {
 			buf = dma->buflist[i];
 			buf_priv = buf->dev_private;
-			if ( buf->filp == 0 || (buf->pending && 
-					       buf_priv->age <= done_age) ) {
+			if (buf->filp == 0 || (buf->pending &&
+					       buf_priv->age <= done_age)) {
 				dev_priv->stats.requested_bufs++;
 				buf->pending = 0;
 				return buf;
@@ -1613,73 +1599,74 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 }
 #endif
 
-void radeon_freelist_reset( drm_device_t *dev )
+void radeon_freelist_reset(drm_device_t * dev)
 {
 	drm_device_dma_t *dma = dev->dma;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	int i;
 
 	dev_priv->last_buf = 0;
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+	for (i = 0; i < dma->buf_count; i++) {
 		drm_buf_t *buf = dma->buflist[i];
 		drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 		buf_priv->age = 0;
 	}
 }
 
-
 /* ================================================================
  * CP command submission
  */
 
-int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
+int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
 {
 	drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
 	int i;
-	u32 last_head = GET_RING_HEAD( dev_priv );
+	u32 last_head = GET_RING_HEAD(dev_priv);
 
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		u32 head = GET_RING_HEAD( dev_priv );
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		u32 head = GET_RING_HEAD(dev_priv);
 
 		ring->space = (head - ring->tail) * sizeof(u32);
-		if ( ring->space <= 0 )
+		if (ring->space <= 0)
 			ring->space += ring->size;
-		if ( ring->space > n )
+		if (ring->space > n)
 			return 0;
-		
+
 		dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
 		if (head != last_head)
 			i = 0;
 		last_head = head;
 
-		DRM_UDELAY( 1 );
+		DRM_UDELAY(1);
 	}
 
 	/* FIXME: This return value is ignored in the BEGIN_RING macro! */
 #if RADEON_FIFO_DEBUG
-	radeon_status( dev_priv );
-	DRM_ERROR( "failed!\n" );
+	radeon_status(dev_priv);
+	DRM_ERROR("failed!\n");
 #endif
 	return DRM_ERR(EBUSY);
 }
 
-static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
+static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
+				 drm_dma_t * d)
 {
 	int i;
 	drm_buf_t *buf;
 
-	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
-		buf = radeon_freelist_get( dev );
-		if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
+	for (i = d->granted_count; i < d->request_count; i++) {
+		buf = radeon_freelist_get(dev);
+		if (!buf)
+			return DRM_ERR(EBUSY);	/* NOTE: broken client */
 
 		buf->filp = filp;
 
-		if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
-				   sizeof(buf->idx) ) )
+		if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
+				     sizeof(buf->idx)))
 			return DRM_ERR(EFAULT);
-		if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
-				   sizeof(buf->total) ) )
+		if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
+				     sizeof(buf->total)))
 			return DRM_ERR(EFAULT);
 
 		d->granted_count++;
@@ -1687,7 +1674,7 @@ static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d
 	return 0;
 }
 
-int radeon_cp_buffers( DRM_IOCTL_ARGS )
+int radeon_cp_buffers(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_device_dma_t *dma = dev->dma;
@@ -1695,95 +1682,101 @@ int radeon_cp_buffers( DRM_IOCTL_ARGS )
 	drm_dma_t __user *argp = (void __user *)data;
 	drm_dma_t d;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
+	DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
 
 	/* Please don't send us buffers.
 	 */
-	if ( d.send_count != 0 ) {
-		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
-			   DRM_CURRENTPID, d.send_count );
+	if (d.send_count != 0) {
+		DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
+			  DRM_CURRENTPID, d.send_count);
 		return DRM_ERR(EINVAL);
 	}
 
 	/* We'll send you buffers.
 	 */
-	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
-		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
-			   DRM_CURRENTPID, d.request_count, dma->buf_count );
+	if (d.request_count < 0 || d.request_count > dma->buf_count) {
+		DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
+			  DRM_CURRENTPID, d.request_count, dma->buf_count);
 		return DRM_ERR(EINVAL);
 	}
 
 	d.granted_count = 0;
 
-	if ( d.request_count ) {
-		ret = radeon_cp_get_buffers( filp, dev, &d );
+	if (d.request_count) {
+		ret = radeon_cp_get_buffers(filp, dev, &d);
 	}
 
-	DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
+	DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
 
 	return ret;
 }
 
 /* Always create a map record for MMIO and FB memory, done from DRIVER_POSTINIT */
-int radeon_preinit( struct drm_device *dev, unsigned long flags )
+int radeon_preinit(struct drm_device *dev, unsigned long flags)
 {
 	u32 save, temp;
 	drm_radeon_private_t *dev_priv;
 	int ret = 0;
 
-	dev_priv = drm_alloc( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
-	if ( dev_priv == NULL )
+	dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
+	if (dev_priv == NULL)
 		return DRM_ERR(ENOMEM);
 
-	memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
+	memset(dev_priv, 0, sizeof(drm_radeon_private_t));
 	dev->dev_private = (void *)dev_priv;
 	dev_priv->flags = flags;
 
 	/* registers */
-	if( (ret = drm_initmap( dev, pci_resource_start( dev->pdev, 2 ),
-			pci_resource_len( dev->pdev, 2 ), _DRM_REGISTERS, 0 )))
+	if ((ret = drm_initmap(dev, pci_resource_start(dev->pdev, 2),
+			       pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
+			       0)))
 		return ret;
 
 	/* framebuffer */
-	if( (ret = drm_initmap( dev, pci_resource_start( dev->pdev, 0 ),
-			pci_resource_len( dev->pdev, 0 ), _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING )))
+	if ((ret = drm_initmap(dev, pci_resource_start(dev->pdev, 0),
+			       pci_resource_len(dev->pdev, 0),
+			       _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING)))
 		return ret;
 
 	/* There are signatures in BIOS and PCI-SSID for a PCI card, but they are not very reliable.
-		Following detection method works for all cards tested so far.
-		Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result.
-		However, calling drmAgpEnable on a PCI card can cause some strange lockup when the server
-		restarts next time.
-	*/
+	   Following detection method works for all cards tested so far.
+	   Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result.
+	   However, calling drmAgpEnable on a PCI card can cause some strange lockup when the server
+	   restarts next time.
+	 */
 	pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &save);
-	pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save | RADEON_AGP_ENABLE);
+	pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG,
+			       save | RADEON_AGP_ENABLE);
 	pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &temp);
 	if (temp & RADEON_AGP_ENABLE)
 		dev_priv->flags |= CHIP_IS_AGP;
-	DRM_DEBUG("%s card detected\n", ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
+	DRM_DEBUG("%s card detected\n",
+		  ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
 	pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save);
-	
+
 	/* Check if we need a reset */
-	if (!(dev_priv->mmio = drm_core_findmap(dev , pci_resource_start( dev->pdev, 2 ))))
+	if (!
+	    (dev_priv->mmio =
+	     drm_core_findmap(dev, pci_resource_start(dev->pdev, 2))))
 		return DRM_ERR(ENOMEM);
-	
+
 #if defined(__linux__)
 	ret = radeon_create_i2c_busses(dev);
 #endif
-        return ret;
+	return ret;
 }
 
-int radeon_postcleanup( struct drm_device *dev )
+int radeon_postcleanup(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	
+
 	DRM_DEBUG("\n");
 #if defined(__linux__)
 	radeon_delete_i2c_busses(dev);
 #endif
-	drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER );
+	drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
 
 	dev->dev_private = NULL;
 	return 0;
diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
index 207a0c00..4b161cf1 100644
--- a/shared-core/radeon_drm.h
+++ b/shared-core/radeon_drm.h
@@ -57,78 +57,77 @@
 #define RADEON_UPLOAD_TEX0IMAGES	0x00001000
 #define RADEON_UPLOAD_TEX1IMAGES	0x00002000
 #define RADEON_UPLOAD_TEX2IMAGES	0x00004000
-#define RADEON_UPLOAD_CLIPRECTS		0x00008000 /* handled client-side */
+#define RADEON_UPLOAD_CLIPRECTS		0x00008000	/* handled client-side */
 #define RADEON_REQUIRE_QUIESCENCE	0x00010000
-#define RADEON_UPLOAD_ZBIAS		0x00020000 /* version 1.2 and newer */
+#define RADEON_UPLOAD_ZBIAS		0x00020000	/* version 1.2 and newer */
 #define RADEON_UPLOAD_ALL		0x003effff
 #define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
 
-
 /* New style per-packet identifiers for use in cmd_buffer ioctl with
  * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
  * state bits and the packet size:
  */
-#define RADEON_EMIT_PP_MISC                         0 /* context/7 */
-#define RADEON_EMIT_PP_CNTL                         1 /* context/3 */
-#define RADEON_EMIT_RB3D_COLORPITCH                 2 /* context/1 */
-#define RADEON_EMIT_RE_LINE_PATTERN                 3 /* line/2 */
-#define RADEON_EMIT_SE_LINE_WIDTH                   4 /* line/1 */
-#define RADEON_EMIT_PP_LUM_MATRIX                   5 /* bumpmap/1 */
-#define RADEON_EMIT_PP_ROT_MATRIX_0                 6 /* bumpmap/2 */
-#define RADEON_EMIT_RB3D_STENCILREFMASK             7 /* masks/3 */
-#define RADEON_EMIT_SE_VPORT_XSCALE                 8 /* viewport/6 */
-#define RADEON_EMIT_SE_CNTL                         9 /* setup/2 */
-#define RADEON_EMIT_SE_CNTL_STATUS                  10 /* setup/1 */
-#define RADEON_EMIT_RE_MISC                         11 /* misc/1 */
-#define RADEON_EMIT_PP_TXFILTER_0                   12 /* tex0/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_0               13 /* tex0/1 */
-#define RADEON_EMIT_PP_TXFILTER_1                   14 /* tex1/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_1               15 /* tex1/1 */
-#define RADEON_EMIT_PP_TXFILTER_2                   16 /* tex2/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_2               17 /* tex2/1 */
-#define RADEON_EMIT_SE_ZBIAS_FACTOR                 18 /* zbias/2 */
-#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19 /* tcl/11 */
-#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20 /* material/17 */
-#define R200_EMIT_PP_TXCBLEND_0                     21 /* tex0/4 */
-#define R200_EMIT_PP_TXCBLEND_1                     22 /* tex1/4 */
-#define R200_EMIT_PP_TXCBLEND_2                     23 /* tex2/4 */
-#define R200_EMIT_PP_TXCBLEND_3                     24 /* tex3/4 */
-#define R200_EMIT_PP_TXCBLEND_4                     25 /* tex4/4 */
-#define R200_EMIT_PP_TXCBLEND_5                     26 /* tex5/4 */
-#define R200_EMIT_PP_TXCBLEND_6                     27 /* /4 */
-#define R200_EMIT_PP_TXCBLEND_7                     28 /* /4 */
-#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29 /* tcl/7 */
-#define R200_EMIT_TFACTOR_0                         30 /* tf/7 */
-#define R200_EMIT_VTX_FMT_0                         31 /* vtx/5 */
-#define R200_EMIT_VAP_CTL                           32 /* vap/1 */
-#define R200_EMIT_MATRIX_SELECT_0                   33 /* msl/5 */
-#define R200_EMIT_TEX_PROC_CTL_2                    34 /* tcg/5 */
-#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35 /* tcl/1 */
-#define R200_EMIT_PP_TXFILTER_0                     36 /* tex0/6 */
-#define R200_EMIT_PP_TXFILTER_1                     37 /* tex1/6 */
-#define R200_EMIT_PP_TXFILTER_2                     38 /* tex2/6 */
-#define R200_EMIT_PP_TXFILTER_3                     39 /* tex3/6 */
-#define R200_EMIT_PP_TXFILTER_4                     40 /* tex4/6 */
-#define R200_EMIT_PP_TXFILTER_5                     41 /* tex5/6 */
-#define R200_EMIT_PP_TXOFFSET_0                     42 /* tex0/1 */
-#define R200_EMIT_PP_TXOFFSET_1                     43 /* tex1/1 */
-#define R200_EMIT_PP_TXOFFSET_2                     44 /* tex2/1 */
-#define R200_EMIT_PP_TXOFFSET_3                     45 /* tex3/1 */
-#define R200_EMIT_PP_TXOFFSET_4                     46 /* tex4/1 */
-#define R200_EMIT_PP_TXOFFSET_5                     47 /* tex5/1 */
-#define R200_EMIT_VTE_CNTL                          48 /* vte/1 */
-#define R200_EMIT_OUTPUT_VTX_COMP_SEL               49 /* vtx/1 */
-#define R200_EMIT_PP_TAM_DEBUG3                     50 /* tam/1 */
-#define R200_EMIT_PP_CNTL_X                         51 /* cst/1 */
-#define R200_EMIT_RB3D_DEPTHXY_OFFSET               52 /* cst/1 */
-#define R200_EMIT_RE_AUX_SCISSOR_CNTL               53 /* cst/1 */
-#define R200_EMIT_RE_SCISSOR_TL_0                   54 /* cst/2 */
-#define R200_EMIT_RE_SCISSOR_TL_1                   55 /* cst/2 */
-#define R200_EMIT_RE_SCISSOR_TL_2                   56 /* cst/2 */
-#define R200_EMIT_SE_VAP_CNTL_STATUS                57 /* cst/1 */
-#define R200_EMIT_SE_VTX_STATE_CNTL                 58 /* cst/1 */
-#define R200_EMIT_RE_POINTSIZE                      59 /* cst/1 */
-#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60 /* cst/4 */
+#define RADEON_EMIT_PP_MISC                         0	/* context/7 */
+#define RADEON_EMIT_PP_CNTL                         1	/* context/3 */
+#define RADEON_EMIT_RB3D_COLORPITCH                 2	/* context/1 */
+#define RADEON_EMIT_RE_LINE_PATTERN                 3	/* line/2 */
+#define RADEON_EMIT_SE_LINE_WIDTH                   4	/* line/1 */
+#define RADEON_EMIT_PP_LUM_MATRIX                   5	/* bumpmap/1 */
+#define RADEON_EMIT_PP_ROT_MATRIX_0                 6	/* bumpmap/2 */
+#define RADEON_EMIT_RB3D_STENCILREFMASK             7	/* masks/3 */
+#define RADEON_EMIT_SE_VPORT_XSCALE                 8	/* viewport/6 */
+#define RADEON_EMIT_SE_CNTL                         9	/* setup/2 */
+#define RADEON_EMIT_SE_CNTL_STATUS                  10	/* setup/1 */
+#define RADEON_EMIT_RE_MISC                         11	/* misc/1 */
+#define RADEON_EMIT_PP_TXFILTER_0                   12	/* tex0/6 */
+#define RADEON_EMIT_PP_BORDER_COLOR_0               13	/* tex0/1 */
+#define RADEON_EMIT_PP_TXFILTER_1                   14	/* tex1/6 */
+#define RADEON_EMIT_PP_BORDER_COLOR_1               15	/* tex1/1 */
+#define RADEON_EMIT_PP_TXFILTER_2                   16	/* tex2/6 */
+#define RADEON_EMIT_PP_BORDER_COLOR_2               17	/* tex2/1 */
+#define RADEON_EMIT_SE_ZBIAS_FACTOR                 18	/* zbias/2 */
+#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19	/* tcl/11 */
+#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20	/* material/17 */
+#define R200_EMIT_PP_TXCBLEND_0                     21	/* tex0/4 */
+#define R200_EMIT_PP_TXCBLEND_1                     22	/* tex1/4 */
+#define R200_EMIT_PP_TXCBLEND_2                     23	/* tex2/4 */
+#define R200_EMIT_PP_TXCBLEND_3                     24	/* tex3/4 */
+#define R200_EMIT_PP_TXCBLEND_4                     25	/* tex4/4 */
+#define R200_EMIT_PP_TXCBLEND_5                     26	/* tex5/4 */
+#define R200_EMIT_PP_TXCBLEND_6                     27	/* /4 */
+#define R200_EMIT_PP_TXCBLEND_7                     28	/* /4 */
+#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29	/* tcl/7 */
+#define R200_EMIT_TFACTOR_0                         30	/* tf/7 */
+#define R200_EMIT_VTX_FMT_0                         31	/* vtx/5 */
+#define R200_EMIT_VAP_CTL                           32	/* vap/1 */
+#define R200_EMIT_MATRIX_SELECT_0                   33	/* msl/5 */
+#define R200_EMIT_TEX_PROC_CTL_2                    34	/* tcg/5 */
+#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35	/* tcl/1 */
+#define R200_EMIT_PP_TXFILTER_0                     36	/* tex0/6 */
+#define R200_EMIT_PP_TXFILTER_1                     37	/* tex1/6 */
+#define R200_EMIT_PP_TXFILTER_2                     38	/* tex2/6 */
+#define R200_EMIT_PP_TXFILTER_3                     39	/* tex3/6 */
+#define R200_EMIT_PP_TXFILTER_4                     40	/* tex4/6 */
+#define R200_EMIT_PP_TXFILTER_5                     41	/* tex5/6 */
+#define R200_EMIT_PP_TXOFFSET_0                     42	/* tex0/1 */
+#define R200_EMIT_PP_TXOFFSET_1                     43	/* tex1/1 */
+#define R200_EMIT_PP_TXOFFSET_2                     44	/* tex2/1 */
+#define R200_EMIT_PP_TXOFFSET_3                     45	/* tex3/1 */
+#define R200_EMIT_PP_TXOFFSET_4                     46	/* tex4/1 */
+#define R200_EMIT_PP_TXOFFSET_5                     47	/* tex5/1 */
+#define R200_EMIT_VTE_CNTL                          48	/* vte/1 */
+#define R200_EMIT_OUTPUT_VTX_COMP_SEL               49	/* vtx/1 */
+#define R200_EMIT_PP_TAM_DEBUG3                     50	/* tam/1 */
+#define R200_EMIT_PP_CNTL_X                         51	/* cst/1 */
+#define R200_EMIT_RB3D_DEPTHXY_OFFSET               52	/* cst/1 */
+#define R200_EMIT_RE_AUX_SCISSOR_CNTL               53	/* cst/1 */
+#define R200_EMIT_RE_SCISSOR_TL_0                   54	/* cst/2 */
+#define R200_EMIT_RE_SCISSOR_TL_1                   55	/* cst/2 */
+#define R200_EMIT_RE_SCISSOR_TL_2                   56	/* cst/2 */
+#define R200_EMIT_SE_VAP_CNTL_STATUS                57	/* cst/1 */
+#define R200_EMIT_SE_VTX_STATE_CNTL                 58	/* cst/1 */
+#define R200_EMIT_RE_POINTSIZE                      59	/* cst/1 */
+#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60	/* cst/4 */
 #define R200_EMIT_PP_CUBIC_FACES_0                  61
 #define R200_EMIT_PP_CUBIC_OFFSETS_0                62
 #define R200_EMIT_PP_CUBIC_FACES_1                  63
@@ -147,48 +146,45 @@
 #define R200_EMIT_RB3D_BLENDCOLOR                   76
 #define RADEON_MAX_STATE_PACKETS                    77
 
-
 /* Commands understood by cmd_buffer ioctl.  More can be added but
  * obviously these can't be removed or changed:
  */
-#define RADEON_CMD_PACKET      1 /* emit one of the register packets above */
-#define RADEON_CMD_SCALARS     2 /* emit scalar data */
-#define RADEON_CMD_VECTORS     3 /* emit vector data */
-#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
-#define RADEON_CMD_PACKET3     5 /* emit hw packet */
-#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
-#define RADEON_CMD_SCALARS2     7 /* r200 stopgap */
-#define RADEON_CMD_WAIT         8 /* emit hw wait commands -- note:
-				   *  doesn't make the cpu wait, just
-				   *  the graphics hardware */
-
+#define RADEON_CMD_PACKET      1	/* emit one of the register packets above */
+#define RADEON_CMD_SCALARS     2	/* emit scalar data */
+#define RADEON_CMD_VECTORS     3	/* emit vector data */
+#define RADEON_CMD_DMA_DISCARD 4	/* discard current dma buf */
+#define RADEON_CMD_PACKET3     5	/* emit hw packet */
+#define RADEON_CMD_PACKET3_CLIP 6	/* emit hw packet wrapped in cliprects */
+#define RADEON_CMD_SCALARS2     7	/* r200 stopgap */
+#define RADEON_CMD_WAIT         8	/* emit hw wait commands -- note:
+					 *  doesn't make the cpu wait, just
+					 *  the graphics hardware */
 
 typedef union {
 	int i;
-	struct { 
+	struct {
 		unsigned char cmd_type, pad0, pad1, pad2;
 	} header;
-	struct { 
+	struct {
 		unsigned char cmd_type, packet_id, pad0, pad1;
 	} packet;
-	struct { 
-		unsigned char cmd_type, offset, stride, count; 
+	struct {
+		unsigned char cmd_type, offset, stride, count;
 	} scalars;
-	struct { 
-		unsigned char cmd_type, offset, stride, count; 
+	struct {
+		unsigned char cmd_type, offset, stride, count;
 	} vectors;
-	struct { 
-		unsigned char cmd_type, buf_idx, pad0, pad1; 
+	struct {
+		unsigned char cmd_type, buf_idx, pad0, pad1;
 	} dma;
-	struct { 
-		unsigned char cmd_type, flags, pad0, pad1; 
+	struct {
+		unsigned char cmd_type, flags, pad0, pad1;
 	} wait;
 } drm_radeon_cmd_header_t;
 
 #define RADEON_WAIT_2D  0x1
 #define RADEON_WAIT_3D  0x2
 
-
 #define RADEON_FRONT			0x1
 #define RADEON_BACK			0x2
 #define RADEON_DEPTH			0x4
@@ -234,7 +230,7 @@ typedef union {
 #define RADEON_OFFSET_ALIGN             (1 << RADEON_OFFSET_SHIFT)
 #define RADEON_OFFSET_MASK              (RADEON_OFFSET_ALIGN - 1)
 
-#endif /* __RADEON_SAREA_DEFINES__ */
+#endif				/* __RADEON_SAREA_DEFINES__ */
 
 typedef struct {
 	unsigned int red;
@@ -245,7 +241,7 @@ typedef struct {
 
 typedef struct {
 	/* Context state */
-	unsigned int pp_misc;				/* 0x1c14 */
+	unsigned int pp_misc;	/* 0x1c14 */
 	unsigned int pp_fog_color;
 	unsigned int re_solid_color;
 	unsigned int rb3d_blendcntl;
@@ -253,7 +249,7 @@ typedef struct {
 	unsigned int rb3d_depthpitch;
 	unsigned int rb3d_zstencilcntl;
 
-	unsigned int pp_cntl;				/* 0x1c38 */
+	unsigned int pp_cntl;	/* 0x1c38 */
 	unsigned int rb3d_cntl;
 	unsigned int rb3d_coloroffset;
 	unsigned int re_width_height;
@@ -261,27 +257,27 @@ typedef struct {
 	unsigned int se_cntl;
 
 	/* Vertex format state */
-	unsigned int se_coord_fmt;			/* 0x1c50 */
+	unsigned int se_coord_fmt;	/* 0x1c50 */
 
 	/* Line state */
-	unsigned int re_line_pattern;			/* 0x1cd0 */
+	unsigned int re_line_pattern;	/* 0x1cd0 */
 	unsigned int re_line_state;
 
-	unsigned int se_line_width;			/* 0x1db8 */
+	unsigned int se_line_width;	/* 0x1db8 */
 
 	/* Bumpmap state */
-	unsigned int pp_lum_matrix;			/* 0x1d00 */
+	unsigned int pp_lum_matrix;	/* 0x1d00 */
 
-	unsigned int pp_rot_matrix_0;			/* 0x1d58 */
+	unsigned int pp_rot_matrix_0;	/* 0x1d58 */
 	unsigned int pp_rot_matrix_1;
 
 	/* Mask state */
-	unsigned int rb3d_stencilrefmask;		/* 0x1d7c */
+	unsigned int rb3d_stencilrefmask;	/* 0x1d7c */
 	unsigned int rb3d_ropcntl;
 	unsigned int rb3d_planemask;
 
 	/* Viewport state */
-	unsigned int se_vport_xscale;			/* 0x1d98 */
+	unsigned int se_vport_xscale;	/* 0x1d98 */
 	unsigned int se_vport_xoffset;
 	unsigned int se_vport_yscale;
 	unsigned int se_vport_yoffset;
@@ -289,20 +285,19 @@ typedef struct {
 	unsigned int se_vport_zoffset;
 
 	/* Setup state */
-	unsigned int se_cntl_status;			/* 0x2140 */
+	unsigned int se_cntl_status;	/* 0x2140 */
 
 	/* Misc state */
-	unsigned int re_top_left;			/* 0x26c0 */
+	unsigned int re_top_left;	/* 0x26c0 */
 	unsigned int re_misc;
 } drm_radeon_context_regs_t;
 
 typedef struct {
 	/* Zbias state */
-	unsigned int se_zbias_factor;			/* 0x1dac */
+	unsigned int se_zbias_factor;	/* 0x1dac */
 	unsigned int se_zbias_constant;
 } drm_radeon_context2_regs_t;
 
-
 /* Setup registers for each texture unit
  */
 typedef struct {
@@ -320,11 +315,10 @@ typedef struct {
 	unsigned int finish;
 	unsigned int prim:8;
 	unsigned int stateidx:8;
-	unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
-        unsigned int vc_format;   /* vertex format */
+	unsigned int numverts:16;	/* overloaded as offset/64 for elt prims */
+	unsigned int vc_format;	/* vertex format */
 } drm_radeon_prim_t;
 
-
 typedef struct {
 	drm_radeon_context_regs_t context;
 	drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
@@ -332,7 +326,6 @@ typedef struct {
 	unsigned int dirty;
 } drm_radeon_state_t;
 
-
 typedef struct {
 	/* The channel for communication of state information to the
 	 * kernel on firing a vertex buffer with either of the
@@ -355,15 +348,15 @@ typedef struct {
 	unsigned int last_dispatch;
 	unsigned int last_clear;
 
-	drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
+	drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
+						       1];
 	unsigned int tex_age[RADEON_NR_TEX_HEAPS];
 	int ctx_owner;
-        int pfState;                /* number of 3d windows (0,1,2ormore) */
-        int pfCurrentPage;	    /* which buffer is being displayed? */
-	int crtc2_base;		    /* CRTC2 frame offset */
+	int pfState;		/* number of 3d windows (0,1,2ormore) */
+	int pfCurrentPage;	/* which buffer is being displayed? */
+	int crtc2_base;		/* CRTC2 frame offset */
 } drm_radeon_sarea_t;
 
-
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (xf86drmRadeon.h)
  *
@@ -373,15 +366,15 @@ typedef struct {
 /* Radeon specific ioctls
  * The device specific ioctl range is 0x40 to 0x79.
  */
-#define DRM_RADEON_CP_INIT    0x00 
-#define DRM_RADEON_CP_START   0x01 
+#define DRM_RADEON_CP_INIT    0x00
+#define DRM_RADEON_CP_START   0x01
 #define DRM_RADEON_CP_STOP    0x02
 #define DRM_RADEON_CP_RESET   0x03
 #define DRM_RADEON_CP_IDLE    0x04
-#define DRM_RADEON_RESET      0x05 
+#define DRM_RADEON_RESET      0x05
 #define DRM_RADEON_FULLSCREEN 0x06
-#define DRM_RADEON_SWAP       0x07 
-#define DRM_RADEON_CLEAR      0x08 
+#define DRM_RADEON_SWAP       0x07
+#define DRM_RADEON_CLEAR      0x08
 #define DRM_RADEON_VERTEX     0x09
 #define DRM_RADEON_INDICES    0x0A
 #define DRM_RADEON_NOT_USED
@@ -428,12 +421,12 @@ typedef struct {
 
 typedef struct drm_radeon_init {
 	enum {
-		RADEON_INIT_CP    = 0x01,
+		RADEON_INIT_CP = 0x01,
 		RADEON_CLEANUP_CP = 0x02,
 		RADEON_INIT_R200_CP = 0x03
 	} func;
 	unsigned long sarea_priv_offset;
-	int is_pci;	/* not used, driver asks hardware */
+	int is_pci;		/* not used, driver asks hardware */
 	int cp_mode;
 	int gart_size;
 	int ring_size;
@@ -460,7 +453,7 @@ typedef struct drm_radeon_cp_stop {
 
 typedef struct drm_radeon_fullscreen {
 	enum {
-		RADEON_INIT_FULLSCREEN    = 0x01,
+		RADEON_INIT_FULLSCREEN = 0x01,
 		RADEON_CLEANUP_FULLSCREEN = 0x02
 	} func;
 } drm_radeon_fullscreen_t;
@@ -481,15 +474,15 @@ typedef struct drm_radeon_clear {
 	unsigned int clear_color;
 	unsigned int clear_depth;
 	unsigned int color_mask;
-	unsigned int depth_mask;   /* misnamed field:  should be stencil */
+	unsigned int depth_mask;	/* misnamed field:  should be stencil */
 	drm_radeon_clear_rect_t __user *depth_boxes;
 } drm_radeon_clear_t;
 
 typedef struct drm_radeon_vertex {
 	int prim;
-	int idx;			/* Index of vertex buffer */
-	int count;			/* Number of vertices in buffer */
-	int discard;			/* Client finished with buffer? */
+	int idx;		/* Index of vertex buffer */
+	int count;		/* Number of vertices in buffer */
+	int discard;		/* Client finished with buffer? */
 } drm_radeon_vertex_t;
 
 typedef struct drm_radeon_indices {
@@ -497,7 +490,7 @@ typedef struct drm_radeon_indices {
 	int idx;
 	int start;
 	int end;
-	int discard;			/* Client finished with buffer? */
+	int discard;		/* Client finished with buffer? */
 } drm_radeon_indices_t;
 
 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
@@ -505,8 +498,8 @@ typedef struct drm_radeon_indices {
  *      - supports driver change to emit native primitives
  */
 typedef struct drm_radeon_vertex2 {
-	int idx;			/* Index of vertex buffer */
-	int discard;			/* Client finished with buffer? */
+	int idx;		/* Index of vertex buffer */
+	int discard;		/* Client finished with buffer? */
 	int nr_states;
 	drm_radeon_state_t __user *state;
 	int nr_prims;
@@ -514,10 +507,10 @@ typedef struct drm_radeon_vertex2 {
 } drm_radeon_vertex2_t;
 
 /* v1.3 - obsoletes drm_radeon_vertex2
- *      - allows arbitarily large cliprect list 
+ *      - allows arbitarily large cliprect list
  *      - allows updating of tcl packet, vector and scalar state
  *      - allows memory-efficient description of state updates
- *      - allows state to be emitted without a primitive 
+ *      - allows state to be emitted without a primitive
  *           (for clears, ctx switches)
  *      - allows more than one dma buffer to be referenced per ioctl
  *      - supports tcl driver
@@ -531,7 +524,7 @@ typedef struct drm_radeon_cmd_buffer {
 } drm_radeon_cmd_buffer_t;
 
 typedef struct drm_radeon_tex_image {
-	unsigned int x, y;		/* Blit coordinates */
+	unsigned int x, y;	/* Blit coordinates */
 	unsigned int width, height;
 	const void __user *data;
 } drm_radeon_tex_image_t;
@@ -540,7 +533,7 @@ typedef struct drm_radeon_texture {
 	unsigned int offset;
 	int pitch;
 	int format;
-	int width;			/* Texture image coordinates */
+	int width;		/* Texture image coordinates */
 	int height;
 	drm_radeon_tex_image_t __user *image;
 } drm_radeon_texture_t;
@@ -556,19 +549,18 @@ typedef struct drm_radeon_indirect {
 	int discard;
 } drm_radeon_indirect_t;
 
-
 /* 1.3: An ioctl to get parameters that aren't available to the 3d
- * client any other way.  
+ * client any other way.
  */
-#define RADEON_PARAM_GART_BUFFER_OFFSET    1 /* card offset of 1st GART buffer */
+#define RADEON_PARAM_GART_BUFFER_OFFSET    1	/* card offset of 1st GART buffer */
 #define RADEON_PARAM_LAST_FRAME            2
 #define RADEON_PARAM_LAST_DISPATCH         3
 #define RADEON_PARAM_LAST_CLEAR            4
 /* Added with DRM version 1.6. */
 #define RADEON_PARAM_IRQ_NR                5
-#define RADEON_PARAM_GART_BASE             6 /* card offset of GART base */
+#define RADEON_PARAM_GART_BASE             6	/* card offset of GART base */
 /* Added with DRM version 1.8. */
-#define RADEON_PARAM_REGISTER_HANDLE       7 /* for drmMap() */
+#define RADEON_PARAM_REGISTER_HANDLE       7	/* for drmMap() */
 #define RADEON_PARAM_STATUS_HANDLE         8
 #define RADEON_PARAM_SAREA_HANDLE          9
 #define RADEON_PARAM_GART_TEX_HANDLE       10
@@ -599,10 +591,9 @@ typedef struct drm_radeon_mem_free {
 typedef struct drm_radeon_mem_init_heap {
 	int region;
 	int size;
-	int start;	
+	int start;
 } drm_radeon_mem_init_heap_t;
 
-
 /* 1.6: Userspace can request & wait on irq's:
  */
 typedef struct drm_radeon_irq_emit {
@@ -613,17 +604,15 @@ typedef struct drm_radeon_irq_wait {
 	int irq_seq;
 } drm_radeon_irq_wait_t;
 
-
 /* 1.10: Clients tell the DRM where they think the framebuffer is located in
  * the card's address space, via a new generic ioctl to set parameters
  */
 
 typedef struct drm_radeon_setparam {
 	unsigned int param;
-	int64_t      value;
+	int64_t value;
 } drm_radeon_setparam_t;
 
-#define RADEON_SETPARAM_FB_LOCATION    1 /* determined framebuffer location */
-
+#define RADEON_SETPARAM_FB_LOCATION    1	/* determined framebuffer location */
 
 #endif
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 75c02e7a..6d96cf59 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -44,7 +44,6 @@
 #define DRIVER_MINOR		11
 #define DRIVER_PATCHLEVEL	0
 
-
 enum radeon_family {
 	CHIP_R100,
 	CHIP_RS100,
@@ -69,22 +68,22 @@ enum radeon_family {
  * Chip flags
  */
 enum radeon_chip_flags {
-	CHIP_FAMILY_MASK	= 0x0000ffffUL,
-	CHIP_FLAGS_MASK		= 0xffff0000UL,
-	CHIP_IS_MOBILITY	= 0x00010000UL,
-	CHIP_IS_IGP		= 0x00020000UL,
-	CHIP_SINGLE_CRTC	= 0x00040000UL,
-	CHIP_IS_AGP		= 0x00080000UL, 
+	CHIP_FAMILY_MASK = 0x0000ffffUL,
+	CHIP_FLAGS_MASK = 0xffff0000UL,
+	CHIP_IS_MOBILITY = 0x00010000UL,
+	CHIP_IS_IGP = 0x00020000UL,
+	CHIP_SINGLE_CRTC = 0x00040000UL,
+	CHIP_IS_AGP = 0x00080000UL,
 };
 
 #define GET_RING_HEAD(dev_priv)		DRM_READ32(  (dev_priv)->ring_rptr, 0 )
 #define SET_RING_HEAD(dev_priv,val)	DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
 
 typedef struct drm_radeon_freelist {
-   	unsigned int age;
-   	drm_buf_t *buf;
-   	struct drm_radeon_freelist *next;
-   	struct drm_radeon_freelist *prev;
+	unsigned int age;
+	drm_buf_t *buf;
+	struct drm_radeon_freelist *next;
+	struct drm_radeon_freelist *prev;
 } drm_radeon_freelist_t;
 
 typedef struct drm_radeon_ring_buffer {
@@ -132,8 +131,8 @@ typedef struct drm_radeon_private {
 	int cp_mode;
 	int cp_running;
 
-   	drm_radeon_freelist_t *head;
-   	drm_radeon_freelist_t *tail;
+	drm_radeon_freelist_t *head;
+	drm_radeon_freelist_t *tail;
 	int last_buf;
 	volatile u32 *scratch;
 	int writeback_works;
@@ -175,7 +174,7 @@ typedef struct drm_radeon_private {
 	u32 depth_pitch_offset;
 
 	drm_radeon_depth_clear_t depth_clear;
-	
+
 	unsigned long fb_offset;
 	unsigned long mmio_offset;
 	unsigned long ring_offset;
@@ -193,13 +192,13 @@ typedef struct drm_radeon_private {
 	struct mem_block *fb_heap;
 
 	/* SW interrupt */
-   	wait_queue_head_t swi_queue;
-   	atomic_t swi_emitted;
+	wait_queue_head_t swi_queue;
+	atomic_t swi_emitted;
 
 	/* starting from here on, data is preserved accross an open */
 	uint32_t flags;		/* see radeon_chip_flags */
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
-	struct radeon_i2c_chan 	i2c[4];
+	struct radeon_i2c_chan i2c[4];
 #endif
 } drm_radeon_private_t;
 
@@ -208,63 +207,66 @@ typedef struct drm_radeon_buf_priv {
 } drm_radeon_buf_priv_t;
 
 				/* radeon_cp.c */
-extern int radeon_cp_init( DRM_IOCTL_ARGS );
-extern int radeon_cp_start( DRM_IOCTL_ARGS );
-extern int radeon_cp_stop( DRM_IOCTL_ARGS );
-extern int radeon_cp_reset( DRM_IOCTL_ARGS );
-extern int radeon_cp_idle( DRM_IOCTL_ARGS );
-extern int radeon_cp_resume( DRM_IOCTL_ARGS );
-extern int radeon_engine_reset( DRM_IOCTL_ARGS );
-extern int radeon_fullscreen( DRM_IOCTL_ARGS );
-extern int radeon_cp_buffers( DRM_IOCTL_ARGS );
+extern int radeon_cp_init(DRM_IOCTL_ARGS);
+extern int radeon_cp_start(DRM_IOCTL_ARGS);
+extern int radeon_cp_stop(DRM_IOCTL_ARGS);
+extern int radeon_cp_reset(DRM_IOCTL_ARGS);
+extern int radeon_cp_idle(DRM_IOCTL_ARGS);
+extern int radeon_cp_resume(DRM_IOCTL_ARGS);
+extern int radeon_engine_reset(DRM_IOCTL_ARGS);
+extern int radeon_fullscreen(DRM_IOCTL_ARGS);
+extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
 
-extern void radeon_freelist_reset( drm_device_t *dev );
-extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
+extern void radeon_freelist_reset(drm_device_t * dev);
+extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
 
-extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
+extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
 
-extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
-extern int radeon_do_cleanup_cp( drm_device_t *dev );
-extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
+extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
+extern int radeon_do_cleanup_cp(drm_device_t * dev);
+extern int radeon_do_cleanup_pageflip(drm_device_t * dev);
 
 				/* radeon_state.c */
-extern int radeon_cp_clear( DRM_IOCTL_ARGS );
-extern int radeon_cp_swap( DRM_IOCTL_ARGS );
-extern int radeon_cp_vertex( DRM_IOCTL_ARGS );
-extern int radeon_cp_indices( DRM_IOCTL_ARGS );
-extern int radeon_cp_texture( DRM_IOCTL_ARGS );
-extern int radeon_cp_stipple( DRM_IOCTL_ARGS );
-extern int radeon_cp_indirect( DRM_IOCTL_ARGS );
-extern int radeon_cp_vertex2( DRM_IOCTL_ARGS );
-extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS );
-extern int radeon_cp_getparam( DRM_IOCTL_ARGS );
-extern int radeon_cp_setparam( DRM_IOCTL_ARGS );
-extern int radeon_cp_flip( DRM_IOCTL_ARGS );
-
-extern int radeon_mem_alloc( DRM_IOCTL_ARGS );
-extern int radeon_mem_free( DRM_IOCTL_ARGS );
-extern int radeon_mem_init_heap( DRM_IOCTL_ARGS );
-extern void radeon_mem_takedown( struct mem_block **heap );
-extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap );
+extern int radeon_cp_clear(DRM_IOCTL_ARGS);
+extern int radeon_cp_swap(DRM_IOCTL_ARGS);
+extern int radeon_cp_vertex(DRM_IOCTL_ARGS);
+extern int radeon_cp_indices(DRM_IOCTL_ARGS);
+extern int radeon_cp_texture(DRM_IOCTL_ARGS);
+extern int radeon_cp_stipple(DRM_IOCTL_ARGS);
+extern int radeon_cp_indirect(DRM_IOCTL_ARGS);
+extern int radeon_cp_vertex2(DRM_IOCTL_ARGS);
+extern int radeon_cp_cmdbuf(DRM_IOCTL_ARGS);
+extern int radeon_cp_getparam(DRM_IOCTL_ARGS);
+extern int radeon_cp_setparam(DRM_IOCTL_ARGS);
+extern int radeon_cp_flip(DRM_IOCTL_ARGS);
+
+extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
+extern int radeon_mem_free(DRM_IOCTL_ARGS);
+extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
+extern void radeon_mem_takedown(struct mem_block **heap);
+extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
 
 				/* radeon_irq.c */
-extern int radeon_irq_emit( DRM_IOCTL_ARGS );
-extern int radeon_irq_wait( DRM_IOCTL_ARGS );
-
-extern int radeon_emit_and_wait_irq(drm_device_t *dev);
-extern int radeon_wait_irq(drm_device_t *dev, int swi_nr);
-extern int radeon_emit_irq(drm_device_t *dev);
-
-extern void radeon_do_release(drm_device_t *dev);
-extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
-extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS );
-extern void radeon_driver_irq_preinstall( drm_device_t *dev );
-extern void radeon_driver_irq_postinstall( drm_device_t *dev );
-extern void radeon_driver_irq_uninstall( drm_device_t *dev );
-extern void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp);
-extern void radeon_driver_pretakedown(drm_device_t *dev);
-extern int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv);
-extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv);
+extern int radeon_irq_emit(DRM_IOCTL_ARGS);
+extern int radeon_irq_wait(DRM_IOCTL_ARGS);
+
+extern int radeon_emit_and_wait_irq(drm_device_t * dev);
+extern int radeon_wait_irq(drm_device_t * dev, int swi_nr);
+extern int radeon_emit_irq(drm_device_t * dev);
+
+extern void radeon_do_release(drm_device_t * dev);
+extern int radeon_driver_vblank_wait(drm_device_t * dev,
+				     unsigned int *sequence);
+extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
+extern void radeon_driver_irq_preinstall(drm_device_t * dev);
+extern void radeon_driver_irq_postinstall(drm_device_t * dev);
+extern void radeon_driver_irq_uninstall(drm_device_t * dev);
+extern void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp);
+extern void radeon_driver_pretakedown(drm_device_t * dev);
+extern int radeon_driver_open_helper(drm_device_t * dev,
+				     drm_file_t * filp_priv);
+extern void radeon_driver_free_filp_priv(drm_device_t * dev,
+					 drm_file_t * filp_priv);
 
 /* Flags for stats.boxes
  */
@@ -278,7 +280,7 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri
  * for Radeon kernel driver.
  */
 #define RADEON_AGP_COMMAND		0x0f60
-#define RADEON_AGP_COMMAND_PCI_CONFIG	0x0060		/* offset in PCI config*/
+#define RADEON_AGP_COMMAND_PCI_CONFIG	0x0060	/* offset in PCI config */
 #       define RADEON_AGP_ENABLE            (1<<8)
 
 #define RADEON_AUX_SCISSOR_CNTL		0x26f0
@@ -350,7 +352,6 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri
 				? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
 				: RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
 
-
 #define RADEON_GEN_INT_CNTL		0x0040
 #	define RADEON_CRTC_VBLANK_MASK		(1 << 0)
 #	define RADEON_GUI_IDLE_INT_ENABLE	(1 << 19)
@@ -551,7 +552,6 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri
 #	define RADEON_DEPTH_FORMAT_16BIT_INT_Z	(0 << 0)
 #	define RADEON_DEPTH_FORMAT_24BIT_INT_Z	(2 << 0)
 
-
 /* CP registers */
 #define RADEON_CP_ME_RAM_ADDR		0x07d4
 #define RADEON_CP_ME_RAM_RADDR		0x07d8
@@ -668,19 +668,19 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri
 #define R200_PP_TXCBLEND_5                0x2f50
 #define R200_PP_TXCBLEND_6                0x2f60
 #define R200_PP_TXCBLEND_7                0x2f70
-#define R200_SE_TCL_LIGHT_MODEL_CTL_0     0x2268 
+#define R200_SE_TCL_LIGHT_MODEL_CTL_0     0x2268
 #define R200_PP_TFACTOR_0                 0x2ee0
 #define R200_SE_VTX_FMT_0                 0x2088
 #define R200_SE_VAP_CNTL                  0x2080
 #define R200_SE_TCL_MATRIX_SEL_0          0x2230
-#define R200_SE_TCL_TEX_PROC_CTL_2        0x22a8 
-#define R200_SE_TCL_UCP_VERT_BLEND_CTL    0x22c0 
-#define R200_PP_TXFILTER_5                0x2ca0 
-#define R200_PP_TXFILTER_4                0x2c80 
-#define R200_PP_TXFILTER_3                0x2c60 
-#define R200_PP_TXFILTER_2                0x2c40 
-#define R200_PP_TXFILTER_1                0x2c20 
-#define R200_PP_TXFILTER_0                0x2c00 
+#define R200_SE_TCL_TEX_PROC_CTL_2        0x22a8
+#define R200_SE_TCL_UCP_VERT_BLEND_CTL    0x22c0
+#define R200_PP_TXFILTER_5                0x2ca0
+#define R200_PP_TXFILTER_4                0x2c80
+#define R200_PP_TXFILTER_3                0x2c60
+#define R200_PP_TXFILTER_2                0x2c40
+#define R200_PP_TXFILTER_1                0x2c20
+#define R200_PP_TXFILTER_0                0x2c00
 #define R200_PP_TXOFFSET_5                0x2d78
 #define R200_PP_TXOFFSET_4                0x2d60
 #define R200_PP_TXOFFSET_3                0x2d48
@@ -734,17 +734,16 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri
 #define R200_RE_SCISSOR_TL_0              0x1cd8
 #define R200_RE_SCISSOR_TL_1              0x1ce0
 #define R200_RE_SCISSOR_TL_2              0x1ce8
-#define R200_RB3D_DEPTHXY_OFFSET          0x1d60 
+#define R200_RB3D_DEPTHXY_OFFSET          0x1d60
 #define R200_RE_AUX_SCISSOR_CNTL          0x26f0
 #define R200_SE_VTX_STATE_CNTL            0x2180
 #define R200_RE_POINTSIZE                 0x2648
 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
 
-#define RADEON_PP_TEX_SIZE_0                0x1d04  /* NPOT */
+#define RADEON_PP_TEX_SIZE_0                0x1d04	/* NPOT */
 #define RADEON_PP_TEX_SIZE_1                0x1d0c
 #define RADEON_PP_TEX_SIZE_2                0x1d14
 
-
 #define SE_VAP_CNTL__TCL_ENA_MASK                          0x00000001
 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK                   0x00010000
 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT                 0x00000012
@@ -755,7 +754,7 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri
 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT               0x0000000b
 #define R200_3D_DRAW_IMMD_2      0xC0003500
 #define R200_SE_VTX_FMT_1                 0x208c
-#define R200_RE_CNTL                      0x1c50 
+#define R200_RE_CNTL                      0x1c50
 
 #define R200_RB3D_BLENDCOLOR              0x3218
 
@@ -785,10 +784,10 @@ do {									\
 	RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) );			\
 } while (0)
 
-extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
-extern int radeon_preinit( struct drm_device *dev, unsigned long flags );
-extern int radeon_postinit( struct drm_device *dev, unsigned long flags );
-extern int radeon_postcleanup( struct drm_device *dev );
+extern int RADEON_READ_PLL(drm_device_t * dev, int addr);
+extern int radeon_preinit(struct drm_device *dev, unsigned long flags);
+extern int radeon_postinit(struct drm_device *dev, unsigned long flags);
+extern int radeon_postcleanup(struct drm_device *dev);
 
 #define CP_PACKET0( reg, n )						\
 	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
@@ -801,7 +800,6 @@ extern int radeon_postcleanup( struct drm_device *dev );
 #define CP_PACKET3( pkt, n )						\
 	(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
 
-
 /* ================================================================
  * Engine control helper macros
  */
@@ -850,12 +848,11 @@ extern int radeon_postcleanup( struct drm_device *dev );
 	OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );				\
 } while (0)
 
-
 /* ================================================================
  * Misc helper macros
  */
 
-/* Perfbox functionality only.  
+/* Perfbox functionality only.
  */
 #define RING_SPACE_TEST_WITH_RETURN( dev_priv )				\
 do {									\
@@ -892,7 +889,6 @@ do {									\
 	OUT_RING( age );						\
 } while (0)
 
-
 /* ================================================================
  * Ring control
  */
@@ -953,7 +949,6 @@ do {									\
 	OUT_RING( val );						\
 } while (0)
 
-
 #define OUT_RING_USER_TABLE( tab, sz ) do {			\
 	int _size = (sz);					\
 	int __user *_tab = (tab);					\
@@ -976,5 +971,4 @@ do {									\
 	write &= mask;						\
 } while (0)
 
-
-#endif /* __RADEON_DRV_H__ */
+#endif				/* __RADEON_DRV_H__ */
diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c
index b7deca73..b48a7552 100644
--- a/shared-core/radeon_irq.c
+++ b/shared-core/radeon_irq.c
@@ -1,7 +1,7 @@
 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*-
  *
  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
- * 
+ *
  * The Weather Channel (TM) funded Tungsten Graphics to develop the
  * initial release of the Radeon 8500 driver under the XFree86 license.
  * This notice must be preserved.
@@ -53,31 +53,31 @@
  * tied to dma at all, this is just a hangover from dri prehistory.
  */
 
-irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS )
+irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 {
 	drm_device_t *dev = (drm_device_t *) arg;
-	drm_radeon_private_t *dev_priv = 
-	   (drm_radeon_private_t *)dev->dev_private;
-   	u32 stat;
+	drm_radeon_private_t *dev_priv =
+	    (drm_radeon_private_t *) dev->dev_private;
+	u32 stat;
 
 	/* Only consider the bits we're interested in - others could be used
 	 * outside the DRM
 	 */
 	stat = RADEON_READ(RADEON_GEN_INT_STATUS)
-	     & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
+	    & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
 	if (!stat)
 		return IRQ_NONE;
 
 	/* SW interrupt */
 	if (stat & RADEON_SW_INT_TEST) {
-		DRM_WAKEUP( &dev_priv->swi_queue );
+		DRM_WAKEUP(&dev_priv->swi_queue);
 	}
 
 	/* VBLANK interrupt */
 	if (stat & RADEON_CRTC_VBLANK_STAT) {
 		atomic_inc(&dev->vbl_received);
 		DRM_WAKEUP(&dev->vbl_queue);
-		drm_vbl_send_signals( dev );
+		drm_vbl_send_signals(dev);
 	}
 
 	/* Acknowledge interrupts we handle */
@@ -85,15 +85,15 @@ irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS )
 	return IRQ_HANDLED;
 }
 
-static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv)
+static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv)
 {
-	u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS )
-		& (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
+	u32 tmp = RADEON_READ(RADEON_GEN_INT_STATUS)
+	    & (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
 	if (tmp)
-		RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp );
+		RADEON_WRITE(RADEON_GEN_INT_STATUS, tmp);
 }
 
-int radeon_emit_irq(drm_device_t *dev)
+int radeon_emit_irq(drm_device_t * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	unsigned int ret;
@@ -102,156 +102,153 @@ int radeon_emit_irq(drm_device_t *dev)
 	atomic_inc(&dev_priv->swi_emitted);
 	ret = atomic_read(&dev_priv->swi_emitted);
 
-	BEGIN_RING( 4 );
-	OUT_RING_REG( RADEON_LAST_SWI_REG, ret );
-	OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE );
-	ADVANCE_RING(); 
- 	COMMIT_RING();
+	BEGIN_RING(4);
+	OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
+	OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
+	ADVANCE_RING();
+	COMMIT_RING();
 
 	return ret;
 }
 
-
-int radeon_wait_irq(drm_device_t *dev, int swi_nr)
+int radeon_wait_irq(drm_device_t * dev, int swi_nr)
 {
-  	drm_radeon_private_t *dev_priv = 
-	   (drm_radeon_private_t *)dev->dev_private;
+	drm_radeon_private_t *dev_priv =
+	    (drm_radeon_private_t *) dev->dev_private;
 	int ret = 0;
 
- 	if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr)  
- 		return 0; 
+	if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
+		return 0;
 
 	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
 	/* This is a hack to work around mysterious freezes on certain
 	 * systems:
-	 */ 
-	radeon_acknowledge_irqs( dev_priv );
+	 */
+	radeon_acknowledge_irqs(dev_priv);
 
-	DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ, 
-		     RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr );
+	DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
+		    RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 
 	return ret;
 }
 
-int radeon_emit_and_wait_irq(drm_device_t *dev)
+int radeon_emit_and_wait_irq(drm_device_t * dev)
 {
-	return radeon_wait_irq( dev, radeon_emit_irq(dev) );
+	return radeon_wait_irq(dev, radeon_emit_irq(dev));
 }
 
-
-int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
+int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
 {
-  	drm_radeon_private_t *dev_priv = 
-	   (drm_radeon_private_t *)dev->dev_private;
+	drm_radeon_private_t *dev_priv =
+	    (drm_radeon_private_t *) dev->dev_private;
 	unsigned int cur_vblank;
 	int ret = 0;
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	radeon_acknowledge_irqs( dev_priv );
+	radeon_acknowledge_irqs(dev_priv);
 
 	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
 	/* Assume that the user has missed the current sequence number
 	 * by about a day rather than she wants to wait for years
-	 * using vertical blanks... 
+	 * using vertical blanks...
 	 */
-	DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, 
-		     ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
-			 - *sequence ) <= (1<<23) ) );
+	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
+		    (((cur_vblank = atomic_read(&dev->vbl_received))
+		      - *sequence) <= (1 << 23)));
 
 	*sequence = cur_vblank;
 
 	return ret;
 }
 
-
 /* Needs the lock as it touches the ring.
  */
-int radeon_irq_emit( DRM_IOCTL_ARGS )
+int radeon_irq_emit(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_irq_emit_t emit;
 	int result;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t __user *)data,
-				  sizeof(emit) );
+	DRM_COPY_FROM_USER_IOCTL(emit, (drm_radeon_irq_emit_t __user *) data,
+				 sizeof(emit));
 
-	result = radeon_emit_irq( dev );
+	result = radeon_emit_irq(dev);
 
-	if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
-		DRM_ERROR( "copy_to_user\n" );
+	if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) {
+		DRM_ERROR("copy_to_user\n");
 		return DRM_ERR(EFAULT);
 	}
 
 	return 0;
 }
 
-
 /* Doesn't need the hardware lock.
  */
-int radeon_irq_wait( DRM_IOCTL_ARGS )
+int radeon_irq_wait(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_irq_wait_t irqwait;
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t __user*)data,
-				  sizeof(irqwait) );
+	DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_radeon_irq_wait_t __user *) data,
+				 sizeof(irqwait));
 
-	return radeon_wait_irq( dev, irqwait.irq_seq );
+	return radeon_wait_irq(dev, irqwait.irq_seq);
 }
 
-
 /* drm_dma.h hooks
 */
-void radeon_driver_irq_preinstall( drm_device_t *dev ) {
+void radeon_driver_irq_preinstall(drm_device_t * dev)
+{
 	drm_radeon_private_t *dev_priv =
-		(drm_radeon_private_t *)dev->dev_private;
+	    (drm_radeon_private_t *) dev->dev_private;
 
- 	/* Disable *all* interrupts */
-      	RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
+	/* Disable *all* interrupts */
+	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 
 	/* Clear bits if they're already high */
-	radeon_acknowledge_irqs( dev_priv );
+	radeon_acknowledge_irqs(dev_priv);
 }
 
-void radeon_driver_irq_postinstall( drm_device_t *dev ) {
+void radeon_driver_irq_postinstall(drm_device_t * dev)
+{
 	drm_radeon_private_t *dev_priv =
-		(drm_radeon_private_t *)dev->dev_private;
+	    (drm_radeon_private_t *) dev->dev_private;
 
-   	atomic_set(&dev_priv->swi_emitted, 0);
-	DRM_INIT_WAITQUEUE( &dev_priv->swi_queue );
+	atomic_set(&dev_priv->swi_emitted, 0);
+	DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 
 	/* Turn on SW and VBL ints */
-   	RADEON_WRITE( RADEON_GEN_INT_CNTL,
-		      RADEON_CRTC_VBLANK_MASK |	
-		      RADEON_SW_INT_ENABLE );
+	RADEON_WRITE(RADEON_GEN_INT_CNTL,
+		     RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE);
 }
 
-void radeon_driver_irq_uninstall( drm_device_t *dev ) {
+void radeon_driver_irq_uninstall(drm_device_t * dev)
+{
 	drm_radeon_private_t *dev_priv =
-		(drm_radeon_private_t *)dev->dev_private;
+	    (drm_radeon_private_t *) dev->dev_private;
 	if (!dev_priv)
 		return;
 
 	/* Disable *all* interrupts */
-	RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
+	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 }
diff --git a/shared-core/radeon_mem.c b/shared-core/radeon_mem.c
index 17483dd1..7cecd7ee 100644
--- a/shared-core/radeon_mem.c
+++ b/shared-core/radeon_mem.c
@@ -1,7 +1,7 @@
 /* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*-
  *
  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
- * 
+ *
  * The Weather Channel (TM) funded Tungsten Graphics to develop the
  * initial release of the Radeon 8500 driver under the XFree86 license.
  * This notice must be preserved.
@@ -35,16 +35,17 @@
 #include "radeon_drv.h"
 
 /* Very simple allocator for GART memory, working on a static range
- * already mapped into each client's address space.  
+ * already mapped into each client's address space.
  */
 
 static struct mem_block *split_block(struct mem_block *p, int start, int size,
-				     DRMFILE filp )
+				     DRMFILE filp)
 {
 	/* Maybe cut off the start of an existing block */
 	if (start > p->start) {
-		struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFS );
-		if (!newblock) 
+		struct mem_block *newblock =
+		    drm_alloc(sizeof(*newblock), DRM_MEM_BUFS);
+		if (!newblock)
 			goto out;
 		newblock->start = start;
 		newblock->size = p->size - (start - p->start);
@@ -56,10 +57,11 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size,
 		p->size -= newblock->size;
 		p = newblock;
 	}
-   
+
 	/* Maybe cut off the end of an existing block */
 	if (size < p->size) {
-		struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFS );
+		struct mem_block *newblock =
+		    drm_alloc(sizeof(*newblock), DRM_MEM_BUFS);
 		if (!newblock)
 			goto out;
 		newblock->start = start + size;
@@ -72,40 +74,39 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size,
 		p->size = size;
 	}
 
- out:
+      out:
 	/* Our block is in the middle */
 	p->filp = filp;
 	return p;
 }
 
-static struct mem_block *alloc_block( struct mem_block *heap, int size, 
-				      int align2, DRMFILE filp )
+static struct mem_block *alloc_block(struct mem_block *heap, int size,
+				     int align2, DRMFILE filp)
 {
 	struct mem_block *p;
-	int mask = (1 << align2)-1;
+	int mask = (1 << align2) - 1;
 
-	for (p = heap->next ; p != heap ; p = p->next) {
+	for (p = heap->next; p != heap; p = p->next) {
 		int start = (p->start + mask) & ~mask;
 		if (p->filp == 0 && start + size <= p->start + p->size)
-			return split_block( p, start, size, filp );
+			return split_block(p, start, size, filp);
 	}
 
 	return NULL;
 }
 
-static struct mem_block *find_block( struct mem_block *heap, int start )
+static struct mem_block *find_block(struct mem_block *heap, int start)
 {
 	struct mem_block *p;
 
-	for (p = heap->next ; p != heap ; p = p->next) 
+	for (p = heap->next; p != heap; p = p->next)
 		if (p->start == start)
 			return p;
 
 	return NULL;
 }
 
-
-static void free_block( struct mem_block *p )
+static void free_block(struct mem_block *p)
 {
 	p->filp = NULL;
 
@@ -117,7 +118,7 @@ static void free_block( struct mem_block *p )
 		p->size += q->size;
 		p->next = q->next;
 		p->next->prev = p;
-		drm_free(q, sizeof(*q), DRM_MEM_BUFS );
+		drm_free(q, sizeof(*q), DRM_MEM_BUFS);
 	}
 
 	if (p->prev->filp == 0) {
@@ -125,7 +126,7 @@ static void free_block( struct mem_block *p )
 		q->size += p->size;
 		q->next = p->next;
 		q->next->prev = q;
-		drm_free(p, sizeof(*q), DRM_MEM_BUFS );
+		drm_free(p, sizeof(*q), DRM_MEM_BUFS);
 	}
 }
 
@@ -133,14 +134,14 @@ static void free_block( struct mem_block *p )
  */
 static int init_heap(struct mem_block **heap, int start, int size)
 {
-	struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS );
+	struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS);
 
-	if (!blocks) 
+	if (!blocks)
 		return DRM_ERR(ENOMEM);
-	
-	*heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS );
+
+	*heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS);
 	if (!*heap) {
-		drm_free( blocks, sizeof(*blocks), DRM_MEM_BUFS );
+		drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFS);
 		return DRM_ERR(ENOMEM);
 	}
 
@@ -149,70 +150,66 @@ static int init_heap(struct mem_block **heap, int start, int size)
 	blocks->filp = NULL;
 	blocks->next = blocks->prev = *heap;
 
-	memset( *heap, 0, sizeof(**heap) );
-	(*heap)->filp = (DRMFILE) -1;
+	memset(*heap, 0, sizeof(**heap));
+	(*heap)->filp = (DRMFILE) - 1;
 	(*heap)->next = (*heap)->prev = blocks;
 	return 0;
 }
 
-
 /* Free all blocks associated with the releasing file.
  */
-void radeon_mem_release( DRMFILE filp, struct mem_block *heap )
+void radeon_mem_release(DRMFILE filp, struct mem_block *heap)
 {
 	struct mem_block *p;
 
 	if (!heap || !heap->next)
 		return;
 
-	for (p = heap->next ; p != heap ; p = p->next) {
-		if (p->filp == filp) 
+	for (p = heap->next; p != heap; p = p->next) {
+		if (p->filp == filp)
 			p->filp = NULL;
 	}
 
 	/* Assumes a single contiguous range.  Needs a special filp in
 	 * 'heap' to stop it being subsumed.
 	 */
-	for (p = heap->next ; p != heap ; p = p->next) {
+	for (p = heap->next; p != heap; p = p->next) {
 		while (p->filp == 0 && p->next->filp == 0) {
 			struct mem_block *q = p->next;
 			p->size += q->size;
 			p->next = q->next;
 			p->next->prev = p;
-			drm_free(q, sizeof(*q),DRM_MEM_DRIVER);
+			drm_free(q, sizeof(*q), DRM_MEM_DRIVER);
 		}
 	}
 }
 
 /* Shutdown.
  */
-void radeon_mem_takedown( struct mem_block **heap )
+void radeon_mem_takedown(struct mem_block **heap)
 {
 	struct mem_block *p;
-	
+
 	if (!*heap)
 		return;
 
-	for (p = (*heap)->next ; p != *heap ; ) {
+	for (p = (*heap)->next; p != *heap;) {
 		struct mem_block *q = p;
 		p = p->next;
-		drm_free(q, sizeof(*q),DRM_MEM_DRIVER);
+		drm_free(q, sizeof(*q), DRM_MEM_DRIVER);
 	}
 
-	drm_free( *heap, sizeof(**heap),DRM_MEM_DRIVER );
+	drm_free(*heap, sizeof(**heap), DRM_MEM_DRIVER);
 	*heap = NULL;
 }
 
-
-
 /* IOCTL HANDLERS */
 
-static struct mem_block **get_heap( drm_radeon_private_t *dev_priv,
-				   int region )
+static struct mem_block **get_heap(drm_radeon_private_t * dev_priv, int region)
 {
-	switch( region ) {
+	switch (region) {
 	case RADEON_MEM_REGION_GART:
- 		return &dev_priv->gart_heap; 
+		return &dev_priv->gart_heap;
 	case RADEON_MEM_REGION_FB:
 		return &dev_priv->fb_heap;
 	default:
@@ -220,103 +217,98 @@ static struct mem_block **get_heap( drm_radeon_private_t *dev_priv,
 	}
 }
 
-int radeon_mem_alloc( DRM_IOCTL_ARGS )
+int radeon_mem_alloc(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_mem_alloc_t alloc;
 	struct mem_block *block, **heap;
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( alloc, (drm_radeon_mem_alloc_t __user *)data,
-				  sizeof(alloc) );
+	DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_mem_alloc_t __user *) data,
+				 sizeof(alloc));
 
-	heap = get_heap( dev_priv, alloc.region );
+	heap = get_heap(dev_priv, alloc.region);
 	if (!heap || !*heap)
 		return DRM_ERR(EFAULT);
-	
+
 	/* Make things easier on ourselves: all allocations at least
 	 * 4k aligned.
 	 */
 	if (alloc.alignment < 12)
 		alloc.alignment = 12;
 
-	block = alloc_block( *heap, alloc.size, alloc.alignment,
-			     filp );
+	block = alloc_block(*heap, alloc.size, alloc.alignment, filp);
 
-	if (!block) 
+	if (!block)
 		return DRM_ERR(ENOMEM);
 
-	if ( DRM_COPY_TO_USER( alloc.region_offset, &block->start, 
-			       sizeof(int) ) ) {
-		DRM_ERROR( "copy_to_user\n" );
+	if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) {
+		DRM_ERROR("copy_to_user\n");
 		return DRM_ERR(EFAULT);
 	}
-	
+
 	return 0;
 }
 
-
-
-int radeon_mem_free( DRM_IOCTL_ARGS )
+int radeon_mem_free(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_mem_free_t memfree;
 	struct mem_block *block, **heap;
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( memfree, (drm_radeon_mem_free_t __user *)data,
-				  sizeof(memfree) );
+	DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data,
+				 sizeof(memfree));
 
-	heap = get_heap( dev_priv, memfree.region );
+	heap = get_heap(dev_priv, memfree.region);
 	if (!heap || !*heap)
 		return DRM_ERR(EFAULT);
-	
-	block = find_block( *heap, memfree.region_offset );
+
+	block = find_block(*heap, memfree.region_offset);
 	if (!block)
 		return DRM_ERR(EFAULT);
 
 	if (block->filp != filp)
 		return DRM_ERR(EPERM);
 
-	free_block( block );	
+	free_block(block);
 	return 0;
 }
 
-int radeon_mem_init_heap( DRM_IOCTL_ARGS )
+int radeon_mem_init_heap(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_mem_init_heap_t initheap;
 	struct mem_block **heap;
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( initheap, (drm_radeon_mem_init_heap_t __user *)data,
-				  sizeof(initheap) );
+	DRM_COPY_FROM_USER_IOCTL(initheap,
+				 (drm_radeon_mem_init_heap_t __user *) data,
+				 sizeof(initheap));
 
-	heap = get_heap( dev_priv, initheap.region );
-	if (!heap) 
+	heap = get_heap(dev_priv, initheap.region);
+	if (!heap)
 		return DRM_ERR(EFAULT);
-	
+
 	if (*heap) {
 		DRM_ERROR("heap already initialized?");
 		return DRM_ERR(EFAULT);
 	}
-		
-	return init_heap( heap, initheap.start, initheap.size );
-}
-
 
+	return init_heap(heap, initheap.start, initheap.size);
+}
diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index 35fb16e9..325ce070 100644
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -33,72 +33,74 @@
 #include "radeon_drm.h"
 #include "radeon_drv.h"
 
-
 /* ================================================================
  * Helper functions for client state checking and fixup
  */
 
-static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_priv,
-						     drm_file_t *filp_priv,
-						     u32 *offset ) {
+static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
+						    dev_priv,
+						    drm_file_t * filp_priv,
+						    u32 * offset)
+{
 	u32 off = *offset;
 	struct drm_radeon_driver_file_fields *radeon_priv;
 
-	if ( off >= dev_priv->fb_location &&
-	     off < ( dev_priv->gart_vm_start + dev_priv->gart_size ) )
+	if (off >= dev_priv->fb_location &&
+	    off < (dev_priv->gart_vm_start + dev_priv->gart_size))
 		return 0;
 
 	radeon_priv = filp_priv->driver_priv;
 
 	off += radeon_priv->radeon_fb_delta;
 
-	DRM_DEBUG( "offset fixed up to 0x%x\n", off );
+	DRM_DEBUG("offset fixed up to 0x%x\n", off);
 
-	if ( off < dev_priv->fb_location ||
-	     off >= ( dev_priv->gart_vm_start + dev_priv->gart_size ) )
-		return DRM_ERR( EINVAL );
+	if (off < dev_priv->fb_location ||
+	    off >= (dev_priv->gart_vm_start + dev_priv->gart_size))
+		return DRM_ERR(EINVAL);
 
 	*offset = off;
 
 	return 0;
 }
 
-static __inline__ int radeon_check_and_fixup_offset_user( drm_radeon_private_t *dev_priv,
-							  drm_file_t *filp_priv,
-							  u32 __user *offset ) {
+static __inline__ int radeon_check_and_fixup_offset_user(drm_radeon_private_t *
+							 dev_priv,
+							 drm_file_t * filp_priv,
+							 u32 __user * offset)
+{
 	u32 off;
 
-	DRM_GET_USER_UNCHECKED( off, offset );
+	DRM_GET_USER_UNCHECKED(off, offset);
 
-	if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &off ) )
-		return DRM_ERR( EINVAL );
+	if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &off))
+		return DRM_ERR(EINVAL);
 
-	DRM_PUT_USER_UNCHECKED( offset, off );
+	DRM_PUT_USER_UNCHECKED(offset, off);
 
 	return 0;
 }
 
-static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv,
-						      drm_file_t *filp_priv,
-						      int id,
-						      u32 __user *data ) {
-	switch ( id ) {
+static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
+						     dev_priv,
+						     drm_file_t * filp_priv,
+						     int id, u32 __user * data)
+{
+	switch (id) {
 
 	case RADEON_EMIT_PP_MISC:
-		if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-							 &data[( RADEON_RB3D_DEPTHOFFSET
-								 - RADEON_PP_MISC ) / 4] ) ) {
-			DRM_ERROR( "Invalid depth buffer offset\n" );
-			return DRM_ERR( EINVAL );
+		if (radeon_check_and_fixup_offset_user(dev_priv, filp_priv,
+						       &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) {
+			DRM_ERROR("Invalid depth buffer offset\n");
+			return DRM_ERR(EINVAL);
 		}
 		break;
 
 	case RADEON_EMIT_PP_CNTL:
-		if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-							 &data[( RADEON_RB3D_COLOROFFSET
-								 - RADEON_PP_CNTL ) / 4] ) ) {
-			DRM_ERROR( "Invalid colour buffer offset\n" );
-			return DRM_ERR( EINVAL );
+		if (radeon_check_and_fixup_offset_user(dev_priv, filp_priv,
+						       &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) {
+			DRM_ERROR("Invalid colour buffer offset\n");
+			return DRM_ERR(EINVAL);
 		}
 		break;
 
@@ -108,21 +110,20 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
 	case R200_EMIT_PP_TXOFFSET_3:
 	case R200_EMIT_PP_TXOFFSET_4:
 	case R200_EMIT_PP_TXOFFSET_5:
-		if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-							 &data[0] ) ) {
-			DRM_ERROR( "Invalid R200 texture offset\n" );
-			return DRM_ERR( EINVAL );
+		if (radeon_check_and_fixup_offset_user(dev_priv, filp_priv,
+						       &data[0])) {
+			DRM_ERROR("Invalid R200 texture offset\n");
+			return DRM_ERR(EINVAL);
 		}
 		break;
 
 	case RADEON_EMIT_PP_TXFILTER_0:
 	case RADEON_EMIT_PP_TXFILTER_1:
 	case RADEON_EMIT_PP_TXFILTER_2:
-		if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-							 &data[( RADEON_PP_TXOFFSET_0
-								 - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
-			DRM_ERROR( "Invalid R100 texture offset\n" );
-			return DRM_ERR( EINVAL );
+		if (radeon_check_and_fixup_offset_user(dev_priv, filp_priv,
+						       &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) {
+			DRM_ERROR("Invalid R100 texture offset\n");
+			return DRM_ERR(EINVAL);
 		}
 		break;
 
@@ -131,18 +132,20 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
 	case R200_EMIT_PP_CUBIC_OFFSETS_2:
 	case R200_EMIT_PP_CUBIC_OFFSETS_3:
 	case R200_EMIT_PP_CUBIC_OFFSETS_4:
-	case R200_EMIT_PP_CUBIC_OFFSETS_5: {
-		int i;
-		for ( i = 0; i < 5; i++ ) {
-			if ( radeon_check_and_fixup_offset_user( dev_priv,
-								 filp_priv,
-								 &data[i] ) ) {
-				DRM_ERROR( "Invalid R200 cubic texture offset\n" );
-				return DRM_ERR( EINVAL );
+	case R200_EMIT_PP_CUBIC_OFFSETS_5:{
+			int i;
+			for (i = 0; i < 5; i++) {
+				if (radeon_check_and_fixup_offset_user(dev_priv,
+								       filp_priv,
+								       &data
+								       [i])) {
+					DRM_ERROR
+					    ("Invalid R200 cubic texture offset\n");
+					return DRM_ERR(EINVAL);
+				}
 			}
+			break;
 		}
-		break;
-	}
 
 	case RADEON_EMIT_RB3D_COLORPITCH:
 	case RADEON_EMIT_RE_LINE_PATTERN:
@@ -208,254 +211,258 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
 		break;
 
 	default:
-		DRM_ERROR( "Unknown state packet ID %d\n", id );
-		return DRM_ERR( EINVAL );
+		DRM_ERROR("Unknown state packet ID %d\n", id);
+		return DRM_ERR(EINVAL);
 	}
 
 	return 0;
 }
 
-static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_priv,
-						      drm_file_t *filp_priv,
-						      drm_radeon_cmd_buffer_t *cmdbuf,
-						      unsigned int *cmdsz ) {
+static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
+						     dev_priv,
+						     drm_file_t * filp_priv,
+						     drm_radeon_cmd_buffer_t *
+						     cmdbuf,
+						     unsigned int *cmdsz)
+{
 	u32 tmp[4];
-	u32 __user *cmd = (u32 __user *)cmdbuf->buf;
+	u32 __user *cmd = (u32 __user *) cmdbuf->buf;
 
-	if ( DRM_COPY_FROM_USER_UNCHECKED( tmp, cmd, sizeof( tmp ) ) ) {
-		DRM_ERROR( "Failed to copy data from user space\n" );
-		return DRM_ERR( EFAULT );
+	if (DRM_COPY_FROM_USER_UNCHECKED(tmp, cmd, sizeof(tmp))) {
+		DRM_ERROR("Failed to copy data from user space\n");
+		return DRM_ERR(EFAULT);
 	}
 
-	*cmdsz = 2 + ( ( tmp[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 );
+	*cmdsz = 2 + ((tmp[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
 
-	if ( ( tmp[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) {
-		DRM_ERROR( "Not a type 3 packet\n" );
-		return DRM_ERR( EINVAL );
+	if ((tmp[0] & 0xc0000000) != RADEON_CP_PACKET3) {
+		DRM_ERROR("Not a type 3 packet\n");
+		return DRM_ERR(EINVAL);
 	}
 
-	if ( 4 * *cmdsz > cmdbuf->bufsz ) {
-		DRM_ERROR( "Packet size larger than size of data provided\n" );
-		return DRM_ERR( EINVAL );
+	if (4 * *cmdsz > cmdbuf->bufsz) {
+		DRM_ERROR("Packet size larger than size of data provided\n");
+		return DRM_ERR(EINVAL);
 	}
 
 	/* Check client state and fix it up if necessary */
-	if ( tmp[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */
+	if (tmp[0] & 0x8000) {	/* MSB of opcode: next DWORD GUI_CNTL */
 		u32 offset;
 
-		if ( tmp[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL
-			      | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
+		if (tmp[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
+			      | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
 			offset = tmp[2] << 10;
-			if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) {
-				DRM_ERROR( "Invalid first packet offset\n" );
-				return DRM_ERR( EINVAL );
+			if (radeon_check_and_fixup_offset
+			    (dev_priv, filp_priv, &offset)) {
+				DRM_ERROR("Invalid first packet offset\n");
+				return DRM_ERR(EINVAL);
 			}
-			tmp[2] = ( tmp[2] & 0xffc00000 ) | offset >> 10;
+			tmp[2] = (tmp[2] & 0xffc00000) | offset >> 10;
 		}
 
-		if ( ( tmp[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) &&
-		     ( tmp[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
+		if ((tmp[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
+		    (tmp[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
 			offset = tmp[3] << 10;
-			if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) {
-				DRM_ERROR( "Invalid second packet offset\n" );
-				return DRM_ERR( EINVAL );
+			if (radeon_check_and_fixup_offset
+			    (dev_priv, filp_priv, &offset)) {
+				DRM_ERROR("Invalid second packet offset\n");
+				return DRM_ERR(EINVAL);
 			}
-			tmp[3] = ( tmp[3] & 0xffc00000 ) | offset >> 10;
+			tmp[3] = (tmp[3] & 0xffc00000) | offset >> 10;
 		}
 
-		if ( DRM_COPY_TO_USER_UNCHECKED( cmd, tmp, sizeof( tmp ) ) ) {
-			DRM_ERROR( "Failed to copy data to user space\n" );
-			return DRM_ERR( EFAULT );
+		if (DRM_COPY_TO_USER_UNCHECKED(cmd, tmp, sizeof(tmp))) {
+			DRM_ERROR("Failed to copy data to user space\n");
+			return DRM_ERR(EFAULT);
 		}
 	}
 
 	return 0;
 }
 
-
 /* ================================================================
  * CP hardware state programming functions
  */
 
-static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
-					  drm_clip_rect_t *box )
+static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
+					     drm_clip_rect_t * box)
 {
 	RING_LOCALS;
 
-	DRM_DEBUG( "   box:  x1=%d y1=%d  x2=%d y2=%d\n",
-		   box->x1, box->y1, box->x2, box->y2 );
+	DRM_DEBUG("   box:  x1=%d y1=%d  x2=%d y2=%d\n",
+		  box->x1, box->y1, box->x2, box->y2);
 
-	BEGIN_RING( 4 );
-	OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
-	OUT_RING( (box->y1 << 16) | box->x1 );
-	OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
-	OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );
+	BEGIN_RING(4);
+	OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
+	OUT_RING((box->y1 << 16) | box->x1);
+	OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
+	OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
 	ADVANCE_RING();
 }
 
 /* Emit 1.1 state
  */
-static int radeon_emit_state( drm_radeon_private_t *dev_priv,
-			      drm_file_t *filp_priv,
-			      drm_radeon_context_regs_t *ctx,
-			      drm_radeon_texture_regs_t *tex,
-			      unsigned int dirty )
+static int radeon_emit_state(drm_radeon_private_t * dev_priv,
+			     drm_file_t * filp_priv,
+			     drm_radeon_context_regs_t * ctx,
+			     drm_radeon_texture_regs_t * tex,
+			     unsigned int dirty)
 {
 	RING_LOCALS;
-	DRM_DEBUG( "dirty=0x%08x\n", dirty );
+	DRM_DEBUG("dirty=0x%08x\n", dirty);
 
-	if ( dirty & RADEON_UPLOAD_CONTEXT ) {
-		if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
-						    &ctx->rb3d_depthoffset ) ) {
-			DRM_ERROR( "Invalid depth buffer offset\n" );
-			return DRM_ERR( EINVAL );
+	if (dirty & RADEON_UPLOAD_CONTEXT) {
+		if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
+						  &ctx->rb3d_depthoffset)) {
+			DRM_ERROR("Invalid depth buffer offset\n");
+			return DRM_ERR(EINVAL);
 		}
 
-		if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
-						    &ctx->rb3d_coloroffset ) ) {
-			DRM_ERROR( "Invalid depth buffer offset\n" );
-			return DRM_ERR( EINVAL );
+		if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
+						  &ctx->rb3d_coloroffset)) {
+			DRM_ERROR("Invalid depth buffer offset\n");
+			return DRM_ERR(EINVAL);
 		}
 
-		BEGIN_RING( 14 );
-		OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) );
-		OUT_RING( ctx->pp_misc );
-		OUT_RING( ctx->pp_fog_color );
-		OUT_RING( ctx->re_solid_color );
-		OUT_RING( ctx->rb3d_blendcntl );
-		OUT_RING( ctx->rb3d_depthoffset );
-		OUT_RING( ctx->rb3d_depthpitch );
-		OUT_RING( ctx->rb3d_zstencilcntl );
-		OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) );
-		OUT_RING( ctx->pp_cntl );
-		OUT_RING( ctx->rb3d_cntl );
-		OUT_RING( ctx->rb3d_coloroffset );
-		OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) );
-		OUT_RING( ctx->rb3d_colorpitch );
+		BEGIN_RING(14);
+		OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
+		OUT_RING(ctx->pp_misc);
+		OUT_RING(ctx->pp_fog_color);
+		OUT_RING(ctx->re_solid_color);
+		OUT_RING(ctx->rb3d_blendcntl);
+		OUT_RING(ctx->rb3d_depthoffset);
+		OUT_RING(ctx->rb3d_depthpitch);
+		OUT_RING(ctx->rb3d_zstencilcntl);
+		OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
+		OUT_RING(ctx->pp_cntl);
+		OUT_RING(ctx->rb3d_cntl);
+		OUT_RING(ctx->rb3d_coloroffset);
+		OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
+		OUT_RING(ctx->rb3d_colorpitch);
 		ADVANCE_RING();
 	}
 
-	if ( dirty & RADEON_UPLOAD_VERTFMT ) {
-		BEGIN_RING( 2 );
-		OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) );
-		OUT_RING( ctx->se_coord_fmt );
+	if (dirty & RADEON_UPLOAD_VERTFMT) {
+		BEGIN_RING(2);
+		OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
+		OUT_RING(ctx->se_coord_fmt);
 		ADVANCE_RING();
 	}
 
-	if ( dirty & RADEON_UPLOAD_LINE ) {
-		BEGIN_RING( 5 );
-		OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) );
-		OUT_RING( ctx->re_line_pattern );
-		OUT_RING( ctx->re_line_state );
-		OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) );
-		OUT_RING( ctx->se_line_width );
+	if (dirty & RADEON_UPLOAD_LINE) {
+		BEGIN_RING(5);
+		OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
+		OUT_RING(ctx->re_line_pattern);
+		OUT_RING(ctx->re_line_state);
+		OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
+		OUT_RING(ctx->se_line_width);
 		ADVANCE_RING();
 	}
 
-	if ( dirty & RADEON_UPLOAD_BUMPMAP ) {
-		BEGIN_RING( 5 );
-		OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) );
-		OUT_RING( ctx->pp_lum_matrix );
-		OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) );
-		OUT_RING( ctx->pp_rot_matrix_0 );
-		OUT_RING( ctx->pp_rot_matrix_1 );
+	if (dirty & RADEON_UPLOAD_BUMPMAP) {
+		BEGIN_RING(5);
+		OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
+		OUT_RING(ctx->pp_lum_matrix);
+		OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
+		OUT_RING(ctx->pp_rot_matrix_0);
+		OUT_RING(ctx->pp_rot_matrix_1);
 		ADVANCE_RING();
 	}
 
-	if ( dirty & RADEON_UPLOAD_MASKS ) {
-		BEGIN_RING( 4 );
-		OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) );
-		OUT_RING( ctx->rb3d_stencilrefmask );
-		OUT_RING( ctx->rb3d_ropcntl );
-		OUT_RING( ctx->rb3d_planemask );
+	if (dirty & RADEON_UPLOAD_MASKS) {
+		BEGIN_RING(4);
+		OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
+		OUT_RING(ctx->rb3d_stencilrefmask);
+		OUT_RING(ctx->rb3d_ropcntl);
+		OUT_RING(ctx->rb3d_planemask);
 		ADVANCE_RING();
 	}
 
-	if ( dirty & RADEON_UPLOAD_VIEWPORT ) {
-		BEGIN_RING( 7 );
-		OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) );
-		OUT_RING( ctx->se_vport_xscale );
-		OUT_RING( ctx->se_vport_xoffset );
-		OUT_RING( ctx->se_vport_yscale );
-		OUT_RING( ctx->se_vport_yoffset );
-		OUT_RING( ctx->se_vport_zscale );
-		OUT_RING( ctx->se_vport_zoffset );
+	if (dirty & RADEON_UPLOAD_VIEWPORT) {
+		BEGIN_RING(7);
+		OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
+		OUT_RING(ctx->se_vport_xscale);
+		OUT_RING(ctx->se_vport_xoffset);
+		OUT_RING(ctx->se_vport_yscale);
+		OUT_RING(ctx->se_vport_yoffset);
+		OUT_RING(ctx->se_vport_zscale);
+		OUT_RING(ctx->se_vport_zoffset);
 		ADVANCE_RING();
 	}
 
-	if ( dirty & RADEON_UPLOAD_SETUP ) {
-		BEGIN_RING( 4 );
-		OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
-		OUT_RING( ctx->se_cntl );
-		OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
-		OUT_RING( ctx->se_cntl_status );
+	if (dirty & RADEON_UPLOAD_SETUP) {
+		BEGIN_RING(4);
+		OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
+		OUT_RING(ctx->se_cntl);
+		OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
+		OUT_RING(ctx->se_cntl_status);
 		ADVANCE_RING();
 	}
 
-	if ( dirty & RADEON_UPLOAD_MISC ) {
-		BEGIN_RING( 2 );
-		OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) );
-		OUT_RING( ctx->re_misc );
+	if (dirty & RADEON_UPLOAD_MISC) {
+		BEGIN_RING(2);
+		OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
+		OUT_RING(ctx->re_misc);
 		ADVANCE_RING();
 	}
 
-	if ( dirty & RADEON_UPLOAD_TEX0 ) {
-		if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
-						    &tex[0].pp_txoffset ) ) {
-			DRM_ERROR( "Invalid texture offset for unit 0\n" );
-			return DRM_ERR( EINVAL );
+	if (dirty & RADEON_UPLOAD_TEX0) {
+		if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
+						  &tex[0].pp_txoffset)) {
+			DRM_ERROR("Invalid texture offset for unit 0\n");
+			return DRM_ERR(EINVAL);
 		}
 
-		BEGIN_RING( 9 );
-		OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
-		OUT_RING( tex[0].pp_txfilter );
-		OUT_RING( tex[0].pp_txformat );
-		OUT_RING( tex[0].pp_txoffset );
-		OUT_RING( tex[0].pp_txcblend );
-		OUT_RING( tex[0].pp_txablend );
-		OUT_RING( tex[0].pp_tfactor );
-		OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
-		OUT_RING( tex[0].pp_border_color );
+		BEGIN_RING(9);
+		OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
+		OUT_RING(tex[0].pp_txfilter);
+		OUT_RING(tex[0].pp_txformat);
+		OUT_RING(tex[0].pp_txoffset);
+		OUT_RING(tex[0].pp_txcblend);
+		OUT_RING(tex[0].pp_txablend);
+		OUT_RING(tex[0].pp_tfactor);
+		OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
+		OUT_RING(tex[0].pp_border_color);
 		ADVANCE_RING();
 	}
 
-	if ( dirty & RADEON_UPLOAD_TEX1 ) {
-		if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
-						    &tex[1].pp_txoffset ) ) {
-			DRM_ERROR( "Invalid texture offset for unit 1\n" );
-			return DRM_ERR( EINVAL );
+	if (dirty & RADEON_UPLOAD_TEX1) {
+		if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
+						  &tex[1].pp_txoffset)) {
+			DRM_ERROR("Invalid texture offset for unit 1\n");
+			return DRM_ERR(EINVAL);
 		}
 
-		BEGIN_RING( 9 );
-		OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
-		OUT_RING( tex[1].pp_txfilter );
-		OUT_RING( tex[1].pp_txformat );
-		OUT_RING( tex[1].pp_txoffset );
-		OUT_RING( tex[1].pp_txcblend );
-		OUT_RING( tex[1].pp_txablend );
-		OUT_RING( tex[1].pp_tfactor );
-		OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
-		OUT_RING( tex[1].pp_border_color );
+		BEGIN_RING(9);
+		OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
+		OUT_RING(tex[1].pp_txfilter);
+		OUT_RING(tex[1].pp_txformat);
+		OUT_RING(tex[1].pp_txoffset);
+		OUT_RING(tex[1].pp_txcblend);
+		OUT_RING(tex[1].pp_txablend);
+		OUT_RING(tex[1].pp_tfactor);
+		OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
+		OUT_RING(tex[1].pp_border_color);
 		ADVANCE_RING();
 	}
 
-	if ( dirty & RADEON_UPLOAD_TEX2 ) {
-		if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
-						    &tex[2].pp_txoffset ) ) {
-			DRM_ERROR( "Invalid texture offset for unit 2\n" );
-			return DRM_ERR( EINVAL );
+	if (dirty & RADEON_UPLOAD_TEX2) {
+		if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
+						  &tex[2].pp_txoffset)) {
+			DRM_ERROR("Invalid texture offset for unit 2\n");
+			return DRM_ERR(EINVAL);
 		}
 
-		BEGIN_RING( 9 );
-		OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
-		OUT_RING( tex[2].pp_txfilter );
-		OUT_RING( tex[2].pp_txformat );
-		OUT_RING( tex[2].pp_txoffset );
-		OUT_RING( tex[2].pp_txcblend );
-		OUT_RING( tex[2].pp_txablend );
-		OUT_RING( tex[2].pp_tfactor );
-		OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
-		OUT_RING( tex[2].pp_border_color );
+		BEGIN_RING(9);
+		OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
+		OUT_RING(tex[2].pp_txfilter);
+		OUT_RING(tex[2].pp_txformat);
+		OUT_RING(tex[2].pp_txoffset);
+		OUT_RING(tex[2].pp_txcblend);
+		OUT_RING(tex[2].pp_txablend);
+		OUT_RING(tex[2].pp_tfactor);
+		OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
+		OUT_RING(tex[2].pp_border_color);
 		ADVANCE_RING();
 	}
 
@@ -464,121 +471,125 @@ static int radeon_emit_state( drm_radeon_private_t *dev_priv,
 
 /* Emit 1.2 state
  */
-static int radeon_emit_state2( drm_radeon_private_t *dev_priv,
-			       drm_file_t *filp_priv,
-			       drm_radeon_state_t *state )
+static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
+			      drm_file_t * filp_priv,
+			      drm_radeon_state_t * state)
 {
 	RING_LOCALS;
 
 	if (state->dirty & RADEON_UPLOAD_ZBIAS) {
-		BEGIN_RING( 3 );
-		OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) );
-		OUT_RING( state->context2.se_zbias_factor ); 
-		OUT_RING( state->context2.se_zbias_constant ); 
+		BEGIN_RING(3);
+		OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
+		OUT_RING(state->context2.se_zbias_factor);
+		OUT_RING(state->context2.se_zbias_constant);
 		ADVANCE_RING();
 	}
 
-	return radeon_emit_state( dev_priv, filp_priv, &state->context,
-			   state->tex, state->dirty );
+	return radeon_emit_state(dev_priv, filp_priv, &state->context,
+				 state->tex, state->dirty);
 }
 
 /* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
  * 1.3 cmdbuffers allow all previous state to be updated as well as
- * the tcl scalar and vector areas.  
+ * the tcl scalar and vector areas.
  */
-static struct { 
-	int start; 
-	int len; 
+static struct {
+	int start;
+	int len;
 	const char *name;
 } packet[RADEON_MAX_STATE_PACKETS] = {
-	{ RADEON_PP_MISC,7,"RADEON_PP_MISC" },
-	{ RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
-	{ RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
-	{ RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
-	{ RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
-	{ RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
-	{ RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
-	{ RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
-	{ RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
-	{ RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
-	{ RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
-	{ RADEON_RE_MISC,1,"RADEON_RE_MISC" },
-	{ RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
-	{ RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
-	{ RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
-	{ RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
-	{ RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
-	{ RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
-	{ RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
-	{ RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
-	{ RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
-	{ R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" },
-	{ R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
-	{ R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
-	{ R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
-	{ R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
-	{ R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
-	{ R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
-	{ R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
-	{ R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
-	{ R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
-	{ R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
-	{ R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
-	{ R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
-	{ R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
-	{ R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
-	{ R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
-	{ R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
-	{ R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
-	{ R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
-	{ R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
-	{ R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
-	{ R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
-	{ R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
-	{ R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
-	{ R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
-	{ R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
-	{ R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
-	{ R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
-	{ R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
-	{ R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
-	{ R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, 
-	{ R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, 
-	{ R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, 
-	{ R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, 
-	{ R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, 
-	{ R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, 
-	{ R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, 
-	{ R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, 
-	{ R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, 
-	{ R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
-	{ R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
-	{ R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
-	{ R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" },
-	{ R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
-	{ R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" },
-	{ R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
-	{ R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" },
-	{ R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
-	{ R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" },
-	{ R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
-	{ R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
-	{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
-	{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
-	{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
-	{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
-	{ R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
-};
-
-
+	{
+	RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, {
+	RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, {
+	RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, {
+	RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, {
+	RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, {
+	RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, {
+	RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, {
+	RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, {
+	RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, {
+	RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, {
+	RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, {
+	RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, {
+	RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, {
+	RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, {
+	RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, {
+	RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, {
+	RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, {
+	RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, {
+	RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, {
+	RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, {
+	RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
+		    "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, {
+	R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, {
+	R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, {
+	R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, {
+	R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, {
+	R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, {
+	R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, {
+	R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, {
+	R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, {
+	R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
+	{
+	R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, {
+	R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, {
+	R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, {
+	R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, {
+	R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, {
+	R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
+	{
+	R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, {
+	R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, {
+	R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, {
+	R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, {
+	R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, {
+	R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, {
+	R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, {
+	R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, {
+	R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, {
+	R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, {
+	R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, {
+	R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, {
+	R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, {
+	R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
+	{
+	R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, {
+	R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, {
+	R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, {
+	R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, {
+	R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, {
+	R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, {
+	R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, {
+	R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, {
+	R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, {
+	R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, {
+	R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
+		    "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, {
+	R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"},	/* 61 */
+	{
+	R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"},	/* 62 */
+	{
+	R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, {
+	R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, {
+	R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, {
+	R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, {
+	R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, {
+	R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, {
+	R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, {
+	R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, {
+	R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, {
+	R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, {
+	RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, {
+	RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, {
+	RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, {
+R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},};
 
 /* ================================================================
  * Performance monitoring functions
  */
 
-static void radeon_clear_box( drm_radeon_private_t *dev_priv,
-			      int x, int y, int w, int h,
-			      int r, int g, int b )
+static void radeon_clear_box(drm_radeon_private_t * dev_priv,
+			     int x, int y, int w, int h, int r, int g, int b)
 {
 	u32 color;
 	RING_LOCALS;
@@ -586,49 +597,47 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
 	x += dev_priv->sarea_priv->boxes[0].x1;
 	y += dev_priv->sarea_priv->boxes[0].y1;
 
-	switch ( dev_priv->color_fmt ) {
+	switch (dev_priv->color_fmt) {
 	case RADEON_COLOR_FORMAT_RGB565:
 		color = (((r & 0xf8) << 8) |
-			 ((g & 0xfc) << 3) |
-			 ((b & 0xf8) >> 3));
+			 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
 		break;
 	case RADEON_COLOR_FORMAT_ARGB8888:
 	default:
-		color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
+		color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
 		break;
 	}
 
-	BEGIN_RING( 4 );
-	RADEON_WAIT_UNTIL_3D_IDLE();		
-	OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
-	OUT_RING( 0xffffffff );
+	BEGIN_RING(4);
+	RADEON_WAIT_UNTIL_3D_IDLE();
+	OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
+	OUT_RING(0xffffffff);
 	ADVANCE_RING();
 
-	BEGIN_RING( 6 );
+	BEGIN_RING(6);
 
-	OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
-	OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-		  RADEON_GMC_BRUSH_SOLID_COLOR |
-		  (dev_priv->color_fmt << 8) |
-		  RADEON_GMC_SRC_DATATYPE_COLOR |
-		  RADEON_ROP3_P |
-		  RADEON_GMC_CLR_CMP_CNTL_DIS );
+	OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
+	OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+		 RADEON_GMC_BRUSH_SOLID_COLOR |
+		 (dev_priv->color_fmt << 8) |
+		 RADEON_GMC_SRC_DATATYPE_COLOR |
+		 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
 
- 	if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { 
-		OUT_RING( dev_priv->front_pitch_offset );
- 	} else {	 
-		OUT_RING( dev_priv->back_pitch_offset );
- 	} 
+	if (dev_priv->page_flipping && dev_priv->current_page == 1) {
+		OUT_RING(dev_priv->front_pitch_offset);
+	} else {
+		OUT_RING(dev_priv->back_pitch_offset);
+	}
 
-	OUT_RING( color );
+	OUT_RING(color);
 
-	OUT_RING( (x << 16) | y );
-	OUT_RING( (w << 16) | h );
+	OUT_RING((x << 16) | y);
+	OUT_RING((w << 16) | h);
 
 	ADVANCE_RING();
 }
 
-static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
+static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
 {
 	/* Collapse various things into a wait flag -- trying to
 	 * guess if userspase slept -- better just to have them tell us.
@@ -644,50 +653,50 @@ static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
 
 	/* Purple box for page flipping
 	 */
-	if ( dev_priv->stats.boxes & RADEON_BOX_FLIP ) 
-		radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 );
+	if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
+		radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);
 
 	/* Red box if we have to wait for idle at any point
 	 */
-	if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE ) 
-		radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 );
+	if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
+		radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);
 
 	/* Blue box: lost context?
 	 */
 
 	/* Yellow box for texture swaps
 	 */
-	if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD ) 
-		radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 );
+	if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
+		radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);
 
 	/* Green box if hardware never idles (as far as we can tell)
 	 */
-	if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) ) 
-		radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
+	if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
+		radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
 
-
-	/* Draw bars indicating number of buffers allocated 
+	/* Draw bars indicating number of buffers allocated
 	 * (not a great measure, easily confused)
 	 */
 	if (dev_priv->stats.requested_bufs) {
 		if (dev_priv->stats.requested_bufs > 100)
 			dev_priv->stats.requested_bufs = 100;
 
-		radeon_clear_box( dev_priv, 4, 16,  
-				  dev_priv->stats.requested_bufs, 4,
-				  196, 128, 128 );
+		radeon_clear_box(dev_priv, 4, 16,
+				 dev_priv->stats.requested_bufs, 4,
+				 196, 128, 128);
 	}
 
-	memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) );
+	memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
 
 }
+
 /* ================================================================
  * CP command dispatch functions
  */
 
-static void radeon_cp_dispatch_clear( drm_device_t *dev,
-				      drm_radeon_clear_t *clear,
-				      drm_radeon_clear_rect_t *depth_boxes )
+static void radeon_cp_dispatch_clear(drm_device_t * dev,
+				     drm_radeon_clear_t * clear,
+				     drm_radeon_clear_rect_t * depth_boxes)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -695,32 +704,34 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 	int nbox = sarea_priv->nbox;
 	drm_clip_rect_t *pbox = sarea_priv->boxes;
 	unsigned int flags = clear->flags;
-	u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0;
+	u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
 	int i;
 	RING_LOCALS;
-	DRM_DEBUG( "flags = 0x%x\n", flags );
+	DRM_DEBUG("flags = 0x%x\n", flags);
 
 	dev_priv->stats.clears++;
 
-	if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
+	if (dev_priv->page_flipping && dev_priv->current_page == 1) {
 		unsigned int tmp = flags;
 
 		flags &= ~(RADEON_FRONT | RADEON_BACK);
-		if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK;
-		if ( tmp & RADEON_BACK )  flags |= RADEON_FRONT;
+		if (tmp & RADEON_FRONT)
+			flags |= RADEON_BACK;
+		if (tmp & RADEON_BACK)
+			flags |= RADEON_FRONT;
 	}
 
-	if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
+	if (flags & (RADEON_FRONT | RADEON_BACK)) {
 
-		BEGIN_RING( 4 );
+		BEGIN_RING(4);
 
 		/* Ensure the 3D stream is idle before doing a
 		 * 2D fill to clear the front or back buffer.
 		 */
 		RADEON_WAIT_UNTIL_3D_IDLE();
-		
-		OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
-		OUT_RING( clear->color_mask );
+
+		OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
+		OUT_RING(clear->color_mask);
 
 		ADVANCE_RING();
 
@@ -728,51 +739,55 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 		 */
 		dev_priv->sarea_priv->ctx_owner = 0;
 
-		for ( i = 0 ; i < nbox ; i++ ) {
+		for (i = 0; i < nbox; i++) {
 			int x = pbox[i].x1;
 			int y = pbox[i].y1;
 			int w = pbox[i].x2 - x;
 			int h = pbox[i].y2 - y;
 
-			DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
-				   x, y, w, h, flags );
-
-			if ( flags & RADEON_FRONT ) {
-				BEGIN_RING( 6 );
-				
-				OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
-				OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-					  RADEON_GMC_BRUSH_SOLID_COLOR |
-					  (dev_priv->color_fmt << 8) |
-					  RADEON_GMC_SRC_DATATYPE_COLOR |
-					  RADEON_ROP3_P |
-					  RADEON_GMC_CLR_CMP_CNTL_DIS );
-
-				OUT_RING( dev_priv->front_pitch_offset );
-				OUT_RING( clear->clear_color );
-				
-				OUT_RING( (x << 16) | y );
-				OUT_RING( (w << 16) | h );
-				
+			DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
+				  x, y, w, h, flags);
+
+			if (flags & RADEON_FRONT) {
+				BEGIN_RING(6);
+
+				OUT_RING(CP_PACKET3
+					 (RADEON_CNTL_PAINT_MULTI, 4));
+				OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+					 RADEON_GMC_BRUSH_SOLID_COLOR |
+					 (dev_priv->
+					  color_fmt << 8) |
+					 RADEON_GMC_SRC_DATATYPE_COLOR |
+					 RADEON_ROP3_P |
+					 RADEON_GMC_CLR_CMP_CNTL_DIS);
+
+				OUT_RING(dev_priv->front_pitch_offset);
+				OUT_RING(clear->clear_color);
+
+				OUT_RING((x << 16) | y);
+				OUT_RING((w << 16) | h);
+
 				ADVANCE_RING();
 			}
-			
-			if ( flags & RADEON_BACK ) {
-				BEGIN_RING( 6 );
-				
-				OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
-				OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-					  RADEON_GMC_BRUSH_SOLID_COLOR |
-					  (dev_priv->color_fmt << 8) |
-					  RADEON_GMC_SRC_DATATYPE_COLOR |
-					  RADEON_ROP3_P |
-					  RADEON_GMC_CLR_CMP_CNTL_DIS );
-				
-				OUT_RING( dev_priv->back_pitch_offset );
-				OUT_RING( clear->clear_color );
-
-				OUT_RING( (x << 16) | y );
-				OUT_RING( (w << 16) | h );
+
+			if (flags & RADEON_BACK) {
+				BEGIN_RING(6);
+
+				OUT_RING(CP_PACKET3
+					 (RADEON_CNTL_PAINT_MULTI, 4));
+				OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+					 RADEON_GMC_BRUSH_SOLID_COLOR |
+					 (dev_priv->
+					  color_fmt << 8) |
+					 RADEON_GMC_SRC_DATATYPE_COLOR |
+					 RADEON_ROP3_P |
+					 RADEON_GMC_CLR_CMP_CNTL_DIS);
+
+				OUT_RING(dev_priv->back_pitch_offset);
+				OUT_RING(clear->clear_color);
+
+				OUT_RING((x << 16) | y);
+				OUT_RING((w << 16) | h);
 
 				ADVANCE_RING();
 			}
@@ -783,8 +798,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 	 * rendering a quad into just those buffers.  Thus, we have to
 	 * make sure the 3D engine is configured correctly.
 	 */
-	if ( dev_priv->is_r200 &&
-	     (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
+	if (dev_priv->is_r200 && (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
 
 		int tempPP_CNTL;
 		int tempRE_CNTL;
@@ -803,37 +817,34 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 		tempRE_CNTL = 0;
 
 		tempRB3D_CNTL = depth_clear->rb3d_cntl;
-		tempRB3D_CNTL &= ~(1<<15); /* unset radeon magic flag */
+		tempRB3D_CNTL &= ~(1 << 15);	/* unset radeon magic flag */
 
 		tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
 		tempRB3D_STENCILREFMASK = 0x0;
 
 		tempSE_CNTL = depth_clear->se_cntl;
 
-
-
 		/* Disable TCL */
 
-		tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK |  */
-				   (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
+		tempSE_VAP_CNTL = (	/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK |  */
+					  (0x9 <<
+					   SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
 
 		tempRB3D_PLANEMASK = 0x0;
 
 		tempRE_AUX_SCISSOR_CNTL = 0x0;
 
 		tempSE_VTE_CNTL =
-			SE_VTE_CNTL__VTX_XY_FMT_MASK |
-			SE_VTE_CNTL__VTX_Z_FMT_MASK;
+		    SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
 
-		/* Vertex format (X, Y, Z, W)*/
+		/* Vertex format (X, Y, Z, W) */
 		tempSE_VTX_FMT_0 =
-			SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
-			SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
+		    SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
+		    SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
 		tempSE_VTX_FMT_1 = 0x0;
 
-
-		/* 
-		 * Depth buffer specific enables 
+		/*
+		 * Depth buffer specific enables
 		 */
 		if (flags & RADEON_DEPTH) {
 			/* Enable depth buffer */
@@ -843,142 +854,133 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 			tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
 		}
 
-		/* 
+		/*
 		 * Stencil buffer specific enables
 		 */
-		if ( flags & RADEON_STENCIL ) {
-			tempRB3D_CNTL |=  RADEON_STENCIL_ENABLE;
-			tempRB3D_STENCILREFMASK = clear->depth_mask; 
+		if (flags & RADEON_STENCIL) {
+			tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
+			tempRB3D_STENCILREFMASK = clear->depth_mask;
 		} else {
 			tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
 			tempRB3D_STENCILREFMASK = 0x00000000;
 		}
 
-		BEGIN_RING( 26 );
+		BEGIN_RING(26);
 		RADEON_WAIT_UNTIL_2D_IDLE();
 
-		OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL );
-		OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL );
-		OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL );
-		OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
-			      tempRB3D_ZSTENCILCNTL );
-		OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, 
-			      tempRB3D_STENCILREFMASK );
-		OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK );
-		OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL );
-		OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL );
-		OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 );
-		OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 );
-		OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL );
-		OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL, 
-			      tempRE_AUX_SCISSOR_CNTL );
+		OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
+		OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
+		OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
+		OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
+		OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
+			     tempRB3D_STENCILREFMASK);
+		OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
+		OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
+		OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
+		OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
+		OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
+		OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
+		OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
 		ADVANCE_RING();
 
 		/* Make sure we restore the 3D state next time.
 		 */
 		dev_priv->sarea_priv->ctx_owner = 0;
 
-		for ( i = 0 ; i < nbox ; i++ ) {
-			
-			/* Funny that this should be required -- 
+		for (i = 0; i < nbox; i++) {
+
+			/* Funny that this should be required --
 			 *  sets top-left?
 			 */
-			radeon_emit_clip_rect( dev_priv,
-					       &sarea_priv->boxes[i] );
-
-			BEGIN_RING( 14 );
-			OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) );
-			OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
-				   RADEON_PRIM_WALK_RING |
-				   (3 << RADEON_NUM_VERTICES_SHIFT)) );
-			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x3f800000 );
-			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x3f800000 );
-			OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x3f800000 );
+			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
+
+			BEGIN_RING(14);
+			OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
+			OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
+				  RADEON_PRIM_WALK_RING |
+				  (3 << RADEON_NUM_VERTICES_SHIFT)));
+			OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
+			OUT_RING(0x3f800000);
+			OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
+			OUT_RING(0x3f800000);
+			OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
+			OUT_RING(0x3f800000);
 			ADVANCE_RING();
 		}
-	} 
-	else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
+	} else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
 
 		rb3d_cntl = depth_clear->rb3d_cntl;
 
-		if ( flags & RADEON_DEPTH ) {
-			rb3d_cntl |=  RADEON_Z_ENABLE;
+		if (flags & RADEON_DEPTH) {
+			rb3d_cntl |= RADEON_Z_ENABLE;
 		} else {
 			rb3d_cntl &= ~RADEON_Z_ENABLE;
 		}
 
-		if ( flags & RADEON_STENCIL ) {
-			rb3d_cntl |=  RADEON_STENCIL_ENABLE;
-			rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
+		if (flags & RADEON_STENCIL) {
+			rb3d_cntl |= RADEON_STENCIL_ENABLE;
+			rb3d_stencilrefmask = clear->depth_mask;	/* misnamed field */
 		} else {
 			rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
 			rb3d_stencilrefmask = 0x00000000;
 		}
 
-		BEGIN_RING( 13 );
+		BEGIN_RING(13);
 		RADEON_WAIT_UNTIL_2D_IDLE();
 
-		OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
-		OUT_RING( 0x00000000 );
-		OUT_RING( rb3d_cntl );
-		
-		OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
-			      depth_clear->rb3d_zstencilcntl );
-		OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
-			      rb3d_stencilrefmask );
-		OUT_RING_REG( RADEON_RB3D_PLANEMASK,
-			      0x00000000 );
-		OUT_RING_REG( RADEON_SE_CNTL,
-			      depth_clear->se_cntl );
+		OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
+		OUT_RING(0x00000000);
+		OUT_RING(rb3d_cntl);
+
+		OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL,
+			     depth_clear->rb3d_zstencilcntl);
+		OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
+		OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
+		OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
 		ADVANCE_RING();
 
 		/* Make sure we restore the 3D state next time.
 		 */
 		dev_priv->sarea_priv->ctx_owner = 0;
 
-		for ( i = 0 ; i < nbox ; i++ ) {
-			
-			/* Funny that this should be required -- 
+		for (i = 0; i < nbox; i++) {
+
+			/* Funny that this should be required --
 			 *  sets top-left?
 			 */
-			radeon_emit_clip_rect( dev_priv,
-					       &sarea_priv->boxes[i] );
-
-			BEGIN_RING( 15 );
-
-			OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) );
-			OUT_RING( RADEON_VTX_Z_PRESENT |
-				  RADEON_VTX_PKCOLOR_PRESENT);
-			OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
-				   RADEON_PRIM_WALK_RING |
-				   RADEON_MAOS_ENABLE |
-				   RADEON_VTX_FMT_RADEON_MODE |
-				   (3 << RADEON_NUM_VERTICES_SHIFT)) );
-
-
-			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x0 );
-
-			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x0 );
-
-			OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x0 );
+			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
+
+			BEGIN_RING(15);
+
+			OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
+			OUT_RING(RADEON_VTX_Z_PRESENT |
+				 RADEON_VTX_PKCOLOR_PRESENT);
+			OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
+				  RADEON_PRIM_WALK_RING |
+				  RADEON_MAOS_ENABLE |
+				  RADEON_VTX_FMT_RADEON_MODE |
+				  (3 << RADEON_NUM_VERTICES_SHIFT)));
+
+			OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
+			OUT_RING(0x0);
+
+			OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
+			OUT_RING(0x0);
+
+			OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
+			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
+			OUT_RING(0x0);
 
 			ADVANCE_RING();
 		}
@@ -990,15 +992,15 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 	 */
 	dev_priv->sarea_priv->last_clear++;
 
-	BEGIN_RING( 4 );
+	BEGIN_RING(4);
 
-	RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
+	RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
 	RADEON_WAIT_UNTIL_IDLE();
 
 	ADVANCE_RING();
 }
 
-static void radeon_cp_dispatch_swap( drm_device_t *dev )
+static void radeon_cp_dispatch_swap(drm_device_t * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1006,59 +1008,55 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
 	drm_clip_rect_t *pbox = sarea_priv->boxes;
 	int i;
 	RING_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	/* Do some trivial performance monitoring...
 	 */
 	if (dev_priv->do_boxes)
-		radeon_cp_performance_boxes( dev_priv );
-
+		radeon_cp_performance_boxes(dev_priv);
 
 	/* Wait for the 3D stream to idle before dispatching the bitblt.
 	 * This will prevent data corruption between the two streams.
 	 */
-	BEGIN_RING( 2 );
+	BEGIN_RING(2);
 
 	RADEON_WAIT_UNTIL_3D_IDLE();
 
 	ADVANCE_RING();
 
-	for ( i = 0 ; i < nbox ; i++ ) {
+	for (i = 0; i < nbox; i++) {
 		int x = pbox[i].x1;
 		int y = pbox[i].y1;
 		int w = pbox[i].x2 - x;
 		int h = pbox[i].y2 - y;
 
-		DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
-			   x, y, w, h );
-
-		BEGIN_RING( 7 );
-
-		OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
-		OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
-			  RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-			  RADEON_GMC_BRUSH_NONE |
-			  (dev_priv->color_fmt << 8) |
-			  RADEON_GMC_SRC_DATATYPE_COLOR |
-			  RADEON_ROP3_S |
-			  RADEON_DP_SRC_SOURCE_MEMORY |
-			  RADEON_GMC_CLR_CMP_CNTL_DIS |
-			  RADEON_GMC_WR_MSK_DIS );
-		
+		DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", x, y, w, h);
+
+		BEGIN_RING(7);
+
+		OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
+		OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
+			 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+			 RADEON_GMC_BRUSH_NONE |
+			 (dev_priv->color_fmt << 8) |
+			 RADEON_GMC_SRC_DATATYPE_COLOR |
+			 RADEON_ROP3_S |
+			 RADEON_DP_SRC_SOURCE_MEMORY |
+			 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
+
 		/* Make this work even if front & back are flipped:
 		 */
 		if (dev_priv->current_page == 0) {
-			OUT_RING( dev_priv->back_pitch_offset );
-			OUT_RING( dev_priv->front_pitch_offset );
-		} 
-		else {
-			OUT_RING( dev_priv->front_pitch_offset );
-			OUT_RING( dev_priv->back_pitch_offset );
+			OUT_RING(dev_priv->back_pitch_offset);
+			OUT_RING(dev_priv->front_pitch_offset);
+		} else {
+			OUT_RING(dev_priv->front_pitch_offset);
+			OUT_RING(dev_priv->back_pitch_offset);
 		}
 
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (w << 16) | h );
+		OUT_RING((x << 16) | y);
+		OUT_RING((x << 16) | y);
+		OUT_RING((w << 16) | h);
 
 		ADVANCE_RING();
 	}
@@ -1069,44 +1067,43 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
 	 */
 	dev_priv->sarea_priv->last_frame++;
 
-	BEGIN_RING( 4 );
+	BEGIN_RING(4);
 
-	RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
+	RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
 	RADEON_WAIT_UNTIL_2D_IDLE();
 
 	ADVANCE_RING();
 }
 
-static void radeon_cp_dispatch_flip( drm_device_t *dev )
+static void radeon_cp_dispatch_flip(drm_device_t * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle;
+	drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle;
 	int offset = (dev_priv->current_page == 1)
-		   ? dev_priv->front_offset : dev_priv->back_offset;
+	    ? dev_priv->front_offset : dev_priv->back_offset;
 	RING_LOCALS;
-	DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", 
-		__FUNCTION__, 
-		dev_priv->current_page,
-		dev_priv->sarea_priv->pfCurrentPage);
+	DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
+		  __FUNCTION__,
+		  dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
 
 	/* Do some trivial performance monitoring...
 	 */
 	if (dev_priv->do_boxes) {
 		dev_priv->stats.boxes |= RADEON_BOX_FLIP;
-		radeon_cp_performance_boxes( dev_priv );
+		radeon_cp_performance_boxes(dev_priv);
 	}
 
 	/* Update the frame offsets for both CRTCs
 	 */
-	BEGIN_RING( 6 );
+	BEGIN_RING(6);
 
 	RADEON_WAIT_UNTIL_3D_IDLE();
-	OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch
-					      + sarea->frame.x 
-					      * ( dev_priv->color_fmt - 2 ) ) & ~7 )
-					  + offset );
-	OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
-					   + offset );
+	OUT_RING_REG(RADEON_CRTC_OFFSET,
+		     ((sarea->frame.y * dev_priv->front_pitch +
+		       sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
+		     + offset);
+	OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
+		     + offset);
 
 	ADVANCE_RING();
 
@@ -1116,16 +1113,16 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
 	 */
 	dev_priv->sarea_priv->last_frame++;
 	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
-					      1 - dev_priv->current_page;
+	    1 - dev_priv->current_page;
 
-	BEGIN_RING( 2 );
+	BEGIN_RING(2);
 
-	RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
+	RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
 
 	ADVANCE_RING();
 }
 
-static int bad_prim_vertex_nr( int primitive, int nr )
+static int bad_prim_vertex_nr(int primitive, int nr)
 {
 	switch (primitive & RADEON_PRIM_TYPE_MASK) {
 	case RADEON_PRIM_TYPE_NONE:
@@ -1145,24 +1142,21 @@ static int bad_prim_vertex_nr( int primitive, int nr )
 		return nr < 3;
 	default:
 		return 1;
-	}	
+	}
 }
 
-
-
 typedef struct {
 	unsigned int start;
 	unsigned int finish;
 	unsigned int prim;
 	unsigned int numverts;
-	unsigned int offset;   
-        unsigned int vc_format;
+	unsigned int offset;
+	unsigned int vc_format;
 } drm_radeon_tcl_prim_t;
 
-static void radeon_cp_dispatch_vertex( drm_device_t *dev,
-				       drm_buf_t *buf,
-				       drm_radeon_tcl_prim_t *prim )
-
+static void radeon_cp_dispatch_vertex(drm_device_t * dev,
+				      drm_buf_t * buf,
+				      drm_radeon_tcl_prim_t * prim)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1174,45 +1168,39 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
 
 	DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
 		  prim->prim,
-		  prim->vc_format,
-		  prim->start,
-		  prim->finish,
-		  prim->numverts);
+		  prim->vc_format, prim->start, prim->finish, prim->numverts);
 
-	if (bad_prim_vertex_nr( prim->prim, prim->numverts )) {
-		DRM_ERROR( "bad prim %x numverts %d\n", 
-			   prim->prim, prim->numverts );
+	if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
+		DRM_ERROR("bad prim %x numverts %d\n",
+			  prim->prim, prim->numverts);
 		return;
 	}
 
 	do {
 		/* Emit the next cliprect */
-		if ( i < nbox ) {
-			radeon_emit_clip_rect( dev_priv, 
-					       &sarea_priv->boxes[i] );
+		if (i < nbox) {
+			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
 		}
 
 		/* Emit the vertex buffer rendering commands */
-		BEGIN_RING( 5 );
+		BEGIN_RING(5);
 
-		OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
-		OUT_RING( offset );
-		OUT_RING( numverts );
-		OUT_RING( prim->vc_format );
-		OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST |
-			  RADEON_COLOR_ORDER_RGBA |
-			  RADEON_VTX_FMT_RADEON_MODE |
-			  (numverts << RADEON_NUM_VERTICES_SHIFT) );
+		OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
+		OUT_RING(offset);
+		OUT_RING(numverts);
+		OUT_RING(prim->vc_format);
+		OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
+			 RADEON_COLOR_ORDER_RGBA |
+			 RADEON_VTX_FMT_RADEON_MODE |
+			 (numverts << RADEON_NUM_VERTICES_SHIFT));
 
 		ADVANCE_RING();
 
 		i++;
-	} while ( i < nbox );
+	} while (i < nbox);
 }
 
-
-
-static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
+static void radeon_cp_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
@@ -1221,24 +1209,22 @@ static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
 	buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
 
 	/* Emit the vertex buffer age */
-	BEGIN_RING( 2 );
-	RADEON_DISPATCH_AGE( buf_priv->age );
+	BEGIN_RING(2);
+	RADEON_DISPATCH_AGE(buf_priv->age);
 	ADVANCE_RING();
 
 	buf->pending = 1;
 	buf->used = 0;
 }
 
-static void radeon_cp_dispatch_indirect( drm_device_t *dev,
-					 drm_buf_t *buf,
-					 int start, int end )
+static void radeon_cp_dispatch_indirect(drm_device_t * dev,
+					drm_buf_t * buf, int start, int end)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	RING_LOCALS;
-	DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
-		   buf->idx, start, end );
+	DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
 
-	if ( start != end ) {
+	if (start != end) {
 		int offset = (dev_priv->gart_buffers_offset
 			      + buf->offset + start);
 		int dwords = (end - start + 3) / sizeof(u32);
@@ -1247,28 +1233,27 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
 		 * dwords, so if we've been given an odd number we must
 		 * pad the data with a Type-2 CP packet.
 		 */
-		if ( dwords & 1 ) {
+		if (dwords & 1) {
 			u32 *data = (u32 *)
-				((char *)dev->agp_buffer_map->handle
-				 + buf->offset + start);
+			    ((char *)dev->agp_buffer_map->handle
+			     + buf->offset + start);
 			data[dwords++] = RADEON_CP_PACKET2;
 		}
 
 		/* Fire off the indirect buffer */
-		BEGIN_RING( 3 );
+		BEGIN_RING(3);
 
-		OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) );
-		OUT_RING( offset );
-		OUT_RING( dwords );
+		OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
+		OUT_RING(offset);
+		OUT_RING(dwords);
 
 		ADVANCE_RING();
 	}
 }
 
-
-static void radeon_cp_dispatch_indices( drm_device_t *dev,
-					drm_buf_t *elt_buf,
-					drm_radeon_tcl_prim_t *prim )
+static void radeon_cp_dispatch_indices(drm_device_t * dev,
+				       drm_buf_t * elt_buf,
+				       drm_radeon_tcl_prim_t * prim)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1283,30 +1268,24 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
 	DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
 		  prim->prim,
 		  prim->vc_format,
-		  prim->start,
-		  prim->finish,
-		  prim->offset,
-		  prim->numverts);
-
-	if (bad_prim_vertex_nr( prim->prim, count )) {
-		DRM_ERROR( "bad prim %x count %d\n", 
-			   prim->prim, count );
+		  prim->start, prim->finish, prim->offset, prim->numverts);
+
+	if (bad_prim_vertex_nr(prim->prim, count)) {
+		DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
 		return;
 	}
 
-
-	if ( start >= prim->finish ||
-	     (prim->start & 0x7) ) {
-		DRM_ERROR( "buffer prim %d\n", prim->prim );
+	if (start >= prim->finish || (prim->start & 0x7)) {
+		DRM_ERROR("buffer prim %d\n", prim->prim);
 		return;
 	}
 
 	dwords = (prim->finish - prim->start + 3) / sizeof(u32);
 
-	data = (u32 *)((char *)dev->agp_buffer_map->handle +
-		       elt_buf->offset + prim->start);
+	data = (u32 *) ((char *)dev->agp_buffer_map->handle +
+			elt_buf->offset + prim->start);
 
-	data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
+	data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
 	data[1] = offset;
 	data[2] = prim->numverts;
 	data[3] = prim->vc_format;
@@ -1314,28 +1293,26 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
 		   RADEON_PRIM_WALK_IND |
 		   RADEON_COLOR_ORDER_RGBA |
 		   RADEON_VTX_FMT_RADEON_MODE |
-		   (count << RADEON_NUM_VERTICES_SHIFT) );
+		   (count << RADEON_NUM_VERTICES_SHIFT));
 
 	do {
-		if ( i < nbox ) 
-			radeon_emit_clip_rect( dev_priv, 
-					       &sarea_priv->boxes[i] );
+		if (i < nbox)
+			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
 
-		radeon_cp_dispatch_indirect( dev, elt_buf,
-					     prim->start,
-					     prim->finish );
+		radeon_cp_dispatch_indirect(dev, elt_buf,
+					    prim->start, prim->finish);
 
 		i++;
-	} while ( i < nbox );
+	} while (i < nbox);
 
 }
 
 #define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32))
 
-static int radeon_cp_dispatch_texture( DRMFILE filp,
-				       drm_device_t *dev,
-				       drm_radeon_texture_t *tex,
-				       drm_radeon_tex_image_t *image )
+static int radeon_cp_dispatch_texture(DRMFILE filp,
+				      drm_device_t * dev,
+				      drm_radeon_texture_t * tex,
+				      drm_radeon_tex_image_t * image)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_file_t *filp_priv;
@@ -1348,11 +1325,11 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
 	int i;
 	RING_LOCALS;
 
-	DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
+	DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
-	if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &tex->offset ) ) {
-		DRM_ERROR( "Invalid destination offset\n" );
-		return DRM_ERR( EINVAL );
+	if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) {
+		DRM_ERROR("Invalid destination offset\n");
+		return DRM_ERR(EINVAL);
 	}
 
 	dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
@@ -1361,7 +1338,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
 	 * up with the texture data from the host data blit, otherwise
 	 * part of the texture image may be corrupted.
 	 */
-	BEGIN_RING( 4 );
+	BEGIN_RING(4);
 	RADEON_FLUSH_CACHE();
 	RADEON_WAIT_UNTIL_IDLE();
 	ADVANCE_RING();
@@ -1371,17 +1348,16 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
 	 * chip wants it, but we need to compensate for the fact that the CP
 	 * ring gets byte-swapped
 	 */
-	BEGIN_RING( 2 );
-	OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT );
+	BEGIN_RING(2);
+	OUT_RING_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT);
 	ADVANCE_RING();
 #endif
 
-
 	/* The compiler won't optimize away a division by a variable,
 	 * even if the only legal values are powers of two.  Thus, we'll
 	 * use a shift instead.
 	 */
-	switch ( tex->format ) {
+	switch (tex->format) {
 	case RADEON_TXFORMAT_ARGB8888:
 	case RADEON_TXFORMAT_RGBA8888:
 		format = RADEON_COLOR_FORMAT_ARGB8888;
@@ -1405,52 +1381,52 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
 		blit_width = image->width * 1;
 		break;
 	default:
-		DRM_ERROR( "invalid texture format %d\n", tex->format );
+		DRM_ERROR("invalid texture format %d\n", tex->format);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width );
+	DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
 
 	do {
-		DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
-			   tex->offset >> 10, tex->pitch, tex->format,
-			   image->x, image->y, image->width, image->height );
+		DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
+			  tex->offset >> 10, tex->pitch, tex->format,
+			  image->x, image->y, image->width, image->height);
 
 		/* Make a copy of some parameters in case we have to
 		 * update them for a multi-pass texture blit.
 		 */
 		height = image->height;
 		data = (const u8 __user *)image->data;
-		
+
 		size = height * blit_width;
 
-		if ( size > RADEON_MAX_TEXTURE_SIZE ) {
+		if (size > RADEON_MAX_TEXTURE_SIZE) {
 			height = RADEON_MAX_TEXTURE_SIZE / blit_width;
 			size = height * blit_width;
-		} else if ( size < 4 && size > 0 ) {
+		} else if (size < 4 && size > 0) {
 			size = 4;
-		} else if ( size == 0 ) {
+		} else if (size == 0) {
 			return 0;
 		}
 
-		buf = radeon_freelist_get( dev );
-		if ( 0 && !buf ) {
-			radeon_do_cp_idle( dev_priv );
-			buf = radeon_freelist_get( dev );
+		buf = radeon_freelist_get(dev);
+		if (0 && !buf) {
+			radeon_do_cp_idle(dev_priv);
+			buf = radeon_freelist_get(dev);
 		}
-		if ( !buf ) {
+		if (!buf) {
 			DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
-			if (DRM_COPY_TO_USER( tex->image, image, sizeof(*image) ))
+			if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
 				return DRM_ERR(EFAULT);
 			return DRM_ERR(EAGAIN);
 		}
 
-
 		/* Dispatch the indirect buffer.
 		 */
-		buffer = (u32*)((char*)dev->agp_buffer_map->handle + buf->offset);
+		buffer =
+		    (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
 		dwords = size / 4;
-		buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
+		buffer[0] = CP_PACKET3(RADEON_CNTL_HOSTDATA_BLT, dwords + 6);
 		buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 			     RADEON_GMC_BRUSH_NONE |
 			     (format << 8) |
@@ -1459,7 +1435,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
 			     RADEON_DP_SRC_SOURCE_HOST_DATA |
 			     RADEON_GMC_CLR_CMP_CNTL_DIS |
 			     RADEON_GMC_WR_MSK_DIS);
-		
+
 		buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
 		buffer[3] = 0xffffffff;
 		buffer[4] = 0xffffffff;
@@ -1468,14 +1444,14 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
 		buffer[7] = dwords;
 		buffer += 8;
 
-		if ( tex_width >= 32 ) {
+		if (tex_width >= 32) {
 			/* Texture image width is larger than the minimum, so we
 			 * can upload it directly.
 			 */
-			if ( DRM_COPY_FROM_USER( buffer, data, 
-						 dwords * sizeof(u32) ) ) {
-				DRM_ERROR( "EFAULT on data, %d dwords\n", 
-					   dwords );
+			if (DRM_COPY_FROM_USER(buffer, data,
+					       dwords * sizeof(u32))) {
+				DRM_ERROR("EFAULT on data, %d dwords\n",
+					  dwords);
 				return DRM_ERR(EFAULT);
 			}
 		} else {
@@ -1483,11 +1459,10 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
 			 * need to pad out each image scanline to the minimum
 			 * width.
 			 */
-			for ( i = 0 ; i < tex->height ; i++ ) {
-				if ( DRM_COPY_FROM_USER( buffer, data, 
-							 tex_width ) ) {
-					DRM_ERROR( "EFAULT on pad, %d bytes\n",
-						   tex_width );
+			for (i = 0; i < tex->height; i++) {
+				if (DRM_COPY_FROM_USER(buffer, data, tex_width)) {
+					DRM_ERROR("EFAULT on pad, %d bytes\n",
+						  tex_width);
 					return DRM_ERR(EFAULT);
 				}
 				buffer += 8;
@@ -1497,8 +1472,8 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
 
 		buf->filp = filp;
 		buf->used = (dwords + 8) * sizeof(u32);
-		radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
-		radeon_cp_discard_buffer( dev, buf );
+		radeon_cp_dispatch_indirect(dev, buf, 0, buf->used);
+		radeon_cp_discard_buffer(dev, buf);
 
 		/* Update the input parameters for next time */
 		image->y += height;
@@ -1510,84 +1485,83 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
 	 * the texture data is written out to memory before rendering
 	 * continues.
 	 */
-	BEGIN_RING( 4 );
+	BEGIN_RING(4);
 	RADEON_FLUSH_CACHE();
 	RADEON_WAIT_UNTIL_2D_IDLE();
 	ADVANCE_RING();
 	return 0;
 }
 
-
-static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
+static void radeon_cp_dispatch_stipple(drm_device_t * dev, u32 * stipple)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	int i;
 	RING_LOCALS;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	BEGIN_RING( 35 );
+	BEGIN_RING(35);
 
-	OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) );
-	OUT_RING( 0x00000000 );
+	OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
+	OUT_RING(0x00000000);
 
-	OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) );
-	for ( i = 0 ; i < 32 ; i++ ) {
-		OUT_RING( stipple[i] );
+	OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
+	for (i = 0; i < 32; i++) {
+		OUT_RING(stipple[i]);
 	}
 
 	ADVANCE_RING();
 }
 
-
 /* ================================================================
  * IOCTL functions
  */
 
-int radeon_cp_clear( DRM_IOCTL_ARGS )
+int radeon_cp_clear(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_radeon_clear_t clear;
 	drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t __user *)data,
-			     sizeof(clear) );
+	DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data,
+				 sizeof(clear));
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
-	if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
+	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
 
-	if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes,
-			     sarea_priv->nbox * sizeof(depth_boxes[0]) ) )
+	if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes,
+			       sarea_priv->nbox * sizeof(depth_boxes[0])))
 		return DRM_ERR(EFAULT);
 
-	radeon_cp_dispatch_clear( dev, &clear, depth_boxes );
+	radeon_cp_dispatch_clear(dev, &clear, depth_boxes);
 
 	COMMIT_RING();
 	return 0;
 }
 
-
 /* Not sure why this isn't set all the time:
- */ 
-static int radeon_do_init_pageflip( drm_device_t *dev )
+ */
+static int radeon_do_init_pageflip(drm_device_t * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	RING_LOCALS;
 
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	BEGIN_RING( 6 );
+	BEGIN_RING(6);
 	RADEON_WAIT_UNTIL_3D_IDLE();
-	OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
-	OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
-	OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) );
-	OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
+	OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
+	OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
+		 RADEON_CRTC_OFFSET_FLIP_CNTL);
+	OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
+	OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
+		 RADEON_CRTC_OFFSET_FLIP_CNTL);
 	ADVANCE_RING();
 
 	dev_priv->page_flipping = 1;
@@ -1600,62 +1574,62 @@ static int radeon_do_init_pageflip( drm_device_t *dev )
 /* Called whenever a client dies, from drm_release.
  * NOTE:  Lock isn't necessarily held when this is called!
  */
-int radeon_do_cleanup_pageflip( drm_device_t *dev )
+int radeon_do_cleanup_pageflip(drm_device_t * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	if (dev_priv->current_page != 0)
-		radeon_cp_dispatch_flip( dev );
+		radeon_cp_dispatch_flip(dev);
 
 	dev_priv->page_flipping = 0;
 	return 0;
 }
 
 /* Swapping and flipping are different operations, need different ioctls.
- * They can & should be intermixed to support multiple 3d windows.  
+ * They can & should be intermixed to support multiple 3d windows.
  */
-int radeon_cp_flip( DRM_IOCTL_ARGS )
+int radeon_cp_flip(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
-	if (!dev_priv->page_flipping) 
-		radeon_do_init_pageflip( dev );
-		
-	radeon_cp_dispatch_flip( dev );
+	if (!dev_priv->page_flipping)
+		radeon_do_init_pageflip(dev);
+
+	radeon_cp_dispatch_flip(dev);
 
 	COMMIT_RING();
 	return 0;
 }
 
-int radeon_cp_swap( DRM_IOCTL_ARGS )
+int radeon_cp_swap(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
-	if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
+	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
 
-	radeon_cp_dispatch_swap( dev );
+	radeon_cp_dispatch_swap(dev);
 	dev_priv->sarea_priv->ctx_owner = 0;
 
 	COMMIT_RING();
 	return 0;
 }
 
-int radeon_cp_vertex( DRM_IOCTL_ARGS )
+int radeon_cp_vertex(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1666,60 +1640,58 @@ int radeon_cp_vertex( DRM_IOCTL_ARGS )
 	drm_radeon_vertex_t vertex;
 	drm_radeon_tcl_prim_t prim;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
+	DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t __user *)data,
-			     sizeof(vertex) );
+	DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data,
+				 sizeof(vertex));
 
-	DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n",
-		   DRM_CURRENTPID,
-		   vertex.idx, vertex.count, vertex.discard );
+	DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
+		  DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
 
-	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   vertex.idx, dma->buf_count - 1 );
+	if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
+		DRM_ERROR("buffer index %d (of %d max)\n",
+			  vertex.idx, dma->buf_count - 1);
 		return DRM_ERR(EINVAL);
 	}
-	if ( vertex.prim < 0 ||
-	     vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
-		DRM_ERROR( "buffer prim %d\n", vertex.prim );
+	if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
+		DRM_ERROR("buffer prim %d\n", vertex.prim);
 		return DRM_ERR(EINVAL);
 	}
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
+	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
 	buf = dma->buflist[vertex.idx];
 
-	if ( buf->filp != filp ) {
-		DRM_ERROR( "process %d using buffer owned by %p\n",
-			   DRM_CURRENTPID, buf->filp );
+	if (buf->filp != filp) {
+		DRM_ERROR("process %d using buffer owned by %p\n",
+			  DRM_CURRENTPID, buf->filp);
 		return DRM_ERR(EINVAL);
 	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
+	if (buf->pending) {
+		DRM_ERROR("sending pending buffer %d\n", vertex.idx);
 		return DRM_ERR(EINVAL);
 	}
 
 	/* Build up a prim_t record:
 	 */
 	if (vertex.count) {
-		buf->used = vertex.count; /* not used? */
-
-		if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
-			if ( radeon_emit_state( dev_priv, filp_priv,
-						&sarea_priv->context_state,
-						sarea_priv->tex_state,
-						sarea_priv->dirty ) ) {
-				DRM_ERROR( "radeon_emit_state failed\n" );
-				return DRM_ERR( EINVAL );
+		buf->used = vertex.count;	/* not used? */
+
+		if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
+			if (radeon_emit_state(dev_priv, filp_priv,
+					      &sarea_priv->context_state,
+					      sarea_priv->tex_state,
+					      sarea_priv->dirty)) {
+				DRM_ERROR("radeon_emit_state failed\n");
+				return DRM_ERR(EINVAL);
 			}
 
 			sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
@@ -1729,23 +1701,23 @@ int radeon_cp_vertex( DRM_IOCTL_ARGS )
 		}
 
 		prim.start = 0;
-		prim.finish = vertex.count; /* unused */
+		prim.finish = vertex.count;	/* unused */
 		prim.prim = vertex.prim;
 		prim.numverts = vertex.count;
 		prim.vc_format = dev_priv->sarea_priv->vc_format;
-		
-		radeon_cp_dispatch_vertex( dev, buf, &prim );
+
+		radeon_cp_dispatch_vertex(dev, buf, &prim);
 	}
 
 	if (vertex.discard) {
-		radeon_cp_discard_buffer( dev, buf );
+		radeon_cp_discard_buffer(dev, buf);
 	}
 
 	COMMIT_RING();
 	return 0;
 }
 
-int radeon_cp_indices( DRM_IOCTL_ARGS )
+int radeon_cp_indices(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1757,69 +1729,67 @@ int radeon_cp_indices( DRM_IOCTL_ARGS )
 	drm_radeon_tcl_prim_t prim;
 	int count;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
+	DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t __user *)data,
-			     sizeof(elts) );
+	DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data,
+				 sizeof(elts));
 
-	DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n",
-		   DRM_CURRENTPID,
-		   elts.idx, elts.start, elts.end, elts.discard );
+	DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
+		  DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard);
 
-	if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   elts.idx, dma->buf_count - 1 );
+	if (elts.idx < 0 || elts.idx >= dma->buf_count) {
+		DRM_ERROR("buffer index %d (of %d max)\n",
+			  elts.idx, dma->buf_count - 1);
 		return DRM_ERR(EINVAL);
 	}
-	if ( elts.prim < 0 ||
-	     elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
-		DRM_ERROR( "buffer prim %d\n", elts.prim );
+	if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
+		DRM_ERROR("buffer prim %d\n", elts.prim);
 		return DRM_ERR(EINVAL);
 	}
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
+	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
 	buf = dma->buflist[elts.idx];
 
-	if ( buf->filp != filp ) {
-		DRM_ERROR( "process %d using buffer owned by %p\n",
-			   DRM_CURRENTPID, buf->filp );
+	if (buf->filp != filp) {
+		DRM_ERROR("process %d using buffer owned by %p\n",
+			  DRM_CURRENTPID, buf->filp);
 		return DRM_ERR(EINVAL);
 	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", elts.idx );
+	if (buf->pending) {
+		DRM_ERROR("sending pending buffer %d\n", elts.idx);
 		return DRM_ERR(EINVAL);
 	}
 
 	count = (elts.end - elts.start) / sizeof(u16);
 	elts.start -= RADEON_INDEX_PRIM_OFFSET;
 
-	if ( elts.start & 0x7 ) {
-		DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
+	if (elts.start & 0x7) {
+		DRM_ERROR("misaligned buffer 0x%x\n", elts.start);
 		return DRM_ERR(EINVAL);
 	}
-	if ( elts.start < buf->used ) {
-		DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
+	if (elts.start < buf->used) {
+		DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used);
 		return DRM_ERR(EINVAL);
 	}
 
 	buf->used = elts.end;
 
-	if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
-		if ( radeon_emit_state( dev_priv, filp_priv,
-					&sarea_priv->context_state,
-					sarea_priv->tex_state,
-					sarea_priv->dirty ) ) {
-			DRM_ERROR( "radeon_emit_state failed\n" );
-			return DRM_ERR( EINVAL );
+	if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
+		if (radeon_emit_state(dev_priv, filp_priv,
+				      &sarea_priv->context_state,
+				      sarea_priv->tex_state,
+				      sarea_priv->dirty)) {
+			DRM_ERROR("radeon_emit_state failed\n");
+			return DRM_ERR(EINVAL);
 		}
 
 		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
@@ -1828,26 +1798,25 @@ int radeon_cp_indices( DRM_IOCTL_ARGS )
 				       RADEON_REQUIRE_QUIESCENCE);
 	}
 
-
 	/* Build up a prim_t record:
 	 */
 	prim.start = elts.start;
-	prim.finish = elts.end; 
+	prim.finish = elts.end;
 	prim.prim = elts.prim;
 	prim.offset = 0;	/* offset from start of dma buffers */
-	prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
+	prim.numverts = RADEON_MAX_VB_VERTS;	/* duh */
 	prim.vc_format = dev_priv->sarea_priv->vc_format;
-	
-	radeon_cp_dispatch_indices( dev, buf, &prim );
+
+	radeon_cp_dispatch_indices(dev, buf, &prim);
 	if (elts.discard) {
-		radeon_cp_discard_buffer( dev, buf );
+		radeon_cp_discard_buffer(dev, buf);
 	}
 
 	COMMIT_RING();
 	return 0;
 }
 
-int radeon_cp_texture( DRM_IOCTL_ARGS )
+int radeon_cp_texture(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1855,53 +1824,54 @@ int radeon_cp_texture( DRM_IOCTL_ARGS )
 	drm_radeon_tex_image_t image;
 	int ret;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t __user *)data, sizeof(tex) );
+	DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data,
+				 sizeof(tex));
 
-	if ( tex.image == NULL ) {
-		DRM_ERROR( "null texture image!\n" );
+	if (tex.image == NULL) {
+		DRM_ERROR("null texture image!\n");
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( DRM_COPY_FROM_USER( &image,
-			     (drm_radeon_tex_image_t __user *)tex.image,
-			     sizeof(image) ) )
+	if (DRM_COPY_FROM_USER(&image,
+			       (drm_radeon_tex_image_t __user *) tex.image,
+			       sizeof(image)))
 		return DRM_ERR(EFAULT);
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
+	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
-	ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image );
+	ret = radeon_cp_dispatch_texture(filp, dev, &tex, &image);
 
 	COMMIT_RING();
 	return ret;
 }
 
-int radeon_cp_stipple( DRM_IOCTL_ARGS )
+int radeon_cp_stipple(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_stipple_t stipple;
 	u32 mask[32];
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t __user *)data,
-			     sizeof(stipple) );
+	DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data,
+				 sizeof(stipple));
 
-	if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) )
+	if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32)))
 		return DRM_ERR(EFAULT);
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
-	radeon_cp_dispatch_stipple( dev, mask );
+	radeon_cp_dispatch_stipple(dev, mask);
 
 	COMMIT_RING();
 	return 0;
 }
 
-int radeon_cp_indirect( DRM_IOCTL_ARGS )
+int radeon_cp_indirect(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1910,53 +1880,53 @@ int radeon_cp_indirect( DRM_IOCTL_ARGS )
 	drm_radeon_indirect_t indirect;
 	RING_LOCALS;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t __user *)data,
-			     sizeof(indirect) );
+	DRM_COPY_FROM_USER_IOCTL(indirect,
+				 (drm_radeon_indirect_t __user *) data,
+				 sizeof(indirect));
 
-	DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
-		   indirect.idx, indirect.start,
-		   indirect.end, indirect.discard );
+	DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
+		  indirect.idx, indirect.start, indirect.end, indirect.discard);
 
-	if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   indirect.idx, dma->buf_count - 1 );
+	if (indirect.idx < 0 || indirect.idx >= dma->buf_count) {
+		DRM_ERROR("buffer index %d (of %d max)\n",
+			  indirect.idx, dma->buf_count - 1);
 		return DRM_ERR(EINVAL);
 	}
 
 	buf = dma->buflist[indirect.idx];
 
-	if ( buf->filp != filp ) {
-		DRM_ERROR( "process %d using buffer owned by %p\n",
-			   DRM_CURRENTPID, buf->filp );
+	if (buf->filp != filp) {
+		DRM_ERROR("process %d using buffer owned by %p\n",
+			  DRM_CURRENTPID, buf->filp);
 		return DRM_ERR(EINVAL);
 	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
+	if (buf->pending) {
+		DRM_ERROR("sending pending buffer %d\n", indirect.idx);
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( indirect.start < buf->used ) {
-		DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
-			   indirect.start, buf->used );
+	if (indirect.start < buf->used) {
+		DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
+			  indirect.start, buf->used);
 		return DRM_ERR(EINVAL);
 	}
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
+	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
 	buf->used = indirect.end;
 
 	/* Wait for the 3D stream to idle before the indirect buffer
 	 * containing 2D acceleration commands is processed.
 	 */
-	BEGIN_RING( 2 );
+	BEGIN_RING(2);
 
 	RADEON_WAIT_UNTIL_3D_IDLE();
 
@@ -1966,17 +1936,16 @@ int radeon_cp_indirect( DRM_IOCTL_ARGS )
 	 * X server.  This is insecure and is thus only available to
 	 * privileged clients.
 	 */
-	radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
+	radeon_cp_dispatch_indirect(dev, buf, indirect.start, indirect.end);
 	if (indirect.discard) {
-		radeon_cp_discard_buffer( dev, buf );
+		radeon_cp_discard_buffer(dev, buf);
 	}
 
-
 	COMMIT_RING();
 	return 0;
 }
 
-int radeon_cp_vertex2( DRM_IOCTL_ARGS )
+int radeon_cp_vertex2(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1988,65 +1957,64 @@ int radeon_cp_vertex2( DRM_IOCTL_ARGS )
 	int i;
 	unsigned char laststate;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
+	DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t __user *)data,
-			     sizeof(vertex) );
+	DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data,
+				 sizeof(vertex));
 
-	DRM_DEBUG( "pid=%d index=%d discard=%d\n",
-		   DRM_CURRENTPID,
-		   vertex.idx, vertex.discard );
+	DRM_DEBUG("pid=%d index=%d discard=%d\n",
+		  DRM_CURRENTPID, vertex.idx, vertex.discard);
 
-	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   vertex.idx, dma->buf_count - 1 );
+	if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
+		DRM_ERROR("buffer index %d (of %d max)\n",
+			  vertex.idx, dma->buf_count - 1);
 		return DRM_ERR(EINVAL);
 	}
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
+	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
 	buf = dma->buflist[vertex.idx];
 
-	if ( buf->filp != filp ) {
-		DRM_ERROR( "process %d using buffer owned by %p\n",
-			   DRM_CURRENTPID, buf->filp );
+	if (buf->filp != filp) {
+		DRM_ERROR("process %d using buffer owned by %p\n",
+			  DRM_CURRENTPID, buf->filp);
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
+	if (buf->pending) {
+		DRM_ERROR("sending pending buffer %d\n", vertex.idx);
 		return DRM_ERR(EINVAL);
 	}
-	
+
 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
 		return DRM_ERR(EINVAL);
 
-	for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) {
+	for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) {
 		drm_radeon_prim_t prim;
 		drm_radeon_tcl_prim_t tclprim;
-		
-		if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) )
+
+		if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim)))
 			return DRM_ERR(EFAULT);
-		
-		if ( prim.stateidx != laststate ) {
-			drm_radeon_state_t state;			       
-				
-			if ( DRM_COPY_FROM_USER( &state, 
-					     &vertex.state[prim.stateidx], 
-					     sizeof(state) ) )
+
+		if (prim.stateidx != laststate) {
+			drm_radeon_state_t state;
+
+			if (DRM_COPY_FROM_USER(&state,
+					       &vertex.state[prim.stateidx],
+					       sizeof(state)))
 				return DRM_ERR(EFAULT);
 
-			if ( radeon_emit_state2( dev_priv, filp_priv, &state ) ) {
-				DRM_ERROR( "radeon_emit_state2 failed\n" );
-				return DRM_ERR( EINVAL );
+			if (radeon_emit_state2(dev_priv, filp_priv, &state)) {
+				DRM_ERROR("radeon_emit_state2 failed\n");
+				return DRM_ERR(EINVAL);
 			}
 
 			laststate = prim.stateidx;
@@ -2057,42 +2025,40 @@ int radeon_cp_vertex2( DRM_IOCTL_ARGS )
 		tclprim.prim = prim.prim;
 		tclprim.vc_format = prim.vc_format;
 
-		if ( prim.prim & RADEON_PRIM_WALK_IND ) {
+		if (prim.prim & RADEON_PRIM_WALK_IND) {
 			tclprim.offset = prim.numverts * 64;
-			tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
+			tclprim.numverts = RADEON_MAX_VB_VERTS;	/* duh */
 
-			radeon_cp_dispatch_indices( dev, buf, &tclprim );
+			radeon_cp_dispatch_indices(dev, buf, &tclprim);
 		} else {
 			tclprim.numverts = prim.numverts;
-			tclprim.offset = 0; /* not used */
+			tclprim.offset = 0;	/* not used */
 
-			radeon_cp_dispatch_vertex( dev, buf, &tclprim );
+			radeon_cp_dispatch_vertex(dev, buf, &tclprim);
 		}
-		
+
 		if (sarea_priv->nbox == 1)
 			sarea_priv->nbox = 0;
 	}
 
-	if ( vertex.discard ) {
-		radeon_cp_discard_buffer( dev, buf );
+	if (vertex.discard) {
+		radeon_cp_discard_buffer(dev, buf);
 	}
 
 	COMMIT_RING();
 	return 0;
 }
 
-
-static int radeon_emit_packets( 
-	drm_radeon_private_t *dev_priv,
-	drm_file_t *filp_priv,
-	drm_radeon_cmd_header_t header,
-	drm_radeon_cmd_buffer_t *cmdbuf )
+static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
+			       drm_file_t * filp_priv,
+			       drm_radeon_cmd_header_t header,
+			       drm_radeon_cmd_buffer_t * cmdbuf)
 {
 	int id = (int)header.packet.packet_id;
 	int sz, reg;
 	int __user *data = (int __user *)cmdbuf->buf;
 	RING_LOCALS;
-   
+
 	if (id >= RADEON_MAX_STATE_PACKETS)
 		return DRM_ERR(EINVAL);
 
@@ -2100,18 +2066,18 @@ static int radeon_emit_packets(
 	reg = packet[id].start;
 
 	if (sz * sizeof(int) > cmdbuf->bufsz) {
-		DRM_ERROR( "Packet size provided larger than data provided\n" );
+		DRM_ERROR("Packet size provided larger than data provided\n");
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( radeon_check_and_fixup_packets( dev_priv, filp_priv, id, data ) ) {
-		DRM_ERROR( "Packet verification failed\n" );
-		return DRM_ERR( EINVAL );
+	if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) {
+		DRM_ERROR("Packet verification failed\n");
+		return DRM_ERR(EINVAL);
 	}
 
-	BEGIN_RING(sz+1);
-	OUT_RING( CP_PACKET0( reg, (sz-1) ) );
-	OUT_RING_USER_TABLE( data, sz );
+	BEGIN_RING(sz + 1);
+	OUT_RING(CP_PACKET0(reg, (sz - 1)));
+	OUT_RING_USER_TABLE(data, sz);
 	ADVANCE_RING();
 
 	cmdbuf->buf += sz * sizeof(int);
@@ -2119,10 +2085,9 @@ static int radeon_emit_packets(
 	return 0;
 }
 
-static __inline__ int radeon_emit_scalars( 
-	drm_radeon_private_t *dev_priv,
-	drm_radeon_cmd_header_t header,
-	drm_radeon_cmd_buffer_t *cmdbuf )
+static __inline__ int radeon_emit_scalars(drm_radeon_private_t * dev_priv,
+					  drm_radeon_cmd_header_t header,
+					  drm_radeon_cmd_buffer_t * cmdbuf)
 {
 	int sz = header.scalars.count;
 	int __user *data = (int __user *)cmdbuf->buf;
@@ -2130,11 +2095,11 @@ static __inline__ int radeon_emit_scalars(
 	int stride = header.scalars.stride;
 	RING_LOCALS;
 
-	BEGIN_RING( 3+sz );
-	OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
-	OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
-	OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
-	OUT_RING_USER_TABLE( data, sz );
+	BEGIN_RING(3 + sz);
+	OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
+	OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
+	OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
+	OUT_RING_USER_TABLE(data, sz);
 	ADVANCE_RING();
 	cmdbuf->buf += sz * sizeof(int);
 	cmdbuf->bufsz -= sz * sizeof(int);
@@ -2143,10 +2108,9 @@ static __inline__ int radeon_emit_scalars(
 
 /* God this is ugly
  */
-static __inline__ int radeon_emit_scalars2( 
-	drm_radeon_private_t *dev_priv,
-	drm_radeon_cmd_header_t header,
-	drm_radeon_cmd_buffer_t *cmdbuf )
+static __inline__ int radeon_emit_scalars2(drm_radeon_private_t * dev_priv,
+					   drm_radeon_cmd_header_t header,
+					   drm_radeon_cmd_buffer_t * cmdbuf)
 {
 	int sz = header.scalars.count;
 	int __user *data = (int __user *)cmdbuf->buf;
@@ -2154,21 +2118,20 @@ static __inline__ int radeon_emit_scalars2(
 	int stride = header.scalars.stride;
 	RING_LOCALS;
 
-	BEGIN_RING( 3+sz );
-	OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
-	OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
-	OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
-	OUT_RING_USER_TABLE( data, sz );
+	BEGIN_RING(3 + sz);
+	OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
+	OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
+	OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
+	OUT_RING_USER_TABLE(data, sz);
 	ADVANCE_RING();
 	cmdbuf->buf += sz * sizeof(int);
 	cmdbuf->bufsz -= sz * sizeof(int);
 	return 0;
 }
 
-static __inline__ int radeon_emit_vectors( 
-	drm_radeon_private_t *dev_priv,
-	drm_radeon_cmd_header_t header,
-	drm_radeon_cmd_buffer_t *cmdbuf )
+static __inline__ int radeon_emit_vectors(drm_radeon_private_t * dev_priv,
+					  drm_radeon_cmd_header_t header,
+					  drm_radeon_cmd_buffer_t * cmdbuf)
 {
 	int sz = header.vectors.count;
 	int __user *data = (int __user *)cmdbuf->buf;
@@ -2176,11 +2139,11 @@ static __inline__ int radeon_emit_vectors(
 	int stride = header.vectors.stride;
 	RING_LOCALS;
 
-	BEGIN_RING( 3+sz );
-	OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) );
-	OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
-	OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) );
-	OUT_RING_USER_TABLE( data, sz );
+	BEGIN_RING(3 + sz);
+	OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
+	OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
+	OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
+	OUT_RING_USER_TABLE(data, sz);
 	ADVANCE_RING();
 
 	cmdbuf->buf += sz * sizeof(int);
@@ -2188,10 +2151,9 @@ static __inline__ int radeon_emit_vectors(
 	return 0;
 }
 
-
-static int radeon_emit_packet3( drm_device_t *dev,
-				drm_file_t *filp_priv,
-				drm_radeon_cmd_buffer_t *cmdbuf )
+static int radeon_emit_packet3(drm_device_t * dev,
+			       drm_file_t * filp_priv,
+			       drm_radeon_cmd_buffer_t * cmdbuf)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	unsigned int cmdsz;
@@ -2201,14 +2163,14 @@ static int radeon_emit_packet3( drm_device_t *dev,
 
 	DRM_DEBUG("\n");
 
-	if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv,
-						     cmdbuf, &cmdsz ) ) ) {
-		DRM_ERROR( "Packet verification failed\n" );
+	if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
+						  cmdbuf, &cmdsz))) {
+		DRM_ERROR("Packet verification failed\n");
 		return ret;
 	}
 
-	BEGIN_RING( cmdsz );
-	OUT_RING_USER_TABLE( cmd, cmdsz );
+	BEGIN_RING(cmdsz);
+	OUT_RING_USER_TABLE(cmd, cmdsz);
 	ADVANCE_RING();
 
 	cmdbuf->buf += cmdsz * 4;
@@ -2216,11 +2178,10 @@ static int radeon_emit_packet3( drm_device_t *dev,
 	return 0;
 }
 
-
-static int radeon_emit_packet3_cliprect( drm_device_t *dev,
-					 drm_file_t *filp_priv,
-					 drm_radeon_cmd_buffer_t *cmdbuf,
-					 int orig_nbox )
+static int radeon_emit_packet3_cliprect(drm_device_t * dev,
+					drm_file_t * filp_priv,
+					drm_radeon_cmd_buffer_t * cmdbuf,
+					int orig_nbox)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_clip_rect_t box;
@@ -2233,9 +2194,9 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
 
 	DRM_DEBUG("\n");
 
-	if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv,
-						     cmdbuf, &cmdsz ) ) ) {
-		DRM_ERROR( "Packet verification failed\n" );
+	if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
+						  cmdbuf, &cmdsz))) {
+		DRM_ERROR("Packet verification failed\n");
 		return ret;
 	}
 
@@ -2243,8 +2204,9 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
 		goto out;
 
 	do {
-		if ( i < cmdbuf->nbox ) {
-			if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
+		if (i < cmdbuf->nbox) {
+			if (DRM_COPY_FROM_USER_UNCHECKED
+			    (&box, &boxes[i], sizeof(box)))
 				return DRM_ERR(EFAULT);
 			/* FIXME The second and subsequent times round
 			 * this loop, send a WAIT_UNTIL_3D_IDLE before
@@ -2258,30 +2220,29 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
 			 * the correct place to fix it but this works
 			 * around it until I can figure that out - Tim
 			 * Smith */
-			if ( i ) {
-				BEGIN_RING( 2 );
+			if (i) {
+				BEGIN_RING(2);
 				RADEON_WAIT_UNTIL_3D_IDLE();
 				ADVANCE_RING();
 			}
-			radeon_emit_clip_rect( dev_priv, &box );
+			radeon_emit_clip_rect(dev_priv, &box);
 		}
-		
-		BEGIN_RING( cmdsz );
-		OUT_RING_USER_TABLE( cmd, cmdsz );
+
+		BEGIN_RING(cmdsz);
+		OUT_RING_USER_TABLE(cmd, cmdsz);
 		ADVANCE_RING();
 
-	} while ( ++i < cmdbuf->nbox );
- 	if (cmdbuf->nbox == 1)
+	} while (++i < cmdbuf->nbox);
+	if (cmdbuf->nbox == 1)
 		cmdbuf->nbox = 0;
 
- out:
+      out:
 	cmdbuf->buf += cmdsz * 4;
 	cmdbuf->bufsz -= cmdsz * 4;
 	return 0;
 }
 
-
-static int radeon_emit_wait( drm_device_t *dev, int flags )
+static int radeon_emit_wait(drm_device_t * dev, int flags)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	RING_LOCALS;
@@ -2289,18 +2250,18 @@ static int radeon_emit_wait( drm_device_t *dev, int flags )
 	DRM_DEBUG("%s: %x\n", __FUNCTION__, flags);
 	switch (flags) {
 	case RADEON_WAIT_2D:
-		BEGIN_RING( 2 );
-		RADEON_WAIT_UNTIL_2D_IDLE(); 
+		BEGIN_RING(2);
+		RADEON_WAIT_UNTIL_2D_IDLE();
 		ADVANCE_RING();
 		break;
 	case RADEON_WAIT_3D:
-		BEGIN_RING( 2 );
-		RADEON_WAIT_UNTIL_3D_IDLE(); 
+		BEGIN_RING(2);
+		RADEON_WAIT_UNTIL_3D_IDLE();
 		ADVANCE_RING();
 		break;
-	case RADEON_WAIT_2D|RADEON_WAIT_3D:
-		BEGIN_RING( 2 );
-		RADEON_WAIT_UNTIL_IDLE(); 
+	case RADEON_WAIT_2D | RADEON_WAIT_3D:
+		BEGIN_RING(2);
+		RADEON_WAIT_UNTIL_IDLE();
 		ADVANCE_RING();
 		break;
 	default:
@@ -2310,7 +2271,7 @@ static int radeon_emit_wait( drm_device_t *dev, int flags )
 	return 0;
 }
 
-int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
+int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2322,35 +2283,35 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
 	drm_radeon_cmd_header_t header;
 	int orig_nbox;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
+	DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t __user *)data,
-			     sizeof(cmdbuf) );
+	DRM_COPY_FROM_USER_IOCTL(cmdbuf,
+				 (drm_radeon_cmd_buffer_t __user *) data,
+				 sizeof(cmdbuf));
 
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
+	RING_SPACE_TEST_WITH_RETURN(dev_priv);
+	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
-
-	if (DRM_VERIFYAREA_READ( cmdbuf.buf, cmdbuf.bufsz ))
+	if (DRM_VERIFYAREA_READ(cmdbuf.buf, cmdbuf.bufsz))
 		return DRM_ERR(EFAULT);
 
 	if (cmdbuf.nbox &&
-	    DRM_VERIFYAREA_READ(cmdbuf.boxes, 
-			 cmdbuf.nbox * sizeof(drm_clip_rect_t)))
+	    DRM_VERIFYAREA_READ(cmdbuf.boxes,
+				cmdbuf.nbox * sizeof(drm_clip_rect_t)))
 		return DRM_ERR(EFAULT);
 
 	orig_nbox = cmdbuf.nbox;
 
-	while ( cmdbuf.bufsz >= sizeof(header) ) {
-		
-		if (DRM_GET_USER_UNCHECKED( header.i, (int __user *)cmdbuf.buf )) {
+	while (cmdbuf.bufsz >= sizeof(header)) {
+
+		if (DRM_GET_USER_UNCHECKED(header.i, (int __user *)cmdbuf.buf)) {
 			DRM_ERROR("__get_user %p\n", cmdbuf.buf);
 			return DRM_ERR(EFAULT);
 		}
@@ -2359,9 +2320,10 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
 		cmdbuf.bufsz -= sizeof(header);
 
 		switch (header.header.cmd_type) {
-		case RADEON_CMD_PACKET: 
+		case RADEON_CMD_PACKET:
 			DRM_DEBUG("RADEON_CMD_PACKET\n");
-			if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) {
+			if (radeon_emit_packets
+			    (dev_priv, filp_priv, header, &cmdbuf)) {
 				DRM_ERROR("radeon_emit_packets failed\n");
 				return DRM_ERR(EINVAL);
 			}
@@ -2369,7 +2331,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
 
 		case RADEON_CMD_SCALARS:
 			DRM_DEBUG("RADEON_CMD_SCALARS\n");
-			if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) {
+			if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) {
 				DRM_ERROR("radeon_emit_scalars failed\n");
 				return DRM_ERR(EINVAL);
 			}
@@ -2377,7 +2339,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
 
 		case RADEON_CMD_VECTORS:
 			DRM_DEBUG("RADEON_CMD_VECTORS\n");
-			if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) {
+			if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) {
 				DRM_ERROR("radeon_emit_vectors failed\n");
 				return DRM_ERR(EINVAL);
 			}
@@ -2386,25 +2348,25 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
 		case RADEON_CMD_DMA_DISCARD:
 			DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
 			idx = header.dma.buf_idx;
-			if ( idx < 0 || idx >= dma->buf_count ) {
-				DRM_ERROR( "buffer index %d (of %d max)\n",
-					   idx, dma->buf_count - 1 );
+			if (idx < 0 || idx >= dma->buf_count) {
+				DRM_ERROR("buffer index %d (of %d max)\n",
+					  idx, dma->buf_count - 1);
 				return DRM_ERR(EINVAL);
 			}
 
 			buf = dma->buflist[idx];
-			if ( buf->filp != filp || buf->pending ) {
-				DRM_ERROR( "bad buffer %p %p %d\n",
-					   buf->filp, filp, buf->pending);
+			if (buf->filp != filp || buf->pending) {
+				DRM_ERROR("bad buffer %p %p %d\n",
+					  buf->filp, filp, buf->pending);
 				return DRM_ERR(EINVAL);
 			}
 
-			radeon_cp_discard_buffer( dev, buf );
+			radeon_cp_discard_buffer(dev, buf);
 			break;
 
 		case RADEON_CMD_PACKET3:
 			DRM_DEBUG("RADEON_CMD_PACKET3\n");
-			if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) {
+			if (radeon_emit_packet3(dev, filp_priv, &cmdbuf)) {
 				DRM_ERROR("radeon_emit_packet3 failed\n");
 				return DRM_ERR(EINVAL);
 			}
@@ -2412,7 +2374,8 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
 
 		case RADEON_CMD_PACKET3_CLIP:
 			DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
-			if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) {
+			if (radeon_emit_packet3_cliprect
+			    (dev, filp_priv, &cmdbuf, orig_nbox)) {
 				DRM_ERROR("radeon_emit_packet3_clip failed\n");
 				return DRM_ERR(EINVAL);
 			}
@@ -2420,7 +2383,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
 
 		case RADEON_CMD_SCALARS2:
 			DRM_DEBUG("RADEON_CMD_SCALARS2\n");
-			if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) {
+			if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) {
 				DRM_ERROR("radeon_emit_scalars2 failed\n");
 				return DRM_ERR(EINVAL);
 			}
@@ -2428,58 +2391,55 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
 
 		case RADEON_CMD_WAIT:
 			DRM_DEBUG("RADEON_CMD_WAIT\n");
-			if (radeon_emit_wait( dev, header.wait.flags )) {
+			if (radeon_emit_wait(dev, header.wait.flags)) {
 				DRM_ERROR("radeon_emit_wait failed\n");
 				return DRM_ERR(EINVAL);
 			}
 			break;
 		default:
-			DRM_ERROR("bad cmd_type %d at %p\n", 
+			DRM_ERROR("bad cmd_type %d at %p\n",
 				  header.header.cmd_type,
 				  cmdbuf.buf - sizeof(header));
 			return DRM_ERR(EINVAL);
 		}
 	}
 
-
 	DRM_DEBUG("DONE\n");
 	COMMIT_RING();
 	return 0;
 }
 
-
-
-int radeon_cp_getparam( DRM_IOCTL_ARGS )
+int radeon_cp_getparam(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_getparam_t param;
 	int value;
 
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t __user *)data,
-			     sizeof(param) );
+	DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data,
+				 sizeof(param));
 
-	DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
+	DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
 
-	switch( param.param ) {
+	switch (param.param) {
 	case RADEON_PARAM_GART_BUFFER_OFFSET:
 		value = dev_priv->gart_buffers_offset;
 		break;
 	case RADEON_PARAM_LAST_FRAME:
 		dev_priv->stats.last_frame_reads++;
-		value = GET_SCRATCH( 0 );
+		value = GET_SCRATCH(0);
 		break;
 	case RADEON_PARAM_LAST_DISPATCH:
-		value = GET_SCRATCH( 1 );
+		value = GET_SCRATCH(1);
 		break;
 	case RADEON_PARAM_LAST_CLEAR:
 		dev_priv->stats.last_clear_reads++;
-		value = GET_SCRATCH( 2 );
+		value = GET_SCRATCH(2);
 		break;
 	case RADEON_PARAM_IRQ_NR:
 		value = dev->irq;
@@ -2494,15 +2454,15 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
 		value = dev_priv->ring_rptr_offset;
 		break;
 #if BITS_PER_LONG == 32
-	/*
-	 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
-	 * pointer which can't fit into an int-sized variable.  According to
-	 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
-	 * not supporting it shouldn't be a problem.  If the same functionality
-	 * is needed on 64-bit platforms, a new ioctl() would have to be added,
-	 * so backwards-compatibility for the embedded platforms can be
-	 * maintained.  --davidm 4-Feb-2004.
-	 */
+		/*
+		 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
+		 * pointer which can't fit into an int-sized variable.  According to
+		 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
+		 * not supporting it shouldn't be a problem.  If the same functionality
+		 * is needed on 64-bit platforms, a new ioctl() would have to be added,
+		 * so backwards-compatibility for the embedded platforms can be
+		 * maintained.  --davidm 4-Feb-2004.
+		 */
 	case RADEON_PARAM_SAREA_HANDLE:
 		/* The lock is the first dword in the sarea. */
 		value = (long)dev->lock.hw_lock;
@@ -2515,39 +2475,40 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
 		return DRM_ERR(EINVAL);
 	}
 
-	if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
-		DRM_ERROR( "copy_to_user\n" );
+	if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
+		DRM_ERROR("copy_to_user\n");
 		return DRM_ERR(EFAULT);
 	}
-	
+
 	return 0;
 }
 
-int radeon_cp_setparam( DRM_IOCTL_ARGS ) {
+int radeon_cp_setparam(DRM_IOCTL_ARGS)
+{
 	DRM_DEVICE;
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_file_t *filp_priv;
 	drm_radeon_setparam_t sp;
 	struct drm_radeon_driver_file_fields *radeon_priv;
-	
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		return DRM_ERR( EINVAL );
+
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
+		return DRM_ERR(EINVAL);
 	}
 
-	DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
+	DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
-	DRM_COPY_FROM_USER_IOCTL( sp, ( drm_radeon_setparam_t __user * )data,
-				  sizeof( sp ) );
+	DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data,
+				 sizeof(sp));
 
-	switch( sp.param ) {
+	switch (sp.param) {
 	case RADEON_SETPARAM_FB_LOCATION:
 		radeon_priv = filp_priv->driver_priv;
 		radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
 		break;
 	default:
-		DRM_DEBUG( "Invalid parameter %d\n", sp.param );
-		return DRM_ERR( EINVAL );
+		DRM_DEBUG("Invalid parameter %d\n", sp.param);
+		return DRM_ERR(EINVAL);
 	}
 
 	return 0;
@@ -2559,46 +2520,48 @@ int radeon_cp_setparam( DRM_IOCTL_ARGS ) {
  *
  * DRM infrastructure takes care of reclaiming dma buffers.
  */
-void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp)
+void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp)
 {
-	if ( dev->dev_private ) {				
-		drm_radeon_private_t *dev_priv = dev->dev_private; 
-		if ( dev_priv->page_flipping ) {		
-			radeon_do_cleanup_pageflip( dev );	
-		}						
-		radeon_mem_release( filp, dev_priv->gart_heap ); 
-		radeon_mem_release( filp, dev_priv->fb_heap );	
-	}				
+	if (dev->dev_private) {
+		drm_radeon_private_t *dev_priv = dev->dev_private;
+		if (dev_priv->page_flipping) {
+			radeon_do_cleanup_pageflip(dev);
+		}
+		radeon_mem_release(filp, dev_priv->gart_heap);
+		radeon_mem_release(filp, dev_priv->fb_heap);
+	}
 }
 
-void radeon_driver_pretakedown(drm_device_t *dev)
+void radeon_driver_pretakedown(drm_device_t * dev)
 {
 	radeon_do_release(dev);
 }
 
-int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv)
+int radeon_driver_open_helper(drm_device_t * dev, drm_file_t * filp_priv)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	struct drm_radeon_driver_file_fields *radeon_priv;
-	
-	radeon_priv = (struct drm_radeon_driver_file_fields *)drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES);
-	
+
+	radeon_priv =
+	    (struct drm_radeon_driver_file_fields *)
+	    drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES);
+
 	if (!radeon_priv)
 		return -ENOMEM;
-	
+
 	filp_priv->driver_priv = radeon_priv;
-	
-	if ( dev_priv )
+
+	if (dev_priv)
 		radeon_priv->radeon_fb_delta = dev_priv->fb_location;
 	else
 		radeon_priv->radeon_fb_delta = 0;
 	return 0;
 }
 
-void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv)
+void radeon_driver_free_filp_priv(drm_device_t * dev, drm_file_t * filp_priv)
 {
-	struct drm_radeon_driver_file_fields *radeon_priv = filp_priv->driver_priv;
-	
+	struct drm_radeon_driver_file_fields *radeon_priv =
+	    filp_priv->driver_priv;
+
 	drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES);
 }
-
diff --git a/shared-core/sis_drm.h b/shared-core/sis_drm.h
index e99c3a43..8f273da7 100644
--- a/shared-core/sis_drm.h
+++ b/shared-core/sis_drm.h
@@ -39,4 +39,4 @@ typedef struct {
 	unsigned int offset, size;
 } drm_sis_fb_t;
 
-#endif /* __SIS_DRM_H__ */
+#endif				/* __SIS_DRM_H__ */
diff --git a/shared-core/sis_drv.h b/shared-core/sis_drv.h
index 7232b8f3..2f0f2b84 100644
--- a/shared-core/sis_drv.h
+++ b/shared-core/sis_drv.h
@@ -10,11 +10,11 @@
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
@@ -22,7 +22,7 @@
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
- * 
+ *
  */
 
 #ifndef _SIS_DRV_H_
@@ -46,14 +46,14 @@ typedef struct drm_sis_private {
 	memHeap_t *FBHeap;
 } drm_sis_private_t;
 
-extern int sis_fb_alloc( DRM_IOCTL_ARGS );
-extern int sis_fb_free( DRM_IOCTL_ARGS );
-extern int sis_ioctl_agp_init( DRM_IOCTL_ARGS );
-extern int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS );
-extern int sis_ioctl_agp_free( DRM_IOCTL_ARGS );
-extern int sis_fb_init( DRM_IOCTL_ARGS );
+extern int sis_fb_alloc(DRM_IOCTL_ARGS);
+extern int sis_fb_free(DRM_IOCTL_ARGS);
+extern int sis_ioctl_agp_init(DRM_IOCTL_ARGS);
+extern int sis_ioctl_agp_alloc(DRM_IOCTL_ARGS);
+extern int sis_ioctl_agp_free(DRM_IOCTL_ARGS);
+extern int sis_fb_init(DRM_IOCTL_ARGS);
 
-extern int sis_init_context(drm_device_t *dev, int context);
-extern int sis_final_context(drm_device_t *dev, int context);
+extern int sis_init_context(drm_device_t * dev, int context);
+extern int sis_final_context(drm_device_t * dev, int context);
 
 #endif
diff --git a/shared-core/sis_ds.c b/shared-core/sis_ds.c
index 60bffa69..cc49c27d 100644
--- a/shared-core/sis_ds.c
+++ b/shared-core/sis_ds.c
@@ -10,11 +10,11 @@
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
@@ -22,10 +22,10 @@
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
- * 
+ *
  * Authors:
  *    Sung-Ching Lin <sclin@sis.com.tw>
- * 
+ *
  */
 
 #include "drmP.h"
@@ -41,13 +41,13 @@ set_t *setInit(void)
 	int i;
 	set_t *set;
 
-	set = (set_t *)drm_alloc(sizeof(set_t), DRM_MEM_DRIVER);
+	set = (set_t *) drm_alloc(sizeof(set_t), DRM_MEM_DRIVER);
 	if (set != NULL) {
 		for (i = 0; i < SET_SIZE; i++) {
-			set->list[i].free_next = i + 1;    
+			set->list[i].free_next = i + 1;
 			set->list[i].alloc_next = -1;
 		}
-		set->list[SET_SIZE-1].free_next = -1;
+		set->list[SET_SIZE - 1].free_next = -1;
 		set->free = 0;
 		set->alloc = -1;
 		set->trace = -1;
@@ -55,10 +55,10 @@ set_t *setInit(void)
 	return set;
 }
 
-int setAdd(set_t *set, ITEM_TYPE item)
+int setAdd(set_t * set, ITEM_TYPE item)
 {
 	int free = set->free;
-  
+
 	if (free != -1) {
 		set->list[free].val = item;
 		set->free = set->list[free].free_next;
@@ -67,16 +67,16 @@ int setAdd(set_t *set, ITEM_TYPE item)
 	}
 
 	set->list[free].alloc_next = set->alloc;
-	set->alloc = free;  
-	set->list[free].free_next = -1;    
+	set->alloc = free;
+	set->list[free].free_next = -1;
 
 	return 1;
 }
 
-int setDel(set_t *set, ITEM_TYPE item)
+int setDel(set_t * set, ITEM_TYPE item)
 {
 	int alloc = set->alloc;
-	int prev = -1;  
+	int prev = -1;
 
 	while (alloc != -1) {
 		if (set->list[alloc].val == item) {
@@ -103,7 +103,7 @@ int setDel(set_t *set, ITEM_TYPE item)
 
 /* setFirst -> setAdd -> setNext is wrong */
 
-int setFirst(set_t *set, ITEM_TYPE *item)
+int setFirst(set_t * set, ITEM_TYPE * item)
 {
 	if (set->alloc == -1)
 		return 0;
@@ -114,7 +114,7 @@ int setFirst(set_t *set, ITEM_TYPE *item)
 	return 1;
 }
 
-int setNext(set_t *set, ITEM_TYPE *item)
+int setNext(set_t * set, ITEM_TYPE * item)
 {
 	if (set->trace == -1)
 		return 0;
@@ -125,7 +125,7 @@ int setNext(set_t *set, ITEM_TYPE *item)
 	return 1;
 }
 
-int setDestroy(set_t *set)
+int setDestroy(set_t * set)
 {
 	drm_free(set, sizeof(set_t), DRM_MEM_DRIVER);
 
@@ -149,35 +149,34 @@ int setDestroy(set_t *set)
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 
+ * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  */
 
 #define ISFREE(bptr) ((bptr)->free)
 
-memHeap_t *mmInit(int ofs,
-		  int size)
+memHeap_t *mmInit(int ofs, int size)
 {
 	PMemBlock blocks;
 
 	if (size <= 0)
 		return NULL;
 
-	blocks = (TMemBlock *)drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER);
+	blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER);
 	if (blocks != NULL) {
 		blocks->ofs = ofs;
 		blocks->size = size;
 		blocks->free = 1;
-		return (memHeap_t *)blocks;
+		return (memHeap_t *) blocks;
 	} else
 		return NULL;
 }
 
 /* Checks if a pointer 'b' is part of the heap 'heap' */
-int mmBlockInHeap(memHeap_t *heap, PMemBlock b)
+int mmBlockInHeap(memHeap_t * heap, PMemBlock b)
 {
 	TMemBlock *p;
 
@@ -196,12 +195,10 @@ int mmBlockInHeap(memHeap_t *heap, PMemBlock b)
 
 /* Kludgey workaround for existing i810 server.  Remove soon.
  */
-memHeap_t *mmAddRange( memHeap_t *heap,
-		       int ofs,
-		       int size )
+memHeap_t *mmAddRange(memHeap_t * heap, int ofs, int size)
 {
 	PMemBlock blocks;
-	blocks = (TMemBlock *)drm_calloc(2, sizeof(TMemBlock), DRM_MEM_DRIVER);
+	blocks = (TMemBlock *) drm_calloc(2, sizeof(TMemBlock), DRM_MEM_DRIVER);
 	if (blocks != NULL) {
 		blocks[0].size = size;
 		blocks[0].free = 1;
@@ -213,23 +210,23 @@ memHeap_t *mmAddRange( memHeap_t *heap,
 		 */
 		blocks[1].size = 0;
 		blocks[1].free = 0;
-		blocks[1].ofs = ofs+size;
-		blocks[1].next = (PMemBlock)heap;
-		return (memHeap_t *)blocks;
+		blocks[1].ofs = ofs + size;
+		blocks[1].next = (PMemBlock) heap;
+		return (memHeap_t *) blocks;
 	} else
 		return heap;
 }
 
-static TMemBlock* SliceBlock(TMemBlock *p, 
-			     int startofs, int size, 
+static TMemBlock *SliceBlock(TMemBlock * p,
+			     int startofs, int size,
 			     int reserved, int alignment)
 {
 	TMemBlock *newblock;
 
 	/* break left */
 	if (startofs > p->ofs) {
-		newblock = (TMemBlock*) drm_calloc(1, sizeof(TMemBlock),
-		    DRM_MEM_DRIVER);
+		newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
+						    DRM_MEM_DRIVER);
 		newblock->ofs = startofs;
 		newblock->size = p->size - (startofs - p->ofs);
 		newblock->free = 1;
@@ -241,8 +238,8 @@ static TMemBlock* SliceBlock(TMemBlock *p,
 
 	/* break right */
 	if (size < p->size) {
-		newblock = (TMemBlock*) drm_calloc(1, sizeof(TMemBlock),
-		    DRM_MEM_DRIVER);
+		newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
+						    DRM_MEM_DRIVER);
 		newblock->ofs = startofs + size;
 		newblock->size = p->size - size;
 		newblock->free = 1;
@@ -258,37 +255,37 @@ static TMemBlock* SliceBlock(TMemBlock *p,
 	return p;
 }
 
-PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch)
+PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch)
 {
-	int mask,startofs, endofs;
+	int mask, startofs, endofs;
 	TMemBlock *p;
-	
+
 	if (heap == NULL || align2 < 0 || size <= 0)
 		return NULL;
 
-	mask = (1 << align2)-1;
+	mask = (1 << align2) - 1;
 	startofs = 0;
-	p = (TMemBlock *)heap;
+	p = (TMemBlock *) heap;
 	while (p != NULL) {
 		if (ISFREE(p)) {
 			startofs = (p->ofs + mask) & ~mask;
-			if ( startofs < startSearch ) {
+			if (startofs < startSearch) {
 				startofs = startSearch;
 			}
-			endofs = startofs+size;
-			if (endofs <= (p->ofs+p->size))
+			endofs = startofs + size;
+			if (endofs <= (p->ofs + p->size))
 				break;
 		}
 		p = p->next;
 	}
 	if (p == NULL)
 		return NULL;
-	p = SliceBlock(p,startofs,size,0,mask+1);
+	p = SliceBlock(p, startofs, size, 0, mask + 1);
 	p->heap = heap;
 	return p;
 }
 
-static __inline__ int Join2Blocks(TMemBlock *p)
+static __inline__ int Join2Blocks(TMemBlock * p)
 {
 	if (p->free && p->next && p->next->free) {
 		TMemBlock *q = p->next;
@@ -321,11 +318,11 @@ int mmFreeMem(PMemBlock b)
 	p->free = 1;
 	Join2Blocks(p);
 	if (prev)
-	Join2Blocks(prev);
+		Join2Blocks(prev);
 	return 0;
 }
 
-int mmReserveMem(memHeap_t *heap, int offset,int size)
+int mmReserveMem(memHeap_t * heap, int offset, int size)
 {
 	int endofs;
 	TMemBlock *p;
@@ -334,10 +331,10 @@ int mmReserveMem(memHeap_t *heap, int offset,int size)
 		return -1;
 
 	endofs = offset + size;
-	p = (TMemBlock *)heap;
+	p = (TMemBlock *) heap;
 	while (p && p->ofs <= offset) {
-		if (ISFREE(p) && endofs <= (p->ofs+p->size)) {
-			SliceBlock(p,offset,size,1,1);
+		if (ISFREE(p) && endofs <= (p->ofs + p->size)) {
+			SliceBlock(p, offset, size, 1, 1);
 			return 0;
 		}
 		p = p->next;
@@ -345,14 +342,14 @@ int mmReserveMem(memHeap_t *heap, int offset,int size)
 	return -1;
 }
 
-int mmFreeReserved(memHeap_t *heap, int offset)
+int mmFreeReserved(memHeap_t * heap, int offset)
 {
-	TMemBlock *p,*prev;
+	TMemBlock *p, *prev;
 
 	if (heap == NULL)
 		return -1;
 
-	p = (TMemBlock *)heap;
+	p = (TMemBlock *) heap;
 	prev = NULL;
 	while (p != NULL && p->ofs != offset) {
 		prev = p;
@@ -369,14 +366,14 @@ int mmFreeReserved(memHeap_t *heap, int offset)
 	return 0;
 }
 
-void mmDestroy(memHeap_t *heap)
+void mmDestroy(memHeap_t * heap)
 {
-	TMemBlock *p,*q;
+	TMemBlock *p, *q;
 
 	if (heap == NULL)
 		return;
 
-	p = (TMemBlock *)heap;
+	p = (TMemBlock *) heap;
 	while (p != NULL) {
 		q = p->next;
 		drm_free(p, sizeof(TMemBlock), DRM_MEM_DRIVER);
diff --git a/shared-core/sis_ds.h b/shared-core/sis_ds.h
index bbd3fe1b..13e94b23 100644
--- a/shared-core/sis_ds.h
+++ b/shared-core/sis_ds.h
@@ -10,11 +10,11 @@
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
@@ -22,10 +22,10 @@
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
- * 
+ *
  * Authors:
  *    Sung-Ching Lin <sclin@sis.com.tw>
- * 
+ *
  */
 
 #ifndef __SIS_DS_H__
@@ -50,11 +50,11 @@ typedef struct {
 } set_t;
 
 set_t *setInit(void);
-int setAdd(set_t *set, ITEM_TYPE item);
-int setDel(set_t *set, ITEM_TYPE item);
-int setFirst(set_t *set, ITEM_TYPE *item);
-int setNext(set_t *set, ITEM_TYPE *item);
-int setDestroy(set_t *set);
+int setAdd(set_t * set, ITEM_TYPE item);
+int setDel(set_t * set, ITEM_TYPE item);
+int setFirst(set_t * set, ITEM_TYPE * item);
+int setNext(set_t * set, ITEM_TYPE * item);
+int setDestroy(set_t * set);
 
 /*
  * GLX Hardware Device Driver common code
@@ -73,9 +73,9 @@ int setDestroy(set_t *set);
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 
+ * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  */
@@ -83,7 +83,7 @@ int setDestroy(set_t *set);
 struct mem_block_t {
 	struct mem_block_t *next;
 	struct mem_block_t *heap;
-	int ofs,size;
+	int ofs, size;
 	int align;
 	int free:1;
 	int reserved:1;
@@ -109,15 +109,13 @@ static __inline__ void mmMarkReserved(PMemBlock b)
 	b->reserved = 1;
 }
 
-/* 
+/*
  * input: total size in bytes
  * return: a heap pointer if OK, NULL if error
  */
-memHeap_t *mmInit( int ofs, int size );
+memHeap_t *mmInit(int ofs, int size);
 
-memHeap_t *mmAddRange( memHeap_t *heap,
-		       int ofs,
-		       int size );
+memHeap_t *mmAddRange(memHeap_t * heap, int ofs, int size);
 
 /*
  * Allocate 'size' bytes with 2^align2 bytes alignment,
@@ -129,19 +127,19 @@ memHeap_t *mmAddRange( memHeap_t *heap,
  *		startSearch = linear offset from start of heap to begin search
  * return: pointer to the allocated block, 0 if error
  */
-PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch );
+PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch);
 
 /*
  * Returns 1 if the block 'b' is part of the heap 'heap'
  */
-int mmBlockInHeap( PMemBlock heap, PMemBlock b );
+int mmBlockInHeap(PMemBlock heap, PMemBlock b);
 
 /*
  * Free block starts at offset
  * input: pointer to a block
  * return: 0 if OK, -1 if error
  */
-int mmFreeMem( PMemBlock b );
+int mmFreeMem(PMemBlock b);
 
 /*
  * Reserve 'size' bytes block start at offset
@@ -150,15 +148,15 @@ int mmFreeMem( PMemBlock b );
  * input: size, offset
  * output: 0 if OK, -1 if error
  */
-int mmReserveMem( memHeap_t *heap, int offset,int size );
-int mmFreeReserved( memHeap_t *heap, int offset );
+int mmReserveMem(memHeap_t * heap, int offset, int size);
+int mmFreeReserved(memHeap_t * heap, int offset);
 
 /*
  * destroy MM
  */
-void mmDestroy( memHeap_t *mmInit );
+void mmDestroy(memHeap_t * mmInit);
 
 /* For debuging purpose. */
-void mmDumpMemInfo( memHeap_t *mmInit );
+void mmDumpMemInfo(memHeap_t * mmInit);
 
-#endif /* __SIS_DS_H__ */
+#endif				/* __SIS_DS_H__ */
diff --git a/shared-core/sis_mm.c b/shared-core/sis_mm.c
index a895e0b8..7b0a2a43 100644
--- a/shared-core/sis_mm.c
+++ b/shared-core/sis_mm.c
@@ -10,11 +10,11 @@
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
@@ -22,16 +22,12 @@
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
- * 
+ *
  * Authors:
  *    Sung-Ching Lin <sclin@sis.com.tw>
- * 
+ *
  */
 
-#include "drmP.h"
-#include "sis_drm.h"
-#include "sis_drv.h"
-#include "sis_ds.h"
 #if defined(__linux__) && defined(CONFIG_FB_SIS)
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
 #include <video/sisfb.h>
@@ -39,27 +35,29 @@
 #include <linux/sisfb.h>
 #endif
 #endif
+#include "drmP.h"
+#include "sis_drm.h"
+#include "sis_drv.h"
+#include "sis_ds.h"
 
 #define MAX_CONTEXT 100
-#define VIDEO_TYPE 0 
+#define VIDEO_TYPE 0
 #define AGP_TYPE 1
 
 typedef struct {
 	int used;
 	int context;
-	set_t *sets[2]; /* 0 for video, 1 for AGP */
+	set_t *sets[2];		/* 0 for video, 1 for AGP */
 } sis_context_t;
 
 static sis_context_t global_ppriv[MAX_CONTEXT];
 
-
 static int add_alloc_set(int context, int type, unsigned int val)
 {
 	int i, retval = 0;
-	
+
 	for (i = 0; i < MAX_CONTEXT; i++) {
-		if (global_ppriv[i].used && global_ppriv[i].context == context)
-		{
+		if (global_ppriv[i].used && global_ppriv[i].context == context) {
 			retval = setAdd(global_ppriv[i].sets[type], val);
 			break;
 		}
@@ -68,12 +66,11 @@ static int add_alloc_set(int context, int type, unsigned int val)
 }
 
 static int del_alloc_set(int context, int type, unsigned int val)
-{  
+{
 	int i, retval = 0;
 
 	for (i = 0; i < MAX_CONTEXT; i++) {
-		if (global_ppriv[i].used && global_ppriv[i].context == context)
-		{
+		if (global_ppriv[i].used && global_ppriv[i].context == context) {
 			retval = setDel(global_ppriv[i].sets[type], val);
 			break;
 		}
@@ -81,15 +78,15 @@ static int del_alloc_set(int context, int type, unsigned int val)
 	return retval;
 }
 
-/* fb management via fb device */ 
+/* fb management via fb device */
 #if defined(__linux__) && defined(CONFIG_FB_SIS)
 
-int sis_fb_init( DRM_IOCTL_ARGS )
+int sis_fb_init(DRM_IOCTL_ARGS)
 {
 	return 0;
 }
 
-int sis_fb_alloc( DRM_IOCTL_ARGS )
+int sis_fb_alloc(DRM_IOCTL_ARGS)
 {
 	drm_sis_mem_t fb;
 	struct sis_memreq req;
@@ -109,7 +106,7 @@ int sis_fb_alloc( DRM_IOCTL_ARGS )
 			sis_free(req.offset);
 			retval = DRM_ERR(EINVAL);
 		}
-	} else {  
+	} else {
 		fb.offset = 0;
 		fb.size = 0;
 		fb.free = 0;
@@ -122,12 +119,12 @@ int sis_fb_alloc( DRM_IOCTL_ARGS )
 	return retval;
 }
 
-int sis_fb_free( DRM_IOCTL_ARGS )
+int sis_fb_free(DRM_IOCTL_ARGS)
 {
 	drm_sis_mem_t fb;
 	int retval = 0;
 
-	DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *)data, sizeof(fb));
+	DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *) data, sizeof(fb));
 
 	if (!fb.free)
 		return DRM_ERR(EINVAL);
@@ -153,17 +150,17 @@ int sis_fb_free( DRM_IOCTL_ARGS )
  *    X driver/sisfb                                  HW-   Command-
  *  framebuffer memory           DRI heap           Cursor   queue
  */
-int sis_fb_init( DRM_IOCTL_ARGS )
+int sis_fb_init(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_sis_private_t *dev_priv = dev->dev_private;
 	drm_sis_fb_t fb;
 
-	DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_fb_t __user *)data, sizeof(fb));
+	DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_fb_t __user *) data, sizeof(fb));
 
 	if (dev_priv == NULL) {
 		dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t),
-		    DRM_MEM_DRIVER);
+					      DRM_MEM_DRIVER);
 		dev_priv = dev->dev_private;
 		if (dev_priv == NULL)
 			return ENOMEM;
@@ -179,7 +176,7 @@ int sis_fb_init( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-int sis_fb_alloc( DRM_IOCTL_ARGS )
+int sis_fb_alloc(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_sis_private_t *dev_priv = dev->dev_private;
@@ -190,9 +187,9 @@ int sis_fb_alloc( DRM_IOCTL_ARGS )
 
 	if (dev_priv == NULL || dev_priv->FBHeap == NULL)
 		return DRM_ERR(EINVAL);
-  
+
 	DRM_COPY_FROM_USER_IOCTL(fb, argp, sizeof(fb));
-  
+
 	block = mmAllocMem(dev_priv->FBHeap, fb.size, 0, 0);
 	if (block) {
 		/* TODO */
@@ -200,7 +197,7 @@ int sis_fb_alloc( DRM_IOCTL_ARGS )
 		fb.free = (unsigned long)block;
 		if (!add_alloc_set(fb.context, VIDEO_TYPE, fb.free)) {
 			DRM_DEBUG("adding to allocation set fails\n");
-			mmFreeMem((PMemBlock)fb.free);
+			mmFreeMem((PMemBlock) fb.free);
 			retval = DRM_ERR(EINVAL);
 		}
 	} else {
@@ -216,7 +213,7 @@ int sis_fb_alloc( DRM_IOCTL_ARGS )
 	return retval;
 }
 
-int sis_fb_free( DRM_IOCTL_ARGS )
+int sis_fb_free(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_sis_private_t *dev_priv = dev->dev_private;
@@ -225,14 +222,14 @@ int sis_fb_free( DRM_IOCTL_ARGS )
 	if (dev_priv == NULL || dev_priv->FBHeap == NULL)
 		return DRM_ERR(EINVAL);
 
-	DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *)data, sizeof(fb));
+	DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *) data, sizeof(fb));
 
-	if (!mmBlockInHeap(dev_priv->FBHeap, (PMemBlock)fb.free))
+	if (!mmBlockInHeap(dev_priv->FBHeap, (PMemBlock) fb.free))
 		return DRM_ERR(EINVAL);
 
 	if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free))
 		return DRM_ERR(EINVAL);
-	mmFreeMem((PMemBlock)fb.free);
+	mmFreeMem((PMemBlock) fb.free);
 
 	DRM_DEBUG("free fb, free = 0x%lx\n", fb.free);
 
@@ -241,9 +238,9 @@ int sis_fb_free( DRM_IOCTL_ARGS )
 
 #endif
 
-/* agp memory management */ 
+/* agp memory management */
 
-int sis_ioctl_agp_init( DRM_IOCTL_ARGS )
+int sis_ioctl_agp_init(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_sis_private_t *dev_priv = dev->dev_private;
@@ -251,7 +248,7 @@ int sis_ioctl_agp_init( DRM_IOCTL_ARGS )
 
 	if (dev_priv == NULL) {
 		dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t),
-		    DRM_MEM_DRIVER);
+					      DRM_MEM_DRIVER);
 		dev_priv = dev->dev_private;
 		if (dev_priv == NULL)
 			return ENOMEM;
@@ -260,16 +257,17 @@ int sis_ioctl_agp_init( DRM_IOCTL_ARGS )
 	if (dev_priv->AGPHeap != NULL)
 		return DRM_ERR(EINVAL);
 
-	DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_agp_t __user *)data, sizeof(agp));
+	DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_agp_t __user *) data,
+				 sizeof(agp));
 
 	dev_priv->AGPHeap = mmInit(agp.offset, agp.size);
 
 	DRM_DEBUG("offset = %u, size = %u", agp.offset, agp.size);
-  
+
 	return 0;
 }
 
-int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS )
+int sis_ioctl_agp_alloc(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_sis_private_t *dev_priv = dev->dev_private;
@@ -277,12 +275,12 @@ int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS )
 	drm_sis_mem_t agp;
 	PMemBlock block;
 	int retval = 0;
-   
+
 	if (dev_priv == NULL || dev_priv->AGPHeap == NULL)
 		return DRM_ERR(EINVAL);
-  
+
 	DRM_COPY_FROM_USER_IOCTL(agp, argp, sizeof(agp));
-  
+
 	block = mmAllocMem(dev_priv->AGPHeap, agp.size, 0, 0);
 	if (block) {
 		/* TODO */
@@ -290,10 +288,10 @@ int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS )
 		agp.free = (unsigned long)block;
 		if (!add_alloc_set(agp.context, AGP_TYPE, agp.free)) {
 			DRM_DEBUG("adding to allocation set fails\n");
-			mmFreeMem((PMemBlock)agp.free);
+			mmFreeMem((PMemBlock) agp.free);
 			retval = -1;
 		}
-	} else {  
+	} else {
 		agp.offset = 0;
 		agp.size = 0;
 		agp.free = 0;
@@ -306,7 +304,7 @@ int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS )
 	return retval;
 }
 
-int sis_ioctl_agp_free( DRM_IOCTL_ARGS )
+int sis_ioctl_agp_free(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_sis_private_t *dev_priv = dev->dev_private;
@@ -315,12 +313,13 @@ int sis_ioctl_agp_free( DRM_IOCTL_ARGS )
 	if (dev_priv == NULL || dev_priv->AGPHeap == NULL)
 		return DRM_ERR(EINVAL);
 
-	DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_mem_t __user *)data, sizeof(agp));
+	DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_mem_t __user *) data,
+				 sizeof(agp));
 
-	if (!mmBlockInHeap(dev_priv->AGPHeap, (PMemBlock)agp.free))
+	if (!mmBlockInHeap(dev_priv->AGPHeap, (PMemBlock) agp.free))
 		return DRM_ERR(EINVAL);
 
-	mmFreeMem((PMemBlock)agp.free);
+	mmFreeMem((PMemBlock) agp.free);
 	if (!del_alloc_set(agp.context, AGP_TYPE, agp.free))
 		return DRM_ERR(EINVAL);
 
@@ -333,31 +332,30 @@ int sis_init_context(struct drm_device *dev, int context)
 {
 	int i;
 
-	for (i = 0; i < MAX_CONTEXT ; i++) {
+	for (i = 0; i < MAX_CONTEXT; i++) {
 		if (global_ppriv[i].used &&
 		    (global_ppriv[i].context == context))
 			break;
 	}
 
 	if (i >= MAX_CONTEXT) {
-		for (i = 0; i < MAX_CONTEXT ; i++) {
+		for (i = 0; i < MAX_CONTEXT; i++) {
 			if (!global_ppriv[i].used) {
 				global_ppriv[i].context = context;
 				global_ppriv[i].used = 1;
 				global_ppriv[i].sets[0] = setInit();
 				global_ppriv[i].sets[1] = setInit();
 				DRM_DEBUG("init allocation set, socket=%d, "
-				    "context = %d\n", i, context);
+					  "context = %d\n", i, context);
 				break;
 			}
 		}
 		if ((i >= MAX_CONTEXT) || (global_ppriv[i].sets[0] == NULL) ||
-		    (global_ppriv[i].sets[1] == NULL))
-		{
+		    (global_ppriv[i].sets[1] == NULL)) {
 			return 0;
 		}
 	}
-	
+
 	return 1;
 }
 
@@ -365,7 +363,7 @@ int sis_final_context(struct drm_device *dev, int context)
 {
 	int i;
 
-	for (i=0; i<MAX_CONTEXT; i++) {
+	for (i = 0; i < MAX_CONTEXT; i++) {
 		if (global_ppriv[i].used &&
 		    (global_ppriv[i].context == context))
 			break;
@@ -386,7 +384,7 @@ int sis_final_context(struct drm_device *dev, int context)
 #if defined(__linux__) && defined(CONFIG_FB_SIS)
 			sis_free(item);
 #else
-			mmFreeMem((PMemBlock)item);
+			mmFreeMem((PMemBlock) item);
 #endif
 			retval = setNext(set, &item);
 		}
@@ -397,13 +395,13 @@ int sis_final_context(struct drm_device *dev, int context)
 		retval = setFirst(set, &item);
 		while (retval) {
 			DRM_DEBUG("free agp memory 0x%lx\n", item);
-			mmFreeMem((PMemBlock)item);
+			mmFreeMem((PMemBlock) item);
 			retval = setNext(set, &item);
 		}
 		setDestroy(set);
 
-		global_ppriv[i].used = 0;	  
-        }
-	
+		global_ppriv[i].used = 0;
+	}
+
 	return 1;
 }
diff --git a/shared-core/tdfx_drv.h b/shared-core/tdfx_drv.h
index a582a3db..857be434 100644
--- a/shared-core/tdfx_drv.h
+++ b/shared-core/tdfx_drv.h
@@ -30,10 +30,6 @@
 #ifndef __TDFX_H__
 #define __TDFX_H__
 
-/* This remains constant for all DRM template files.
- */
-#define DRM(x) tdfx_##x
-
 /* General customization:
  */
 
diff --git a/shared-core/via_3d_reg.h b/shared-core/via_3d_reg.h
index 424ce281..3bb59a34 100644
--- a/shared-core/via_3d_reg.h
+++ b/shared-core/via_3d_reg.h
@@ -51,8 +51,8 @@
 
 /* Transmission Space
  */
-#define HC_REG_Hpara0           0x0040          
-#define HC_REG_HpataAF          0x02fc          
+#define HC_REG_Hpara0           0x0040
+#define HC_REG_HpataAF          0x02fc
 
 /* Read
  */
@@ -174,7 +174,7 @@
 /* Command
  * Command A
  */
-#define HC_HCmdHeader_MASK      0xfe000000  /*0xffe00000*/
+#define HC_HCmdHeader_MASK      0xfe000000	/*0xffe00000 */
 #define HC_HE3Fire_MASK         0x00100000
 #define HC_HPMType_MASK         0x000f0000
 #define HC_HEFlag_MASK          0x0000e000
@@ -302,10 +302,10 @@
 #define HC_HZWTMD_GE            0x00060000
 #define HC_HZWTMD_AllPass       0x00070000
 #define HC_HEBEBias_SHIFT       8
-/* HC_SubA_HZWCDL          0x0016 
+/* HC_SubA_HZWCDL          0x0016
  */
 #define HC_HZWCDL_MASK          0x00ffffff
-/* HC_SubA_HZWCTAGnum      0x0017 
+/* HC_SubA_HZWCTAGnum      0x0017
  */
 #define HC_HZWCTAGnum_MASK      0x00ff0000
 #define HC_HZWCTAGnum_SHIFT     16
@@ -1046,7 +1046,7 @@
 #define HC_XTC_Atex             0x00000007
 #define HC_XTC_Acur             0x00000008
 #define HC_XTC_HTXnTBLRC        0x00000009
-#define HC_XTC_Ctexnext         0x0000000a 
+#define HC_XTC_Ctexnext         0x0000000a
 /*--
  */
 #define HC_HTXnTBLCsat_MASK     0x00800000
@@ -1066,7 +1066,7 @@
 #define HC_HTXnTBLCa_Atex       (HC_XTC_Atex << 14)
 #define HC_HTXnTBLCa_Acur       (HC_XTC_Acur << 14)
 #define HC_HTXnTBLCa_HTXnTBLRC  (HC_XTC_HTXnTBLRC << 14)
-#define HC_HTXnTBLCa_Ctexnext   (HC_XTC_Ctexnext << 14) 
+#define HC_HTXnTBLCa_Ctexnext   (HC_XTC_Ctexnext << 14)
 #define HC_HTXnTBLCb_TOPC       (HC_XTC_TOPC << 7)
 #define HC_HTXnTBLCb_InvTOPC    (HC_XTC_InvTOPC << 7)
 #define HC_HTXnTBLCb_TOPCp5     (HC_XTC_TOPCp5 << 7)
@@ -1080,7 +1080,7 @@
 #define HC_HTXnTBLCb_Atex       (HC_XTC_Atex << 7)
 #define HC_HTXnTBLCb_Acur       (HC_XTC_Acur << 7)
 #define HC_HTXnTBLCb_HTXnTBLRC  (HC_XTC_HTXnTBLRC << 7)
-#define HC_HTXnTBLCb_Ctexnext   (HC_XTC_Ctexnext << 7) 
+#define HC_HTXnTBLCb_Ctexnext   (HC_XTC_Ctexnext << 7)
 #define HC_HTXnTBLCc_TOPC       (HC_XTC_TOPC << 0)
 #define HC_HTXnTBLCc_InvTOPC    (HC_XTC_InvTOPC << 0)
 #define HC_HTXnTBLCc_TOPCp5     (HC_XTC_TOPCp5 << 0)
@@ -1094,7 +1094,7 @@
 #define HC_HTXnTBLCc_Atex       (HC_XTC_Atex << 0)
 #define HC_HTXnTBLCc_Acur       (HC_XTC_Acur << 0)
 #define HC_HTXnTBLCc_HTXnTBLRC  (HC_XTC_HTXnTBLRC << 0)
-#define HC_HTXnTBLCc_Ctexnext   (HC_XTC_Ctexnext << 0) 
+#define HC_HTXnTBLCc_Ctexnext   (HC_XTC_Ctexnext << 0)
 /* HC_SubA_HTXnTBLCop      0x0081
  */
 #define HC_HTXnTBLdot_MASK      0x00c00000
@@ -1164,7 +1164,7 @@
 #define HC_XTA_Acur             0x00000002
 #define HC_XTA_HTXnTBLRA        0x00000003
 #define HC_XTA_Atex             0x00000004
-#define HC_XTA_Atexnext         0x00000005 
+#define HC_XTA_Atexnext         0x00000005
 /*--
  */
 #define HC_HTXnTBLAsat_MASK     0x00800000
@@ -1181,7 +1181,7 @@
 #define HC_HTXnTBLAa_Acur       (HC_XTA_Acur << 14)
 #define HC_HTXnTBLAa_HTXnTBLRA  (HC_XTA_HTXnTBLRA << 14)
 #define HC_HTXnTBLAa_Atex       (HC_XTA_Atex << 14)
-#define HC_HTXnTBLAa_Atexnext   (HC_XTA_Atexnext << 14) 
+#define HC_HTXnTBLAa_Atexnext   (HC_XTA_Atexnext << 14)
 #define HC_HTXnTBLAb_TOPA       (HC_XTA_TOPA << 7)
 #define HC_HTXnTBLAb_InvTOPA    (HC_XTA_InvTOPA << 7)
 #define HC_HTXnTBLAb_TOPAp5     (HC_XTA_TOPAp5 << 7)
@@ -1190,7 +1190,7 @@
 #define HC_HTXnTBLAb_Acur       (HC_XTA_Acur << 7)
 #define HC_HTXnTBLAb_HTXnTBLRA  (HC_XTA_HTXnTBLRA << 7)
 #define HC_HTXnTBLAb_Atex       (HC_XTA_Atex << 7)
-#define HC_HTXnTBLAb_Atexnext   (HC_XTA_Atexnext << 7) 
+#define HC_HTXnTBLAb_Atexnext   (HC_XTA_Atexnext << 7)
 #define HC_HTXnTBLAc_TOPA       (HC_XTA_TOPA << 0)
 #define HC_HTXnTBLAc_InvTOPA    (HC_XTA_InvTOPA << 0)
 #define HC_HTXnTBLAc_TOPAp5     (HC_XTA_TOPAp5 << 0)
@@ -1199,7 +1199,7 @@
 #define HC_HTXnTBLAc_Acur       (HC_XTA_Acur << 0)
 #define HC_HTXnTBLAc_HTXnTBLRA  (HC_XTA_HTXnTBLRA << 0)
 #define HC_HTXnTBLAc_Atex       (HC_XTA_Atex << 0)
-#define HC_HTXnTBLAc_Atexnext   (HC_XTA_Atexnext << 0) 
+#define HC_HTXnTBLAc_Atexnext   (HC_XTA_Atexnext << 0)
 /* HC_SubA_HTXnTBLRAa      0x0089
  */
 #define HC_HTXnTBLRAa_MASK      0x00ff0000
@@ -1581,44 +1581,44 @@
 /******************************************************************************
 ** Define the AGP command header.
 ******************************************************************************/
-#define HC_ACMD_MASK            0xfe000000      
-#define HC_ACMD_SUB_MASK        0x0c000000      
-#define HC_ACMD_HCmdA           0xee000000      
-#define HC_ACMD_HCmdB           0xec000000      
-#define HC_ACMD_HCmdC           0xea000000      
-#define HC_ACMD_H1              0xf0000000      
-#define HC_ACMD_H2              0xf2000000      
-#define HC_ACMD_H3              0xf4000000      
-#define HC_ACMD_H4              0xf6000000      
+#define HC_ACMD_MASK            0xfe000000
+#define HC_ACMD_SUB_MASK        0x0c000000
+#define HC_ACMD_HCmdA           0xee000000
+#define HC_ACMD_HCmdB           0xec000000
+#define HC_ACMD_HCmdC           0xea000000
+#define HC_ACMD_H1              0xf0000000
+#define HC_ACMD_H2              0xf2000000
+#define HC_ACMD_H3              0xf4000000
+#define HC_ACMD_H4              0xf6000000
 
 #define HC_ACMD_H1IO_MASK       0x000001ff
-#define HC_ACMD_H2IO1_MASK      0x001ff000      
+#define HC_ACMD_H2IO1_MASK      0x001ff000
 #define HC_ACMD_H2IO2_MASK      0x000001ff
-#define HC_ACMD_H2IO1_SHIFT     12              
+#define HC_ACMD_H2IO1_SHIFT     12
 #define HC_ACMD_H2IO2_SHIFT     0
 #define HC_ACMD_H3IO_MASK       0x000001ff
-#define HC_ACMD_H3COUNT_MASK    0x01fff000      
-#define HC_ACMD_H3COUNT_SHIFT   12              
+#define HC_ACMD_H3COUNT_MASK    0x01fff000
+#define HC_ACMD_H3COUNT_SHIFT   12
 #define HC_ACMD_H4ID_MASK       0x000001ff
 #define HC_ACMD_H4COUNT_MASK    0x01fffe00
 #define HC_ACMD_H4COUNT_SHIFT   9
 
 /********************************************************************************
-** Define Header 
+** Define Header
 ********************************************************************************/
 #define HC_HEADER2		0xF210F110
 
 /********************************************************************************
-** Define Dummy Value 
+** Define Dummy Value
 ********************************************************************************/
 #define HC_DUMMY		0xCCCCCCCC
 /********************************************************************************
-** Define for DMA use 
+** Define for DMA use
 ********************************************************************************/
 #define HALCYON_HEADER2     0XF210F110
-#define HALCYON_FIRECMD     0XEE100000  
+#define HALCYON_FIRECMD     0XEE100000
 #define HALCYON_FIREMASK    0XFFF00000
-#define HALCYON_CMDB        0XEC000000  
+#define HALCYON_CMDB        0XEC000000
 #define HALCYON_CMDBMASK    0XFFFE0000
 #define HALCYON_SUB_ADDR0   0X00000000
 #define HALCYON_HEADER1MASK 0XFFFFFF00
diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c
index 493c0b00..a48cb883 100644
--- a/shared-core/via_dma.c
+++ b/shared-core/via_dma.c
@@ -1,13 +1,13 @@
 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
  */
 /**************************************************************************
- * 
+ *
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
  *
  * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
  * All Rights Reserved.
- * 
+ *
  **************************************************************************/
 
 #include "drmP.h"
@@ -21,14 +21,14 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv);
 static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
 static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
-static int  via_wait_idle(drm_via_private_t * dev_priv);
+static int via_wait_idle(drm_via_private_t * dev_priv);
 
 static inline int
 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
 {
 	uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 	uint32_t cur_addr, hw_addr, next_addr;
-	volatile uint32_t * hw_addr_ptr;
+	volatile uint32_t *hw_addr_ptr;
 	uint32_t count;
 	hw_addr_ptr = dev_priv->hw_addr_ptr;
 	cur_addr = agp_base + dev_priv->dma_low;
@@ -38,12 +38,13 @@ via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
 	 * a large 64KB window between buffer head and tail.
 	 */
 	next_addr = cur_addr + size + 64 * 1024;
-	count = 1000000; /* How long is this? */
+	count = 1000000;	/* How long is this? */
 	do {
 		hw_addr = *hw_addr_ptr;
 		if (count-- == 0) {
-			DRM_ERROR("via_cmdbuf_wait timed out hw %x dma_low %x\n",
-					hw_addr, dev_priv->dma_low);
+			DRM_ERROR
+			    ("via_cmdbuf_wait timed out hw %x dma_low %x\n",
+			     hw_addr, dev_priv->dma_low);
 			return -1;
 		}
 	} while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
@@ -56,8 +57,8 @@ via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
  *
  * Returns virtual pointer to ring buffer.
  */
-static inline uint32_t *
-via_check_dma(drm_via_private_t * dev_priv, unsigned int size)
+static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
+				      unsigned int size)
 {
 	if ((dev_priv->dma_low + size + 0x400) > dev_priv->dma_high) {
 		via_cmdbuf_rewind(dev_priv);
@@ -66,19 +67,19 @@ via_check_dma(drm_via_private_t * dev_priv, unsigned int size)
 		return NULL;
 	}
 
-	return (uint32_t*)(dev_priv->dma_ptr + dev_priv->dma_low);
+	return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 }
 
-int via_dma_cleanup(drm_device_t *dev)
+int via_dma_cleanup(drm_device_t * dev)
 {
 	if (dev->dev_private) {
-		drm_via_private_t *dev_priv = 
-				(drm_via_private_t *) dev->dev_private;
+		drm_via_private_t *dev_priv =
+		    (drm_via_private_t *) dev->dev_private;
 
 		if (dev_priv->ring.virtual_start) {
 			via_cmdbuf_reset(dev_priv);
 
-			drm_core_ioremapfree( &dev_priv->ring.map, dev);
+			drm_core_ioremapfree(&dev_priv->ring.map, dev);
 			dev_priv->ring.virtual_start = NULL;
 		}
 	}
@@ -86,10 +87,9 @@ int via_dma_cleanup(drm_device_t *dev)
 	return 0;
 }
 
-
-static int via_initialize(drm_device_t *dev, 
-			       drm_via_private_t *dev_priv,
-			       drm_via_dma_init_t *init)
+static int via_initialize(drm_device_t * dev,
+			  drm_via_private_t * dev_priv,
+			  drm_via_dma_init_t * init)
 {
 	if (!dev_priv || !dev_priv->mmio) {
 		DRM_ERROR("via_dma_init called before via_map_init\n");
@@ -98,7 +98,7 @@ static int via_initialize(drm_device_t *dev,
 
 	if (dev_priv->ring.virtual_start != NULL) {
 		DRM_ERROR("%s called again without calling cleanup\n",
-				__FUNCTION__);
+			  __FUNCTION__);
 		return DRM_ERR(EFAULT);
 	}
 
@@ -108,12 +108,12 @@ static int via_initialize(drm_device_t *dev,
 	dev_priv->ring.map.flags = 0;
 	dev_priv->ring.map.mtrr = 0;
 
-	drm_core_ioremap( &dev_priv->ring.map, dev );
+	drm_core_ioremap(&dev_priv->ring.map, dev);
 
 	if (dev_priv->ring.map.handle == NULL) {
 		via_dma_cleanup(dev);
 		DRM_ERROR("can not ioremap virtual address for"
-				" ring buffer\n");
+			  " ring buffer\n");
 		return DRM_ERR(ENOMEM);
 	}
 
@@ -131,17 +131,17 @@ static int via_initialize(drm_device_t *dev,
 	return 0;
 }
 
-
-int via_dma_init( DRM_IOCTL_ARGS )
+int via_dma_init(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
-	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
+	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 	drm_via_dma_init_t init;
 	int retcode = 0;
 
-	DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t *)data, sizeof(init));
+	DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t *) data,
+				 sizeof(init));
 
-	switch(init.func) {
+	switch (init.func) {
 	case VIA_INIT_DMA:
 		retcode = via_initialize(dev, dev_priv, &init);
 		break;
@@ -156,12 +156,10 @@ int via_dma_init( DRM_IOCTL_ARGS )
 	return retcode;
 }
 
-
-static int via_dispatch_cmdbuffer(drm_device_t *dev, 
-				   drm_via_cmdbuffer_t *cmd )
+static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
 {
 	drm_via_private_t *dev_priv = dev->dev_private;
-	uint32_t * vb;
+	uint32_t *vb;
 	vb = via_check_dma(dev_priv, cmd->size);
 	if (vb == NULL) {
 		return DRM_ERR(EAGAIN);
@@ -175,8 +173,7 @@ static int via_dispatch_cmdbuffer(drm_device_t *dev,
 	return 0;
 }
 
-
-static int via_quiescent(drm_device_t *dev)
+static int via_quiescent(drm_device_t * dev)
 {
 	drm_via_private_t *dev_priv = dev->dev_private;
 
@@ -186,37 +183,35 @@ static int via_quiescent(drm_device_t *dev)
 	return 0;
 }
 
-
-int via_flush_ioctl( DRM_IOCTL_ARGS )
+int via_flush_ioctl(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 
-	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
 		DRM_ERROR("via_flush_ioctl called without lock held\n");
 		return DRM_ERR(EINVAL);
 	}
 
-	return via_quiescent(dev); 
+	return via_quiescent(dev);
 }
 
-
-int via_cmdbuffer( DRM_IOCTL_ARGS )
+int via_cmdbuffer(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_via_cmdbuffer_t cmdbuf;
 	int ret;
 
-	DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_via_cmdbuffer_t *)data, 
-			sizeof(cmdbuf) );
+	DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t *) data,
+				 sizeof(cmdbuf));
 
 	DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
 
-	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
 		DRM_ERROR("via_cmdbuffer called without lock held\n");
 		return DRM_ERR(EINVAL);
 	}
 
-	ret = via_dispatch_cmdbuffer( dev, &cmdbuf );
+	ret = via_dispatch_cmdbuffer(dev, &cmdbuf);
 	if (ret) {
 		return ret;
 	}
@@ -224,39 +219,39 @@ int via_cmdbuffer( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-static int via_parse_pci_cmdbuffer( drm_device_t *dev, const char *buf, 
-				    unsigned int size )
+static int via_parse_pci_cmdbuffer(drm_device_t * dev, const char *buf,
+				   unsigned int size)
 {
 	drm_via_private_t *dev_priv = dev->dev_private;
 	uint32_t offset, value;
-	const uint32_t *regbuf = (uint32_t *)buf;
+	const uint32_t *regbuf = (uint32_t *) buf;
 	unsigned int i;
 
-	size >>=3 ;
-	for (i=0; i<size; ++i) {
-		offset = *regbuf; 
+	size >>= 3;
+	for (i = 0; i < size; ++i) {
+		offset = *regbuf;
 		regbuf += 2;
-		if ((offset > ((0x7FF >> 2) | VIA_2D_CMD)) && 
-		    (offset < ((0xC00 >> 2) | VIA_2D_CMD)) ) {
+		if ((offset > ((0x7FF >> 2) | VIA_2D_CMD)) &&
+		    (offset < ((0xC00 >> 2) | VIA_2D_CMD))) {
 			DRM_DEBUG("Attempt to access Burst Command Area.\n");
-			return DRM_ERR( EINVAL );
+			return DRM_ERR(EINVAL);
 		} else if (offset > ((0xDFF >> 2) | VIA_2D_CMD)) {
 			DRM_DEBUG("Attempt to access DMA or VGA registers.\n");
-			return DRM_ERR( EINVAL );
+			return DRM_ERR(EINVAL);
 		}
 	}
-			
-	regbuf = (uint32_t *)buf;
-	for ( i=0; i<size; ++i ) {
+
+	regbuf = (uint32_t *) buf;
+	for (i = 0; i < size; ++i) {
 		offset = (*regbuf++ & ~VIA_2D_CMD) << 2;
 		value = *regbuf++;
-		VIA_WRITE( offset, value );
+		VIA_WRITE(offset, value);
 	}
 	return 0;
 }
-		
-static int via_dispatch_pci_cmdbuffer(drm_device_t *dev, 
-				      drm_via_cmdbuffer_t *cmd )
+
+static int via_dispatch_pci_cmdbuffer(drm_device_t * dev,
+				      drm_via_cmdbuffer_t * cmd)
 {
 	drm_via_private_t *dev_priv = dev->dev_private;
 	char *hugebuf;
@@ -269,42 +264,42 @@ static int via_dispatch_pci_cmdbuffer(drm_device_t *dev,
 	 * Small buffers must, on the other hand be handled fast.
 	 */
 
-	if ( cmd->size > VIA_MAX_PCI_SIZE ) {
-		return DRM_ERR( ENOMEM );
-	} else if ( cmd->size > VIA_PREALLOCATED_PCI_SIZE ) {
-	  if (NULL == (hugebuf = (char *) kmalloc( cmd-> size, GFP_KERNEL )))
-			return DRM_ERR( ENOMEM );
-		if (DRM_COPY_FROM_USER( hugebuf, cmd->buf, cmd->size ))
+	if (cmd->size > VIA_MAX_PCI_SIZE) {
+		return DRM_ERR(ENOMEM);
+	} else if (cmd->size > VIA_PREALLOCATED_PCI_SIZE) {
+		if (NULL == (hugebuf = (char *)kmalloc(cmd->size, GFP_KERNEL)))
+			return DRM_ERR(ENOMEM);
+		if (DRM_COPY_FROM_USER(hugebuf, cmd->buf, cmd->size))
 			return DRM_ERR(EFAULT);
-		ret = via_parse_pci_cmdbuffer( dev, hugebuf, cmd->size );
-		kfree( hugebuf );
+		ret = via_parse_pci_cmdbuffer(dev, hugebuf, cmd->size);
+		kfree(hugebuf);
 	} else {
-		if (DRM_COPY_FROM_USER( dev_priv->pci_buf, cmd->buf, cmd->size ))
+		if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 			return DRM_ERR(EFAULT);
-		ret = via_parse_pci_cmdbuffer( dev, dev_priv->pci_buf, cmd->size );
+		ret =
+		    via_parse_pci_cmdbuffer(dev, dev_priv->pci_buf, cmd->size);
 	}
 	return ret;
 }
 
-
-
-int via_pci_cmdbuffer( DRM_IOCTL_ARGS )
+int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_via_cmdbuffer_t cmdbuf;
 	int ret;
 
-	DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_via_cmdbuffer_t *)data, 
-			sizeof(cmdbuf) );
+	DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t *) data,
+				 sizeof(cmdbuf));
 
-	DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
+	DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf,
+		  cmdbuf.size);
 
-	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
 		DRM_ERROR("via_pci_cmdbuffer called without lock held\n");
 		return DRM_ERR(EINVAL);
 	}
 
-	ret = via_dispatch_pci_cmdbuffer( dev, &cmdbuf );
+	ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf);
 	if (ret) {
 		return ret;
 	}
@@ -312,9 +307,6 @@ int via_pci_cmdbuffer( DRM_IOCTL_ARGS )
 	return 0;
 }
 
-
-
-
 /************************************************************************/
 #include "via_3d_reg.h"
 
@@ -325,13 +317,12 @@ int via_pci_cmdbuffer( DRM_IOCTL_ARGS )
 #define VIA_REG_STATUS          0x400
 #define VIA_REG_TRANSET         0x43C
 #define VIA_REG_TRANSPACE       0x440
-                                                                                                                                                                                  
-/* VIA_REG_STATUS(0x400): Engine Status */
-#define VIA_CMD_RGTR_BUSY       0x00000080  /* Command Regulator is busy */
-#define VIA_2D_ENG_BUSY         0x00000001  /* 2D Engine is busy */
-#define VIA_3D_ENG_BUSY         0x00000002  /* 3D Engine is busy */
-#define VIA_VR_QUEUE_BUSY       0x00020000 /* Virtual Queue is busy */
 
+/* VIA_REG_STATUS(0x400): Engine Status */
+#define VIA_CMD_RGTR_BUSY       0x00000080	/* Command Regulator is busy */
+#define VIA_2D_ENG_BUSY         0x00000001	/* 2D Engine is busy */
+#define VIA_3D_ENG_BUSY         0x00000002	/* 3D Engine is busy */
+#define VIA_VR_QUEUE_BUSY       0x00020000	/* Virtual Queue is busy */
 
 #define SetReg2DAGP(nReg, nData) { \
 	*((uint32_t *)(vb)) = ((nReg) >> 2) | 0xF0000000; \
@@ -342,10 +333,10 @@ int via_pci_cmdbuffer( DRM_IOCTL_ARGS )
 
 static uint32_t via_swap_count = 0;
 
-static inline uint32_t *
-via_align_buffer(drm_via_private_t * dev_priv, uint32_t * vb, int qw_count)
+static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
+					 uint32_t * vb, int qw_count)
 {
-	for ( ; qw_count > 0; --qw_count) {
+	for (; qw_count > 0; --qw_count) {
 		*vb++ = (0xcc000000 | (dev_priv->dma_low & 0xffffff));
 		*vb++ = (0xdd400000 | via_swap_count);
 		dev_priv->dma_low += 8;
@@ -359,29 +350,28 @@ via_align_buffer(drm_via_private_t * dev_priv, uint32_t * vb, int qw_count)
  *
  * Returns virtual pointer to ring buffer.
  */
-static inline uint32_t * via_get_dma(drm_via_private_t * dev_priv)
+static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
 {
-	return (uint32_t*)(dev_priv->dma_ptr + dev_priv->dma_low);
+	return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 }
 
-
 static int via_wait_idle(drm_via_private_t * dev_priv)
 {
 	int count = 10000000;
 	while (count-- && (VIA_READ(VIA_REG_STATUS) &
-		(VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)));
+			   (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
+			    VIA_3D_ENG_BUSY))) ;
 	return count;
 }
 
-static inline void
-via_dummy_bitblt(drm_via_private_t * dev_priv)
+static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
 {
-	uint32_t * vb = via_get_dma(dev_priv);
-	/* GEDST*/
+	uint32_t *vb = via_get_dma(dev_priv);
+	/* GEDST */
 	SetReg2DAGP(0x0C, (0 | (0 << 16)));
-	/* GEWD*/
+	/* GEWD */
 	SetReg2DAGP(0x10, 0 | (0 << 16));
-	/* BITBLT*/
+	/* BITBLT */
 	SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
 }
 
@@ -393,7 +383,7 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
 	uint32_t end_addr, end_addr_lo;
 	uint32_t qw_pad_count;
 	uint32_t command;
-	uint32_t * vb;
+	uint32_t *vb;
 
 	dev_priv->dma_low = 0;
 	vb = via_get_dma(dev_priv);
@@ -405,28 +395,27 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
 	start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
 	end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
 	command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
-			((end_addr & 0xff000000) >> 16));
+		   ((end_addr & 0xff000000) >> 16));
 
-	*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET>>2)<<12) |
-			(VIA_REG_TRANSPACE>>2);
-	*vb++ = (HC_ParaType_PreCR<<16);
+	*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
+	    (VIA_REG_TRANSPACE >> 2);
+	*vb++ = (HC_ParaType_PreCR << 16);
 	dev_priv->dma_low += 8;
 
-	qw_pad_count = (CMDBUF_ALIGNMENT_SIZE>>3) -
-			((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
+	qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
+	    ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
 
-	pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count<<3);
-	pause_addr_lo = ((HC_SubA_HAGPBpL<<24) |
-			HC_HAGPBpID_PAUSE |
-			(pause_addr & 0xffffff));
-	pause_addr_hi = ((HC_SubA_HAGPBpH<<24) | (pause_addr >> 24));
+	pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
+	pause_addr_lo = ((HC_SubA_HAGPBpL << 24) |
+			 HC_HAGPBpID_PAUSE | (pause_addr & 0xffffff));
+	pause_addr_hi = ((HC_SubA_HAGPBpH << 24) | (pause_addr >> 24));
 
-	vb = via_align_buffer(dev_priv, vb, qw_pad_count-1);
+	vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
 
 	*vb++ = pause_addr_hi;
 	*vb++ = pause_addr_lo;
 	dev_priv->dma_low += 8;
-	dev_priv->last_pause_ptr = vb-1;
+	dev_priv->last_pause_ptr = vb - 1;
 
 	VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 	VIA_WRITE(VIA_REG_TRANSPACE, command);
@@ -445,7 +434,7 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
 	uint32_t pause_addr, pause_addr_lo, pause_addr_hi;
 	uint32_t start_addr;
 	uint32_t end_addr, end_addr_lo;
-	uint32_t * vb;
+	uint32_t *vb;
 	uint32_t qw_pad_count;
 	uint32_t command;
 	uint32_t jump_addr, jump_addr_lo, jump_addr_hi;
@@ -459,38 +448,37 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
 	via_cmdbuf_wait(dev_priv, 48);
 	via_dummy_bitblt(dev_priv);
 
-	via_cmdbuf_wait(dev_priv, 2*CMDBUF_ALIGNMENT_SIZE);
+	via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
 
 	/* At end of buffer, rewind with a JUMP command. */
 	vb = via_get_dma(dev_priv);
 
-	*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET>>2)<<12) |
-			(VIA_REG_TRANSPACE>>2);
-	*vb++ = (HC_ParaType_PreCR<<16);
+	*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
+	    (VIA_REG_TRANSPACE >> 2);
+	*vb++ = (HC_ParaType_PreCR << 16);
 	dev_priv->dma_low += 8;
 
-	qw_pad_count = (CMDBUF_ALIGNMENT_SIZE>>3) -
-			((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
+	qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
+	    ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
 
 	agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 	start_addr = agp_base;
-	end_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count<<3);
+	end_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
 
 	jump_addr = end_addr;
-	jump_addr_lo = ((HC_SubA_HAGPBpL<<24) | HC_HAGPBpID_JUMP |
+	jump_addr_lo = ((HC_SubA_HAGPBpL << 24) | HC_HAGPBpID_JUMP |
 			(jump_addr & 0xffffff));
-	jump_addr_hi = ((HC_SubA_HAGPBpH<<24) | (jump_addr >> 24));
+	jump_addr_hi = ((HC_SubA_HAGPBpH << 24) | (jump_addr >> 24));
 
 	end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
 	command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
-			((end_addr & 0xff000000) >> 16));
+		   ((end_addr & 0xff000000) >> 16));
 
 	*vb++ = command;
 	*vb++ = end_addr_lo;
 	dev_priv->dma_low += 8;
 
-	vb = via_align_buffer(dev_priv, vb, qw_pad_count-1);
-
+	vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
 
 	/* Now at beginning of buffer, make sure engine will pause here. */
 	dev_priv->dma_low = 0;
@@ -503,19 +491,19 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
 
 	end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
 	command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
-			((end_addr & 0xff000000) >> 16));
+		   ((end_addr & 0xff000000) >> 16));
 
-	qw_pad_count = (CMDBUF_ALIGNMENT_SIZE>>3) -
-			((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
+	qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
+	    ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
 
-	pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count<<3);
-	pause_addr_lo = ((HC_SubA_HAGPBpL<<24) | HC_HAGPBpID_PAUSE |
-			(pause_addr & 0xffffff));
-	pause_addr_hi = ((HC_SubA_HAGPBpH<<24) | (pause_addr >> 24));
+	pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
+	pause_addr_lo = ((HC_SubA_HAGPBpL << 24) | HC_HAGPBpID_PAUSE |
+			 (pause_addr & 0xffffff));
+	pause_addr_hi = ((HC_SubA_HAGPBpH << 24) | (pause_addr >> 24));
 
-	*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET>>2)<<12) |
-			(VIA_REG_TRANSPACE>>2);
-	*vb++ = (HC_ParaType_PreCR<<16);
+	*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
+	    (VIA_REG_TRANSPACE >> 2);
+	*vb++ = (HC_ParaType_PreCR << 16);
 	dev_priv->dma_low += 8;
 
 	*vb++ = pause_addr_hi;
@@ -533,7 +521,7 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
 	dev_priv->dma_low += 8;
 
 	*dev_priv->last_pause_ptr = jump_addr_lo;
-	dev_priv->last_pause_ptr = vb-1;
+	dev_priv->last_pause_ptr = vb - 1;
 
 	if (VIA_READ(0x41c) & 0x80000000) {
 		VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
@@ -552,33 +540,33 @@ static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
 {
 	uint32_t agp_base;
 	uint32_t pause_addr, pause_addr_lo, pause_addr_hi;
-	uint32_t * vb;
+	uint32_t *vb;
 	uint32_t qw_pad_count;
 
 	via_cmdbuf_wait(dev_priv, 0x200);
 
 	vb = via_get_dma(dev_priv);
-	*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET>>2)<<12) |
-			(VIA_REG_TRANSPACE>>2);
-	*vb++ = (HC_ParaType_PreCR<<16);
+	*vb++ = HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
+	    (VIA_REG_TRANSPACE >> 2);
+	*vb++ = (HC_ParaType_PreCR << 16);
 	dev_priv->dma_low += 8;
 
 	agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
-	qw_pad_count = (CMDBUF_ALIGNMENT_SIZE>>3) -
-			((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
+	qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
+	    ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
 
-	pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count<<3);
-	pause_addr_lo = ((HC_SubA_HAGPBpL<<24) | cmd_type |
-			(pause_addr & 0xffffff));
-	pause_addr_hi = ((HC_SubA_HAGPBpH<<24) | (pause_addr >> 24));
+	pause_addr = agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
+	pause_addr_lo = ((HC_SubA_HAGPBpL << 24) | cmd_type |
+			 (pause_addr & 0xffffff));
+	pause_addr_hi = ((HC_SubA_HAGPBpH << 24) | (pause_addr >> 24));
 
-	vb = via_align_buffer(dev_priv, vb, qw_pad_count-1);
+	vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
 
 	*vb++ = pause_addr_hi;
 	*vb++ = pause_addr_lo;
 	dev_priv->dma_low += 8;
 	*dev_priv->last_pause_ptr = pause_addr_lo;
-	dev_priv->last_pause_ptr = vb-1;
+	dev_priv->last_pause_ptr = vb - 1;
 
 	if (VIA_READ(0x41c) & 0x80000000) {
 		VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
@@ -597,5 +585,3 @@ static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
 	via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
 	via_wait_idle(dev_priv);
 }
-
-/************************************************************************/
diff --git a/shared-core/via_drm.h b/shared-core/via_drm.h
index ba94a4fe..5b121491 100644
--- a/shared-core/via_drm.h
+++ b/shared-core/via_drm.h
@@ -52,8 +52,8 @@
 #define VIA_LOG_MIN_TEX_REGION_SIZE 16
 #endif
 
-#define VIA_UPLOAD_TEX0IMAGE  0x1 /* handled clientside */
-#define VIA_UPLOAD_TEX1IMAGE  0x2 /* handled clientside */
+#define VIA_UPLOAD_TEX0IMAGE  0x1	/* handled clientside */
+#define VIA_UPLOAD_TEX1IMAGE  0x2	/* handled clientside */
 #define VIA_UPLOAD_CTX        0x4
 #define VIA_UPLOAD_BUFFERS    0x8
 #define VIA_UPLOAD_TEX0       0x10
@@ -85,12 +85,11 @@
 #define DRM_IOCTL_VIA_FLUSH	DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
 #define DRM_IOCTL_VIA_PCICMD	DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
 
-
 /* Indices into buf.Setup where various bits of state are mirrored per
  * context and per buffer.  These can be fired at the card as a unit,
  * or in a piecewise fashion as required.
  */
- 
+
 #define VIA_TEX_SETUP_SIZE 8
 
 /* Flags for clear ioctl
@@ -102,121 +101,120 @@
 #define VIDEO 0
 #define AGP 1
 typedef struct {
-        unsigned int offset;
-        unsigned int size;
-} drm_via_agp_t;    
+	unsigned int offset;
+	unsigned int size;
+} drm_via_agp_t;
 
 typedef struct {
-        unsigned int offset;
-        unsigned int size;
-} drm_via_fb_t;    
+	unsigned int offset;
+	unsigned int size;
+} drm_via_fb_t;
 
 typedef struct {
-        unsigned int context;
-        unsigned int type;
-        unsigned int size;
-        unsigned long index;
-        unsigned long offset;
-} drm_via_mem_t;    
+	unsigned int context;
+	unsigned int type;
+	unsigned int size;
+	unsigned long index;
+	unsigned long offset;
+} drm_via_mem_t;
 
 typedef struct _drm_via_init {
-        enum {
-                VIA_INIT_MAP = 0x01,
-                VIA_CLEANUP_MAP = 0x02
-        } func;
-
-        unsigned long sarea_priv_offset;
-        unsigned long fb_offset;
-        unsigned long mmio_offset;
-        unsigned long agpAddr;
+	enum {
+		VIA_INIT_MAP = 0x01,
+		VIA_CLEANUP_MAP = 0x02
+	} func;
+
+	unsigned long sarea_priv_offset;
+	unsigned long fb_offset;
+	unsigned long mmio_offset;
+	unsigned long agpAddr;
 } drm_via_init_t;
 
 typedef struct _drm_via_futex {
-        enum {
-                VIA_FUTEX_WAIT = 0x00,
-                VIA_FUTEX_WAKE = 0X01
-        }fut;
-        unsigned int op;
-        unsigned int ms;
-        unsigned int lock;
-        unsigned int val;
+	enum {
+		VIA_FUTEX_WAIT = 0x00,
+		VIA_FUTEX_WAKE = 0X01
+	} fut;
+	unsigned int op;
+	unsigned int ms;
+	unsigned int lock;
+	unsigned int val;
 } drm_via_futex_t;
 
 typedef struct _drm_via_dma_init {
-        enum {
-                VIA_INIT_DMA = 0x01,
-                VIA_CLEANUP_DMA = 0x02
-        } func;
-
-        unsigned long offset;
-        unsigned long size;
-        unsigned long reg_pause_addr;
+	enum {
+		VIA_INIT_DMA = 0x01,
+		VIA_CLEANUP_DMA = 0x02
+	} func;
+
+	unsigned long offset;
+	unsigned long size;
+	unsigned long reg_pause_addr;
 } drm_via_dma_init_t;
 
 typedef struct _drm_via_cmdbuffer {
-        char *buf;
-        unsigned long size;
+	char *buf;
+	unsigned long size;
 } drm_via_cmdbuffer_t;
 
 /* Warning: If you change the SAREA structure you must change the Xserver
  * structure as well */
 
 typedef struct _drm_via_tex_region {
-        unsigned char next, prev;	/* indices to form a circular LRU  */
-        unsigned char inUse;	/* owned by a client, or free? */
-        int age;			/* tracked by clients to update local LRU's */
+	unsigned char next, prev;	/* indices to form a circular LRU  */
+	unsigned char inUse;	/* owned by a client, or free? */
+	int age;		/* tracked by clients to update local LRU's */
 } drm_via_tex_region_t;
 
 typedef struct _drm_via_sarea {
-        unsigned int dirty;
-        unsigned int nbox;
-        drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS];   
-        drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; 
-        int texAge;			/* last time texture was uploaded */
-        int ctxOwner;		/* last context to upload state */
-        int vertexPrim;
-
-        /*
-         * Below is for XvMC.
-         * We want the lock integers alone on, and aligned to, a cache line.
-         * Therefore this somewhat strange construct.
-         */
-
-        char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
-
-        unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];      
-        unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; 
-        unsigned int XvMCCtxNoGrabbed;     /* Last context to hold decoder */
+	unsigned int dirty;
+	unsigned int nbox;
+	drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS];
+	drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
+	int texAge;		/* last time texture was uploaded */
+	int ctxOwner;		/* last context to upload state */
+	int vertexPrim;
+
+	/*
+	 * Below is for XvMC.
+	 * We want the lock integers alone on, and aligned to, a cache line.
+	 * Therefore this somewhat strange construct.
+	 */
+
+	char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
+
+	unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
+	unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
+	unsigned int XvMCCtxNoGrabbed;	/* Last context to hold decoder */
 
 } drm_via_sarea_t;
 
-
 typedef struct _drm_via_flush_agp {
-        unsigned int offset;
-        unsigned int size;
-        unsigned int index;		
-        int discard;	/* client is finished with the buffer? */
+	unsigned int offset;
+	unsigned int size;
+	unsigned int index;
+	int discard;		/* client is finished with the buffer? */
 } drm_via_flush_agp_t;
 
 typedef struct _drm_via_flush_sys {
-        unsigned int offset;
-        unsigned int size;
-        unsigned long index;		
-        int discard;	/* client is finished with the buffer? */
+	unsigned int offset;
+	unsigned int size;
+	unsigned long index;
+	int discard;		/* client is finished with the buffer? */
 } drm_via_flush_sys_t;
 
 #ifdef __KERNEL__
 
-int via_fb_init( DRM_IOCTL_ARGS );		
-int via_mem_alloc( DRM_IOCTL_ARGS );				
-int via_mem_free( DRM_IOCTL_ARGS );		
-int via_agp_init( DRM_IOCTL_ARGS );				
-int via_map_init( DRM_IOCTL_ARGS );				
-int via_decoder_futex( DRM_IOCTL_ARGS ); 
-int via_dma_init( DRM_IOCTL_ARGS );
-int via_cmdbuffer( DRM_IOCTL_ARGS );
-int via_flush_ioctl( DRM_IOCTL_ARGS );
-int via_pci_cmdbuffer( DRM_IOCTL_ARGS );
+int via_fb_init(DRM_IOCTL_ARGS);
+int via_mem_alloc(DRM_IOCTL_ARGS);
+int via_mem_free(DRM_IOCTL_ARGS);
+int via_agp_init(DRM_IOCTL_ARGS);
+int via_map_init(DRM_IOCTL_ARGS);
+int via_decoder_futex(DRM_IOCTL_ARGS);
+int via_dma_init(DRM_IOCTL_ARGS);
+int via_cmdbuffer(DRM_IOCTL_ARGS);
+int via_flush_ioctl(DRM_IOCTL_ARGS);
+int via_pci_cmdbuffer(DRM_IOCTL_ARGS);
 
 #endif
-#endif /* _VIA_DRM_H_ */
+#endif				/* _VIA_DRM_H_ */
diff --git a/shared-core/via_drv.c b/shared-core/via_drv.c
index df74efa8..291cc76e 100644
--- a/shared-core/via_drv.c
+++ b/shared-core/via_drv.c
@@ -39,30 +39,28 @@
 
 #include "drm_pciids.h"
 
-static int postinit( struct drm_device *dev, unsigned long flags )
+static int postinit(struct drm_device *dev, unsigned long flags)
 {
-	DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n",
-		DRIVER_NAME,
-		DRIVER_MAJOR,
-		DRIVER_MINOR,
-		DRIVER_PATCHLEVEL,
-		DRIVER_DATE,
-		dev->minor,
-		pci_pretty_name(dev->pdev)
-		);
+	DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
+		 DRIVER_NAME,
+		 DRIVER_MAJOR,
+		 DRIVER_MINOR,
+		 DRIVER_PATCHLEVEL,
+		 DRIVER_DATE, dev->minor, pci_pretty_name(dev->pdev)
+	    );
 	return 0;
 }
 
-static int version( drm_version_t *version )
+static int version(drm_version_t * version)
 {
 	int len;
 
 	version->version_major = DRIVER_MAJOR;
 	version->version_minor = DRIVER_MINOR;
 	version->version_patchlevel = DRIVER_PATCHLEVEL;
-	DRM_COPY( version->name, DRIVER_NAME );
-	DRM_COPY( version->date, DRIVER_DATE );
-	DRM_COPY( version->desc, DRIVER_DESC );
+	DRM_COPY(version->name, DRIVER_NAME);
+	DRM_COPY(version->date, DRIVER_DATE);
+	DRM_COPY(version->desc, DRIVER_DESC);
 	return 0;
 }
 
@@ -71,20 +69,22 @@ static struct pci_device_id pciidlist[] = {
 };
 
 static drm_ioctl_desc_t ioctls[] = {
-	[DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)]  = { via_mem_alloc,     1, 0},
-	[DRM_IOCTL_NR(DRM_VIA_FREEMEM)]   = { via_mem_free,      1, 0},
-	[DRM_IOCTL_NR(DRM_VIA_AGP_INIT)]  = { via_agp_init,      1, 0},
-	[DRM_IOCTL_NR(DRM_VIA_FB_INIT)]   = { via_fb_init,       1, 0},
-	[DRM_IOCTL_NR(DRM_VIA_MAP_INIT)]  = { via_map_init,      1, 0},
-	[DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = { via_decoder_futex, 1, 0},
-	[DRM_IOCTL_NR(DRM_VIA_DMA_INIT)]  = { via_dma_init,      1, 0},
-	[DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = { via_cmdbuffer,     1, 0},
-	[DRM_IOCTL_NR(DRM_VIA_FLUSH)]     = { via_flush_ioctl,   1, 0},
-	[DRM_IOCTL_NR(DRM_VIA_PCICMD)]    = { via_pci_cmdbuffer, 1, 0}
+	[DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, 1, 0},
+	[DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, 1, 0},
+	[DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, 1, 0},
+	[DRM_IOCTL_NR(DRM_VIA_FB_INIT)] = {via_fb_init, 1, 0},
+	[DRM_IOCTL_NR(DRM_VIA_MAP_INIT)] = {via_map_init, 1, 0},
+	[DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = {via_decoder_futex, 1, 0},
+	[DRM_IOCTL_NR(DRM_VIA_DMA_INIT)] = {via_dma_init, 1, 0},
+	[DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = {via_cmdbuffer, 1, 0},
+	[DRM_IOCTL_NR(DRM_VIA_FLUSH)] = {via_flush_ioctl, 1, 0},
+	[DRM_IOCTL_NR(DRM_VIA_PCICMD)] = {via_pci_cmdbuffer, 1, 0}
 };
 
 static struct drm_driver_fn driver_fn = {
-	.driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL,
+	.driver_features =
+	    DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_IRQ |
+	    DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL,
 	.context_ctor = via_init_context,
 	.context_dtor = via_final_context,
 	.vblank_wait = via_driver_vblank_wait,
@@ -100,13 +100,13 @@ static struct drm_driver_fn driver_fn = {
 	.ioctls = ioctls,
 	.num_ioctls = DRM_ARRAY_SIZE(ioctls),
 	.fops = {
-		.owner   = THIS_MODULE,
-		.open	 = drm_open,
-		.release = drm_release,
-		.ioctl	 = drm_ioctl,
-		.mmap	 = drm_mmap,
-		.fasync  = drm_fasync,
-	},
+		 .owner = THIS_MODULE,
+		 .open = drm_open,
+		 .release = drm_release,
+		 .ioctl = drm_ioctl,
+		 .mmap = drm_mmap,
+		 .fasync = drm_fasync,
+		 },
 };
 
 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
@@ -115,10 +115,10 @@ static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 }
 
 static struct pci_driver driver = {
-	.name          = DRIVER_NAME,
-	.id_table      = pciidlist,
-	.probe         = probe,
-	.remove        = __devexit_p(drm_cleanup_pci),
+	.name = DRIVER_NAME,
+	.id_table = pciidlist,
+	.probe = probe,
+	.remove = __devexit_p(drm_cleanup_pci),
 };
 
 static int __init via_init(void)
@@ -134,6 +134,6 @@ static void __exit via_exit(void)
 module_init(via_init);
 module_exit(via_exit);
 
-MODULE_AUTHOR( DRIVER_AUTHOR );
-MODULE_DESCRIPTION( DRIVER_DESC );
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE("GPL and additional rights");
diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h
index 39ccf0bd..07db9727 100644
--- a/shared-core/via_drv.h
+++ b/shared-core/via_drv.h
@@ -26,30 +26,28 @@
 
 #include "via_drm.h"
 
-
 typedef struct drm_via_ring_buffer {
-        drm_map_t map;
-        char * virtual_start;
+	drm_map_t map;
+	char *virtual_start;
 } drm_via_ring_buffer_t;
 
 typedef struct drm_via_private {
-        drm_via_sarea_t *sarea_priv;
-        drm_map_t *sarea;
-        drm_map_t *fb;
-        drm_map_t *mmio;
-        unsigned long agpAddr;
-        wait_queue_head_t decoder_queue[VIA_NR_XVMC_LOCKS];
-        char * dma_ptr;
-        unsigned int dma_low;
-        unsigned int dma_high;
-        unsigned int dma_offset;
-        uint32_t * last_pause_ptr;
-        volatile uint32_t * hw_addr_ptr;
-        drm_via_ring_buffer_t ring;
+	drm_via_sarea_t *sarea_priv;
+	drm_map_t *sarea;
+	drm_map_t *fb;
+	drm_map_t *mmio;
+	unsigned long agpAddr;
+	wait_queue_head_t decoder_queue[VIA_NR_XVMC_LOCKS];
+	char *dma_ptr;
+	unsigned int dma_low;
+	unsigned int dma_high;
+	unsigned int dma_offset;
+	uint32_t *last_pause_ptr;
+	volatile uint32_t *hw_addr_ptr;
+	drm_via_ring_buffer_t ring;
 	char pci_buf[VIA_PREALLOCATED_PCI_SIZE];
 } drm_via_private_t;
 
- 
 /* VIA MMIO register access */
 #define VIA_BASE ((dev_priv->mmio))
 
@@ -58,22 +56,22 @@ typedef struct drm_via_private {
 #define VIA_READ8(reg)		DRM_READ8(VIA_BASE, reg)
 #define VIA_WRITE8(reg,val)	DRM_WRITE8(VIA_BASE, reg, val)
 
-extern int via_init_context(drm_device_t *dev, int context);
-extern int via_final_context(drm_device_t *dev, int context);
+extern int via_init_context(drm_device_t * dev, int context);
+extern int via_final_context(drm_device_t * dev, int context);
 
-extern int via_do_init_map(drm_device_t *dev, drm_via_init_t *init);
-extern int via_do_cleanup_map(drm_device_t *dev);
+extern int via_do_init_map(drm_device_t * dev, drm_via_init_t * init);
+extern int via_do_cleanup_map(drm_device_t * dev);
 extern int via_map_init(struct inode *inode, struct file *filp,
 			unsigned int cmd, unsigned long arg);
-extern int via_driver_vblank_wait(drm_device_t* dev, unsigned int* sequence);
+extern int via_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence);
 
-extern irqreturn_t via_driver_irq_handler( DRM_IRQ_ARGS );
-extern void via_driver_irq_preinstall( drm_device_t *dev );
-extern void via_driver_irq_postinstall( drm_device_t *dev );
-extern void via_driver_irq_uninstall( drm_device_t *dev );
+extern irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS);
+extern void via_driver_irq_preinstall(drm_device_t * dev);
+extern void via_driver_irq_postinstall(drm_device_t * dev);
+extern void via_driver_irq_uninstall(drm_device_t * dev);
 
-extern int via_dma_cleanup(drm_device_t *dev);
+extern int via_dma_cleanup(drm_device_t * dev);
 
-extern int via_dma_cleanup(drm_device_t *dev);
+extern int via_dma_cleanup(drm_device_t * dev);
 
 #endif
diff --git a/shared-core/via_ds.c b/shared-core/via_ds.c
index 71af0c9b..94478b6c 100644
--- a/shared-core/via_ds.c
+++ b/shared-core/via_ds.c
@@ -28,101 +28,100 @@
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/poll.h>
-#include <asm/io.h>
 #include <linux/pci.h>
+#include <asm/io.h>
 
 #include "via_ds.h"
 extern unsigned int VIA_DEBUG;
 
 set_t *via_setInit(void)
 {
-        int i;
-        set_t *set;
-        set = (set_t *)drm_alloc(sizeof(set_t), DRM_MEM_DRIVER);
-        for (i = 0; i < SET_SIZE; i++) {
-                set->list[i].free_next = i+1;    
-                set->list[i].alloc_next = -1;
-        }    
-        set->list[SET_SIZE-1].free_next = -1;
-        set->free = 0;
-        set->alloc = -1;
-        set->trace = -1;
-        return set;
+	int i;
+	set_t *set;
+	set = (set_t *) drm_alloc(sizeof(set_t), DRM_MEM_DRIVER);
+	for (i = 0; i < SET_SIZE; i++) {
+		set->list[i].free_next = i + 1;
+		set->list[i].alloc_next = -1;
+	}
+	set->list[SET_SIZE - 1].free_next = -1;
+	set->free = 0;
+	set->alloc = -1;
+	set->trace = -1;
+	return set;
 }
 
-int via_setAdd(set_t *set, ITEM_TYPE item)
+int via_setAdd(set_t * set, ITEM_TYPE item)
 {
-        int free = set->free;
-        if (free != -1) {
-                set->list[free].val = item;
-                set->free = set->list[free].free_next;
-        }
-        else {
-                return 0;
-        }
-        set->list[free].alloc_next = set->alloc;
-        set->alloc = free;  
-        set->list[free].free_next = -1;  
-        return 1;
+	int free = set->free;
+	if (free != -1) {
+		set->list[free].val = item;
+		set->free = set->list[free].free_next;
+	} else {
+		return 0;
+	}
+	set->list[free].alloc_next = set->alloc;
+	set->alloc = free;
+	set->list[free].free_next = -1;
+	return 1;
 }
 
-int via_setDel(set_t *set, ITEM_TYPE item)
+int via_setDel(set_t * set, ITEM_TYPE item)
 {
-        int alloc = set->alloc;
-        int prev = -1;  
-  
-        while (alloc != -1) {
-                if (set->list[alloc].val == item) {
-                        if (prev != -1)      
-                                set->list[prev].alloc_next = set->list[alloc].alloc_next; 
-                        else
-                                set->alloc = set->list[alloc].alloc_next;
-                        break;
-                }
-                prev = alloc;
-                alloc = set->list[alloc].alloc_next;      
-        }
-
-        if (alloc == -1)
-                return 0;
-  
-        set->list[alloc].free_next = set->free;
-        set->free = alloc;
-        set->list[alloc].alloc_next = -1;   
-
-        return 1;
+	int alloc = set->alloc;
+	int prev = -1;
+
+	while (alloc != -1) {
+		if (set->list[alloc].val == item) {
+			if (prev != -1)
+				set->list[prev].alloc_next =
+				    set->list[alloc].alloc_next;
+			else
+				set->alloc = set->list[alloc].alloc_next;
+			break;
+		}
+		prev = alloc;
+		alloc = set->list[alloc].alloc_next;
+	}
+
+	if (alloc == -1)
+		return 0;
+
+	set->list[alloc].free_next = set->free;
+	set->free = alloc;
+	set->list[alloc].alloc_next = -1;
+
+	return 1;
 }
 
 /* setFirst -> setAdd -> setNext is wrong */
 
-int via_setFirst(set_t *set, ITEM_TYPE *item)
+int via_setFirst(set_t * set, ITEM_TYPE * item)
 {
-        if (set->alloc == -1)
-                return 0;
+	if (set->alloc == -1)
+		return 0;
 
-        *item = set->list[set->alloc].val;
-        set->trace = set->list[set->alloc].alloc_next; 
+	*item = set->list[set->alloc].val;
+	set->trace = set->list[set->alloc].alloc_next;
 
-	
-        return 1;
+	return 1;
 }
 
-int via_setNext(set_t *set, ITEM_TYPE *item)
+int via_setNext(set_t * set, ITEM_TYPE * item)
 {
-        if (set->trace == -1)
-                return 0;
-  
-        *item = set->list[set->trace].val;
-        set->trace = set->list[set->trace].alloc_next;      
+	if (set->trace == -1)
+		return 0;
+
+	*item = set->list[set->trace].val;
+	set->trace = set->list[set->trace].alloc_next;
 
-        return 1;
+	return 1;
 }
 
-int via_setDestroy(set_t *set)
+int via_setDestroy(set_t * set)
 {
-        drm_free(set, sizeof(set_t), DRM_MEM_DRIVER);
+	drm_free(set, sizeof(set_t), DRM_MEM_DRIVER);
 
-        return 1;
+	return 1;
 }
 
 #define ISFREE(bptr) ((bptr)->free)
@@ -130,261 +129,260 @@ int via_setDestroy(set_t *set)
 #define PRINTF(fmt, arg...) do{}while(0)
 #define fprintf(fmt, arg...) do{}while(0)
 
-void via_mmDumpMemInfo( memHeap_t *heap )
+void via_mmDumpMemInfo(memHeap_t * heap)
 {
-        TMemBlock *p;
-
-        PRINTF ("Memory heap %p:\n", heap);
-    
-        if (heap == 0)
-                PRINTF ("  heap == 0\n");
-        else {
-                p = (TMemBlock *)heap;
-	
-                while (p) {
-                        PRINTF ("  Offset:%08x, Size:%08x, %c%c\n",p->ofs,p->size,
-                                p->free ? '.':'U',
-                                p->reserved ? 'R':'.');
-                        p = p->next;
-                }
-        }
-    
-        PRINTF ("End of memory blocks\n");
+	TMemBlock *p;
+
+	PRINTF("Memory heap %p:\n", heap);
+
+	if (heap == 0)
+		PRINTF("  heap == 0\n");
+	else {
+		p = (TMemBlock *) heap;
+
+		while (p) {
+			PRINTF("  Offset:%08x, Size:%08x, %c%c\n", p->ofs,
+			       p->size, p->free ? '.' : 'U',
+			       p->reserved ? 'R' : '.');
+			p = p->next;
+		}
+	}
+
+	PRINTF("End of memory blocks\n");
 }
 
-memHeap_t *via_mmInit(int ofs,
-		      int size)
+memHeap_t *via_mmInit(int ofs, int size)
 {
-        PMemBlock blocks;
-  
-        if (size <= 0)
-                return 0;
-
-      
-        blocks = (TMemBlock *)drm_calloc(1,sizeof(TMemBlock),DRM_MEM_DRIVER);
-   
-        if (blocks) {
-                blocks->ofs = ofs;
-                blocks->size = size;
-                blocks->free = 1;
-                return (memHeap_t *)blocks;
-        } else
-                return 0;
+	PMemBlock blocks;
+
+	if (size <= 0)
+		return 0;
+
+	blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER);
+
+	if (blocks) {
+		blocks->ofs = ofs;
+		blocks->size = size;
+		blocks->free = 1;
+		return (memHeap_t *) blocks;
+	} else
+		return 0;
 }
 
-memHeap_t *via_mmAddRange(memHeap_t *heap,
-			  int ofs,
-			  int size)
+memHeap_t *via_mmAddRange(memHeap_t * heap, int ofs, int size)
 {
-        PMemBlock blocks;
-        blocks = (TMemBlock *)drm_calloc(2,sizeof(TMemBlock),DRM_MEM_DRIVER);
-    
-        if (blocks) {
-                blocks[0].size = size;
-                blocks[0].free = 1;
-                blocks[0].ofs = ofs;
-                blocks[0].next = &blocks[1];
-
-                /* Discontinuity - stops JoinBlock from trying to join non-adjacent
-                 * ranges.
-                 */
-                blocks[1].size = 0;
-                blocks[1].free = 0;
-                blocks[1].ofs = ofs+size;
-                blocks[1].next = (PMemBlock) heap;      
-                return (memHeap_t *)blocks;
-        } 
-        else
-                return heap;
+	PMemBlock blocks;
+	blocks = (TMemBlock *) drm_calloc(2, sizeof(TMemBlock), DRM_MEM_DRIVER);
+
+	if (blocks) {
+		blocks[0].size = size;
+		blocks[0].free = 1;
+		blocks[0].ofs = ofs;
+		blocks[0].next = &blocks[1];
+
+		/* Discontinuity - stops JoinBlock from trying to join non-adjacent
+		 * ranges.
+		 */
+		blocks[1].size = 0;
+		blocks[1].free = 0;
+		blocks[1].ofs = ofs + size;
+		blocks[1].next = (PMemBlock) heap;
+		return (memHeap_t *) blocks;
+	} else
+		return heap;
 }
 
-static TMemBlock* SliceBlock(TMemBlock *p, 
-			     int startofs, int size, 
+static TMemBlock *SliceBlock(TMemBlock * p,
+			     int startofs, int size,
 			     int reserved, int alignment)
 {
-        TMemBlock *newblock;
-
-        /* break left */
-        if (startofs > p->ofs) {
-                newblock = (TMemBlock*)drm_calloc(1,sizeof(TMemBlock),DRM_MEM_DRIVER);
-                newblock->ofs = startofs;
-                newblock->size = p->size - (startofs - p->ofs);
-                newblock->free = 1;
-                newblock->next = p->next;
-                p->size -= newblock->size;
-                p->next = newblock;
-                p = newblock;
-        }
-
-        /* break right */
-        if (size < p->size) {
-                newblock = (TMemBlock*)drm_calloc(1,sizeof(TMemBlock),DRM_MEM_DRIVER);
-                newblock->ofs = startofs + size;
-                newblock->size = p->size - size;
-                newblock->free = 1;
-                newblock->next = p->next;
-                p->size = size;
-                p->next = newblock;
-        }
-
-        /* p = middle block */
-        p->align = alignment;
-        p->free = 0;
-        p->reserved = reserved;
-        return p;
+	TMemBlock *newblock;
+
+	/* break left */
+	if (startofs > p->ofs) {
+		newblock =
+		    (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
+					     DRM_MEM_DRIVER);
+		newblock->ofs = startofs;
+		newblock->size = p->size - (startofs - p->ofs);
+		newblock->free = 1;
+		newblock->next = p->next;
+		p->size -= newblock->size;
+		p->next = newblock;
+		p = newblock;
+	}
+
+	/* break right */
+	if (size < p->size) {
+		newblock =
+		    (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
+					     DRM_MEM_DRIVER);
+		newblock->ofs = startofs + size;
+		newblock->size = p->size - size;
+		newblock->free = 1;
+		newblock->next = p->next;
+		p->size = size;
+		p->next = newblock;
+	}
+
+	/* p = middle block */
+	p->align = alignment;
+	p->free = 0;
+	p->reserved = reserved;
+	return p;
 }
 
-PMemBlock via_mmAllocMem(memHeap_t *heap, int size, int align2, int startSearch)
+PMemBlock via_mmAllocMem(memHeap_t * heap, int size, int align2,
+			 int startSearch)
 {
-        int mask,startofs,endofs;
-        TMemBlock *p;
-
-        if (!heap || align2 < 0 || size <= 0)
-                return NULL;
-    
-        mask = (1 << align2)-1;
-        startofs = 0;
-        p = (TMemBlock *)heap;
-    
-        while (p) {
-                if (ISFREE(p)) {
-                        startofs = (p->ofs + mask) & ~mask;
-    	
-                        if ( startofs < startSearch )
-                                startofs = startSearch;
-        
-                        endofs = startofs+size;
-        
-                        if (endofs <= (p->ofs+p->size))
-                                break;
-                }
-	
-                p = p->next;
-        }
-    
-        if (!p)
-                return NULL;
-    
-        p = SliceBlock(p,startofs,size,0,mask+1);
-        p->heap = heap;
-    
-        return p;
+	int mask, startofs, endofs;
+	TMemBlock *p;
+
+	if (!heap || align2 < 0 || size <= 0)
+		return NULL;
+
+	mask = (1 << align2) - 1;
+	startofs = 0;
+	p = (TMemBlock *) heap;
+
+	while (p) {
+		if (ISFREE(p)) {
+			startofs = (p->ofs + mask) & ~mask;
+
+			if (startofs < startSearch)
+				startofs = startSearch;
+
+			endofs = startofs + size;
+
+			if (endofs <= (p->ofs + p->size))
+				break;
+		}
+
+		p = p->next;
+	}
+
+	if (!p)
+		return NULL;
+
+	p = SliceBlock(p, startofs, size, 0, mask + 1);
+	p->heap = heap;
+
+	return p;
 }
 
-static __inline__ int Join2Blocks(TMemBlock *p)
+static __inline__ int Join2Blocks(TMemBlock * p)
 {
-        if (p->free && p->next && p->next->free) {
-                TMemBlock *q = p->next;
-                p->size += q->size;
-                p->next = q->next;
-                drm_free(q,sizeof(TMemBlock),DRM_MEM_DRIVER);
-	
-                return 1;
-        }
-    
-        return 0;
+	if (p->free && p->next && p->next->free) {
+		TMemBlock *q = p->next;
+		p->size += q->size;
+		p->next = q->next;
+		drm_free(q, sizeof(TMemBlock), DRM_MEM_DRIVER);
+
+		return 1;
+	}
+
+	return 0;
 }
 
 int via_mmFreeMem(PMemBlock b)
 {
-        TMemBlock *p,*prev;
-
-        if (!b)
-                return 0;
-    
-        if (!b->heap) {
-                fprintf(stderr, "no heap\n");
-        
-                return -1;
-        }
-    
-        p = b->heap;
-        prev = NULL;
-    
-        while (p && p != b) {
-                prev = p;
-                p = p->next;
-        }
-    
-        if (!p || p->free || p->reserved) {
-                if (!p)
-                        fprintf(stderr, "block not found in heap\n");
-                else if (p->free)
-                        fprintf(stderr, "block already free\n");
-                else
-                        fprintf(stderr, "block is reserved\n");
-	
-	
-                return -1;
-        }
-    
-        p->free = 1;
-        Join2Blocks(p);
-    
-        if (prev)
-                Join2Blocks(prev);
-  
-        return 0;
+	TMemBlock *p, *prev;
+
+	if (!b)
+		return 0;
+
+	if (!b->heap) {
+		fprintf(stderr, "no heap\n");
+
+		return -1;
+	}
+
+	p = b->heap;
+	prev = NULL;
+
+	while (p && p != b) {
+		prev = p;
+		p = p->next;
+	}
+
+	if (!p || p->free || p->reserved) {
+		if (!p)
+			fprintf(stderr, "block not found in heap\n");
+		else if (p->free)
+			fprintf(stderr, "block already free\n");
+		else
+			fprintf(stderr, "block is reserved\n");
+
+		return -1;
+	}
+
+	p->free = 1;
+	Join2Blocks(p);
+
+	if (prev)
+		Join2Blocks(prev);
+
+	return 0;
 }
 
-int via_mmReserveMem(memHeap_t *heap, int offset,int size)
+int via_mmReserveMem(memHeap_t * heap, int offset, int size)
 {
-        int endofs;
-        TMemBlock *p;
-
-        if (!heap || size <= 0)
-                return -1;
-        endofs = offset+size;
-        p = (TMemBlock *)heap;
-    
-        while (p && p->ofs <= offset) {
-                if (ISFREE(p) && endofs <= (p->ofs+p->size)) {
-                        SliceBlock(p,offset,size,1,1);
-                        return 0;
-                }
-                p = p->next;
-        }
-        return -1;
+	int endofs;
+	TMemBlock *p;
+
+	if (!heap || size <= 0)
+		return -1;
+	endofs = offset + size;
+	p = (TMemBlock *) heap;
+
+	while (p && p->ofs <= offset) {
+		if (ISFREE(p) && endofs <= (p->ofs + p->size)) {
+			SliceBlock(p, offset, size, 1, 1);
+			return 0;
+		}
+		p = p->next;
+	}
+	return -1;
 }
 
-int via_mmFreeReserved(memHeap_t *heap, int offset)
+int via_mmFreeReserved(memHeap_t * heap, int offset)
 {
-        TMemBlock *p,*prev;
-
-        if (!heap)
-                return -1;
-  
-        p = (TMemBlock *)heap;
-        prev = NULL;
-    
-        while (p && p->ofs != offset) {
-                prev = p;
-                p = p->next;
-        }
-    
-        if (!p || !p->reserved)
-                return -1;
-        p->free = 1;
-        p->reserved = 0;
-        Join2Blocks(p);
-    
-        if (prev)
-                Join2Blocks(prev);
-    
-        return 0;
+	TMemBlock *p, *prev;
+
+	if (!heap)
+		return -1;
+
+	p = (TMemBlock *) heap;
+	prev = NULL;
+
+	while (p && p->ofs != offset) {
+		prev = p;
+		p = p->next;
+	}
+
+	if (!p || !p->reserved)
+		return -1;
+	p->free = 1;
+	p->reserved = 0;
+	Join2Blocks(p);
+
+	if (prev)
+		Join2Blocks(prev);
+
+	return 0;
 }
 
-void via_mmDestroy(memHeap_t *heap)
+void via_mmDestroy(memHeap_t * heap)
 {
-        TMemBlock *p,*q;
-
-        if (!heap)
-                return;
-        p = (TMemBlock *)heap;
-    
-        while (p) {
-                q = p->next;
-                drm_free(p,sizeof(TMemBlock),DRM_MEM_DRIVER);
-                p = q;
-        }
+	TMemBlock *p, *q;
+
+	if (!heap)
+		return;
+	p = (TMemBlock *) heap;
+
+	while (p) {
+		q = p->next;
+		drm_free(p, sizeof(TMemBlock), DRM_MEM_DRIVER);
+		p = q;
+	}
 }
diff --git a/shared-core/via_ds.h b/shared-core/via_ds.h
index d9a60186..bd2f07ca 100644
--- a/shared-core/via_ds.h
+++ b/shared-core/via_ds.h
@@ -23,7 +23,7 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef _via_ds_h_ 
+#ifndef _via_ds_h_
 #define _via_ds_h_
 
 #include "drmP.h"
@@ -33,37 +33,36 @@
 typedef unsigned int ITEM_TYPE;
 
 typedef struct {
-        ITEM_TYPE val;
-        int alloc_next, free_next;
+	ITEM_TYPE val;
+	int alloc_next, free_next;
 } list_item_t;
 
 typedef struct {
-        int alloc;
-        int free;
-        int trace;
-        list_item_t list[SET_SIZE];
+	int alloc;
+	int free;
+	int trace;
+	list_item_t list[SET_SIZE];
 } set_t;
 
 set_t *via_setInit(void);
-int via_setAdd(set_t *set, ITEM_TYPE item);
-int via_setDel(set_t *set, ITEM_TYPE item);
-int via_setFirst(set_t *set, ITEM_TYPE *item);
-int via_setNext(set_t *set, ITEM_TYPE *item);
-int via_setDestroy(set_t *set);
+int via_setAdd(set_t * set, ITEM_TYPE item);
+int via_setDel(set_t * set, ITEM_TYPE item);
+int via_setFirst(set_t * set, ITEM_TYPE * item);
+int via_setNext(set_t * set, ITEM_TYPE * item);
+int via_setDestroy(set_t * set);
 
 #endif
 
-
 #ifndef MM_INC
 #define MM_INC
 
 struct mem_block_t {
-        struct mem_block_t *next;
-        struct mem_block_t *heap;
-        int ofs,size;
-        int align;
-        int free:1;
-        int reserved:1;
+	struct mem_block_t *next;
+	struct mem_block_t *heap;
+	int ofs, size;
+	int align;
+	int free:1;
+	int reserved:1;
 };
 typedef struct mem_block_t TMemBlock;
 typedef struct mem_block_t *PMemBlock;
@@ -72,36 +71,42 @@ typedef struct mem_block_t *PMemBlock;
 typedef struct mem_block_t memHeap_t;
 
 static __inline__ int mmBlockSize(PMemBlock b)
-{ return b->size; }
+{
+	return b->size;
+}
 
 static __inline__ int mmOffset(PMemBlock b)
-{ return b->ofs; }
+{
+	return b->ofs;
+}
 
 static __inline__ void mmMarkReserved(PMemBlock b)
-{ b->reserved = 1; }
+{
+	b->reserved = 1;
+}
 
-/* 
+/*
  * input: total size in bytes
  * return: a heap pointer if OK, NULL if error
  */
 memHeap_t *via_mmInit(int ofs, int size);
 
-
-PMemBlock  via_mmAllocMem(memHeap_t *heap, int size, int align2, int startSearch);
+PMemBlock via_mmAllocMem(memHeap_t * heap, int size, int align2,
+			 int startSearch);
 
 /*
  * Free block starts at offset
  * input: pointer to a block
  * return: 0 if OK, -1 if error
  */
-int  via_mmFreeMem(PMemBlock b);
+int via_mmFreeMem(PMemBlock b);
 
 /*
  * destroy MM
  */
-void via_mmDestroy(memHeap_t *mmInit);
+void via_mmDestroy(memHeap_t * mmInit);
 
 /* For debugging purpose. */
-void via_mmDumpMemInfo(memHeap_t *mmInit);
+void via_mmDumpMemInfo(memHeap_t * mmInit);
 
 #endif
diff --git a/shared-core/via_irq.c b/shared-core/via_irq.c
index b0a3349e..f2cd79df 100644
--- a/shared-core/via_irq.c
+++ b/shared-core/via_irq.c
@@ -10,21 +10,21 @@
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * BEAM LTD, TUNGSTEN GRAPHICS  AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 
+ * BEAM LTD, TUNGSTEN GRAPHICS  AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  * DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  *
- * Authors: 
+ * Authors:
  *    Terry Barnaby <terry1@beam.ltd.uk>
  *    Keith Whitwell <keith@tungstengraphics.com>
  *
@@ -39,126 +39,128 @@
 #include "via_drv.h"
 
 #define VIA_REG_INTERRUPT       0x200
- 
+
 /* VIA_REG_INTERRUPT */
 #define VIA_IRQ_GLOBAL          (1 << 31)
 #define VIA_IRQ_VBI_ENABLE      (1 << 19)
 #define VIA_IRQ_VBI_PENDING     (1 << 3)
 
-irqreturn_t via_driver_irq_handler( DRM_IRQ_ARGS )
+irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
 {
-        drm_device_t*	dev = (drm_device_t*)arg;
-        drm_via_private_t*	dev_priv = (drm_via_private_t*)dev->dev_private;
-        u32			status;
-        int			handled = 0;
-	
-        status = VIA_READ(VIA_REG_INTERRUPT);
-        DRM_DEBUG("viadrv_irq_handler Status: %x\n",status);
-        if(status & VIA_IRQ_VBI_PENDING){
-                atomic_inc(&dev->vbl_received);
-                DRM_WAKEUP(&dev->vbl_queue);
-                drm_vbl_send_signals(dev);
-                handled = 1;
-        }
-    
-        /* Acknowlege interrupts ?? */
-        VIA_WRITE(VIA_REG_INTERRUPT, status);
+	drm_device_t *dev = (drm_device_t *) arg;
+	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+	u32 status;
+	int handled = 0;
+
+	status = VIA_READ(VIA_REG_INTERRUPT);
+	DRM_DEBUG("viadrv_irq_handler Status: %x\n", status);
+	if (status & VIA_IRQ_VBI_PENDING) {
+		atomic_inc(&dev->vbl_received);
+		DRM_WAKEUP(&dev->vbl_queue);
+		drm_vbl_send_signals(dev);
+		handled = 1;
+	}
+
+	/* Acknowlege interrupts ?? */
+	VIA_WRITE(VIA_REG_INTERRUPT, status);
 
 	if (handled)
-        	return IRQ_HANDLED;
+		return IRQ_HANDLED;
 	else
 		return IRQ_NONE;
 }
 
-static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t* dev_priv)
+static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
 {
-        u32	status;
-	
-        if(dev_priv){
-                /* Acknowlege interrupts ?? */
-                status = VIA_READ(VIA_REG_INTERRUPT);
-                VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBI_PENDING);
-        }
+	u32 status;
+
+	if (dev_priv) {
+		/* Acknowlege interrupts ?? */
+		status = VIA_READ(VIA_REG_INTERRUPT);
+		VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBI_PENDING);
+	}
 }
 
-int via_driver_vblank_wait(drm_device_t* dev, unsigned int* sequence)
+int via_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
 {
-        drm_via_private_t*	dev_priv = (drm_via_private_t*)dev->dev_private;
-        unsigned int		cur_vblank;
-        int			ret = 0;
-
-        DRM_DEBUG("viadrv_vblank_wait\n");
-        if(!dev_priv){
-                DRM_ERROR("%s called with no initialization\n", __FUNCTION__ );
-                return -EINVAL;
-        }
-
-        viadrv_acknowledge_irqs(dev_priv);
-
-        /* Assume that the user has missed the current sequence number
-         * by about a day rather than she wants to wait for years
-         * using vertical blanks... 
-         */
-        DRM_WAIT_ON(ret, dev->vbl_queue, 3*DRM_HZ, 
-                    (((cur_vblank = atomic_read(&dev->vbl_received)) - 
-                      *sequence ) <= (1<<23)));
-
-        *sequence = cur_vblank;
-        return ret;
+	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+	unsigned int cur_vblank;
+	int ret = 0;
+
+	DRM_DEBUG("viadrv_vblank_wait\n");
+	if (!dev_priv) {
+		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	viadrv_acknowledge_irqs(dev_priv);
+
+	/* Assume that the user has missed the current sequence number
+	 * by about a day rather than she wants to wait for years
+	 * using vertical blanks...
+	 */
+	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
+		    (((cur_vblank = atomic_read(&dev->vbl_received)) -
+		      *sequence) <= (1 << 23)));
+
+	*sequence = cur_vblank;
+	return ret;
 }
 
 /*
  * drm_dma.h hooks
  */
-void via_driver_irq_preinstall(drm_device_t* dev){
-        drm_via_private_t*	dev_priv = (drm_via_private_t *)dev->dev_private;
-        u32			status;
-
-        DRM_DEBUG("driver_irq_preinstall: dev_priv: %p\n", dev_priv);
-        if(dev_priv){
-                DRM_DEBUG("mmio: %p\n", dev_priv->mmio);
-                status = VIA_READ(VIA_REG_INTERRUPT);
-                DRM_DEBUG("intreg: %x\n", status & VIA_IRQ_VBI_ENABLE);
-		
-                // Clear VSync interrupt regs
-                VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBI_ENABLE);
-
-                /* Clear bits if they're already high */
-                viadrv_acknowledge_irqs(dev_priv);
-        }
+void via_driver_irq_preinstall(drm_device_t * dev)
+{
+	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+	u32 status;
+
+	DRM_DEBUG("driver_irq_preinstall: dev_priv: %p\n", dev_priv);
+	if (dev_priv) {
+		DRM_DEBUG("mmio: %p\n", dev_priv->mmio);
+		status = VIA_READ(VIA_REG_INTERRUPT);
+		DRM_DEBUG("intreg: %x\n", status & VIA_IRQ_VBI_ENABLE);
+
+		// Clear VSync interrupt regs
+		VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBI_ENABLE);
+
+		/* Clear bits if they're already high */
+		viadrv_acknowledge_irqs(dev_priv);
+	}
 }
 
-void via_driver_irq_postinstall(drm_device_t* dev){
-        drm_via_private_t*	dev_priv = (drm_via_private_t *)dev->dev_private;
-        u32			status;
+void via_driver_irq_postinstall(drm_device_t * dev)
+{
+	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+	u32 status;
 
-        DRM_DEBUG("via_driver_irq_postinstall\n");
-        if(dev_priv){
-                status = VIA_READ(VIA_REG_INTERRUPT);
-                VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL 
-                          | VIA_IRQ_VBI_ENABLE);
-                /* Some magic, oh for some data sheets ! */		
+	DRM_DEBUG("via_driver_irq_postinstall\n");
+	if (dev_priv) {
+		status = VIA_READ(VIA_REG_INTERRUPT);
+		VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
+			  | VIA_IRQ_VBI_ENABLE);
+		/* Some magic, oh for some data sheets ! */
 
-                VIA_WRITE8(0x83d4, 0x11);
-                VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
+		VIA_WRITE8(0x83d4, 0x11);
+		VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
 
-        }
+	}
 }
 
-void via_driver_irq_uninstall(drm_device_t* dev){
-        drm_via_private_t*	dev_priv = (drm_via_private_t *)dev->dev_private;
-        u32			status;
+void via_driver_irq_uninstall(drm_device_t * dev)
+{
+	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+	u32 status;
 
-        DRM_DEBUG("driver_irq_uninstall)\n");
-        if(dev_priv){ 
+	DRM_DEBUG("driver_irq_uninstall)\n");
+	if (dev_priv) {
 
-                /* Some more magic, oh for some data sheets ! */		
+		/* Some more magic, oh for some data sheets ! */
 
-                VIA_WRITE8(0x83d4, 0x11);
-                VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
+		VIA_WRITE8(0x83d4, 0x11);
+		VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
 
-                status = VIA_READ(VIA_REG_INTERRUPT);
-                VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBI_ENABLE);
-        }
+		status = VIA_READ(VIA_REG_INTERRUPT);
+		VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBI_ENABLE);
+	}
 }
-
diff --git a/shared-core/via_map.c b/shared-core/via_map.c
index b7f0b43b..096e3e15 100644
--- a/shared-core/via_map.c
+++ b/shared-core/via_map.c
@@ -24,11 +24,11 @@
 #include "drmP.h"
 #include "via_drv.h"
 
-int via_do_init_map(drm_device_t *dev, drm_via_init_t *init)
+int via_do_init_map(drm_device_t * dev, drm_via_init_t * init)
 {
 	drm_via_private_t *dev_priv;
 	unsigned int i;
-	
+
 	DRM_DEBUG("%s\n", __FUNCTION__);
 
 	dev_priv = drm_alloc(sizeof(drm_via_private_t), DRM_MEM_DRIVER);
@@ -36,7 +36,7 @@ int via_do_init_map(drm_device_t *dev, drm_via_init_t *init)
 		return -ENOMEM;
 
 	memset(dev_priv, 0, sizeof(drm_via_private_t));
-	
+
 	DRM_GETSAREA();
 	if (!dev_priv->sarea) {
 		DRM_ERROR("could not find sarea!\n");
@@ -59,23 +59,22 @@ int via_do_init_map(drm_device_t *dev, drm_via_init_t *init)
 		via_do_cleanup_map(dev);
 		return -EINVAL;
 	}
-	
+
 	dev_priv->sarea_priv =
-		(drm_via_sarea_t *)((u8 *)dev_priv->sarea->handle +
-                                    init->sarea_priv_offset);
+	    (drm_via_sarea_t *) ((u8 *) dev_priv->sarea->handle +
+				 init->sarea_priv_offset);
 
 	dev_priv->agpAddr = init->agpAddr;
 
-	
-	for (i=0; i<VIA_NR_XVMC_LOCKS; ++i) 
-                DRM_INIT_WAITQUEUE( &(dev_priv->decoder_queue[i]) );
+	for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i)
+		DRM_INIT_WAITQUEUE(&(dev_priv->decoder_queue[i]));
 
 	dev->dev_private = (void *)dev_priv;
 
 	return 0;
 }
 
-int via_do_cleanup_map(drm_device_t *dev)
+int via_do_cleanup_map(drm_device_t * dev)
 {
 	if (dev->dev_private) {
 
@@ -83,61 +82,56 @@ int via_do_cleanup_map(drm_device_t *dev)
 
 		via_dma_cleanup(dev);
 
-		drm_free(dev_priv, sizeof(drm_via_private_t),
-                          DRM_MEM_DRIVER);
+		drm_free(dev_priv, sizeof(drm_via_private_t), DRM_MEM_DRIVER);
 		dev->dev_private = NULL;
 	}
 
 	return 0;
 }
 
-int via_map_init( DRM_IOCTL_ARGS )
+int via_map_init(DRM_IOCTL_ARGS)
 {
-        DRM_DEVICE;
+	DRM_DEVICE;
 	drm_via_init_t init;
 
 	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	DRM_COPY_FROM_USER_IOCTL(init, (drm_via_init_t *)data, sizeof(init));
+	DRM_COPY_FROM_USER_IOCTL(init, (drm_via_init_t *) data, sizeof(init));
 
 	switch (init.func) {
-        case VIA_INIT_MAP:
+	case VIA_INIT_MAP:
 		return via_do_init_map(dev, &init);
-        case VIA_CLEANUP_MAP:
+	case VIA_CLEANUP_MAP:
 		return via_do_cleanup_map(dev);
 	}
 
 	return -EINVAL;
 }
 
-int via_decoder_futex( DRM_IOCTL_ARGS ) 
+int via_decoder_futex(DRM_IOCTL_ARGS)
 {
-        DRM_DEVICE;
-        drm_via_futex_t fx;
-        volatile int *lock;
-        drm_via_private_t *dev_priv = (drm_via_private_t*) dev->dev_private;
-        drm_via_sarea_t *sAPriv = dev_priv->sarea_priv;
-        int ret = 0;
-
-        DRM_COPY_FROM_USER_IOCTL(fx, (drm_via_futex_t *) data, sizeof(fx));
-    
-        if (fx.lock > VIA_NR_XVMC_LOCKS)
-                return -EFAULT;
-
-        lock = XVMCLOCKPTR(sAPriv,fx.lock);
-
-        switch(fx.op) {
-        case VIA_FUTEX_WAIT:
-                DRM_WAIT_ON(ret, dev_priv->decoder_queue[fx.lock], 
-                            (fx.ms / 10)*(DRM_HZ/100), 
-                            *lock != fx.val);
-                return ret;
-        case VIA_FUTEX_WAKE:
-                DRM_WAKEUP( &(dev_priv->decoder_queue[fx.lock]) );
-                return 0;
-        }
-        return 0;
+	DRM_DEVICE;
+	drm_via_futex_t fx;
+	volatile int *lock;
+	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+	drm_via_sarea_t *sAPriv = dev_priv->sarea_priv;
+	int ret = 0;
+
+	DRM_COPY_FROM_USER_IOCTL(fx, (drm_via_futex_t *) data, sizeof(fx));
+
+	if (fx.lock > VIA_NR_XVMC_LOCKS)
+		return -EFAULT;
+
+	lock = XVMCLOCKPTR(sAPriv, fx.lock);
+
+	switch (fx.op) {
+	case VIA_FUTEX_WAIT:
+		DRM_WAIT_ON(ret, dev_priv->decoder_queue[fx.lock],
+			    (fx.ms / 10) * (DRM_HZ / 100), *lock != fx.val);
+		return ret;
+	case VIA_FUTEX_WAKE:
+		DRM_WAKEUP(&(dev_priv->decoder_queue[fx.lock]));
+		return 0;
+	}
+	return 0;
 }
-	    
-	
-    
diff --git a/shared-core/via_mm.c b/shared-core/via_mm.c
index 706f00d1..c08385ce 100644
--- a/shared-core/via_mm.c
+++ b/shared-core/via_mm.c
@@ -32,324 +32,317 @@
 unsigned int VIA_DEBUG = 1;
 
 typedef struct {
-        int used;
-        int context;
-        set_t *sets[2]; /* 0 for frame buffer, 1 for AGP , 2 for System*/
+	int used;
+	int context;
+	set_t *sets[2];		/* 0 for frame buffer, 1 for AGP , 2 for System */
 } via_context_t;
 
 static via_context_t global_ppriv[MAX_CONTEXT];
 
 static int add_alloc_set(int context, int type, unsigned int val)
 {
-        int i, retval = 0;
-  
-        for (i = 0; i < MAX_CONTEXT; i++) {
-                if (global_ppriv[i].used && 
-                    global_ppriv[i].context == context) {
-                        retval = via_setAdd(global_ppriv[i].sets[type], val);
-                        break;
-                }
-        }
-  
-        return retval;
+	int i, retval = 0;
+
+	for (i = 0; i < MAX_CONTEXT; i++) {
+		if (global_ppriv[i].used && global_ppriv[i].context == context) {
+			retval = via_setAdd(global_ppriv[i].sets[type], val);
+			break;
+		}
+	}
+
+	return retval;
 }
 
 static int del_alloc_set(int context, int type, unsigned int val)
-{  
-        int i, retval = 0;
-  
-        for (i = 0; i < MAX_CONTEXT; i++)
-                if (global_ppriv[i].used && 
-                    global_ppriv[i].context == context) {
-                        retval = via_setDel(global_ppriv[i].sets[type], val);
-                        break;
-                }
-  
-        return retval;
+{
+	int i, retval = 0;
+
+	for (i = 0; i < MAX_CONTEXT; i++)
+		if (global_ppriv[i].used && global_ppriv[i].context == context) {
+			retval = via_setDel(global_ppriv[i].sets[type], val);
+			break;
+		}
+
+	return retval;
 }
 
-/* agp memory management */ 
+/* agp memory management */
 static memHeap_t *AgpHeap = NULL;
 
-int via_agp_init( DRM_IOCTL_ARGS )
+int via_agp_init(DRM_IOCTL_ARGS)
 {
-        drm_via_agp_t agp;
-  
-        DRM_COPY_FROM_USER_IOCTL(agp, (drm_via_agp_t *)data, sizeof(agp));
+	drm_via_agp_t agp;
+
+	DRM_COPY_FROM_USER_IOCTL(agp, (drm_via_agp_t *) data, sizeof(agp));
+
+	AgpHeap = via_mmInit(agp.offset, agp.size);
 
-        AgpHeap = via_mmInit(agp.offset, agp.size);
+	DRM_DEBUG("offset = %u, size = %u", agp.offset, agp.size);
 
-        DRM_DEBUG("offset = %u, size = %u", agp.offset, agp.size);
-  
-        return 0;
+	return 0;
 }
 
-/* fb memory management */ 
+/* fb memory management */
 static memHeap_t *FBHeap = NULL;
 
-int via_fb_init( DRM_IOCTL_ARGS )
+int via_fb_init(DRM_IOCTL_ARGS)
 {
-        drm_via_fb_t fb;
+	drm_via_fb_t fb;
 
-   
-        DRM_COPY_FROM_USER_IOCTL(fb, (drm_via_fb_t *)data, sizeof(fb));
+	DRM_COPY_FROM_USER_IOCTL(fb, (drm_via_fb_t *) data, sizeof(fb));
 
-        FBHeap = via_mmInit(fb.offset, fb.size);
+	FBHeap = via_mmInit(fb.offset, fb.size);
 
-        DRM_DEBUG("offset = %u, size = %u", fb.offset, fb.size);
+	DRM_DEBUG("offset = %u, size = %u", fb.offset, fb.size);
 
-        return 0;
+	return 0;
 }
 
 int via_init_context(struct drm_device *dev, int context)
 {
-        int i;
-    
-        for (i = 0; i < MAX_CONTEXT ; i++)
-                if (global_ppriv[i].used && 
-                    (global_ppriv[i].context == context))
-                        break;
-    
-        if (i >= MAX_CONTEXT) {
-                for (i = 0; i < MAX_CONTEXT ; i++) {
-                        if (!global_ppriv[i].used) {
-                                global_ppriv[i].context = context;
-                                global_ppriv[i].used = 1;
-                                global_ppriv[i].sets[0] = via_setInit();
-                                global_ppriv[i].sets[1] = via_setInit();
-                                DRM_DEBUG("init allocation set, socket=%d,"
-                                          " context = %d\n", i, context);
-                                break;
-                        }
-                }
-	
-                if ((i >= MAX_CONTEXT) || (global_ppriv[i].sets[0] == NULL) ||
-                    (global_ppriv[i].sets[1] == NULL)) {
-                        return 0;
-                }
-        }
-    
-        return 1;
+	int i;
+
+	for (i = 0; i < MAX_CONTEXT; i++)
+		if (global_ppriv[i].used &&
+		    (global_ppriv[i].context == context))
+			break;
+
+	if (i >= MAX_CONTEXT) {
+		for (i = 0; i < MAX_CONTEXT; i++) {
+			if (!global_ppriv[i].used) {
+				global_ppriv[i].context = context;
+				global_ppriv[i].used = 1;
+				global_ppriv[i].sets[0] = via_setInit();
+				global_ppriv[i].sets[1] = via_setInit();
+				DRM_DEBUG("init allocation set, socket=%d,"
+					  " context = %d\n", i, context);
+				break;
+			}
+		}
+
+		if ((i >= MAX_CONTEXT) || (global_ppriv[i].sets[0] == NULL) ||
+		    (global_ppriv[i].sets[1] == NULL)) {
+			return 0;
+		}
+	}
+
+	return 1;
 }
 
 int via_final_context(struct drm_device *dev, int context)
 {
-        int i;
-        for (i=0; i<MAX_CONTEXT; i++)
-                if (global_ppriv[i].used && 
-                    (global_ppriv[i].context == context))
-                        break;
-    
-        if (i < MAX_CONTEXT) {
-                set_t *set;
-                unsigned int item;
-                int retval;
-	  
-                DRM_DEBUG("find socket %d, context = %d\n", i, context);
-	    
-                /* Video Memory */
-                set = global_ppriv[i].sets[0];
-                retval = via_setFirst(set, &item);
-                while (retval) {
-                        DRM_DEBUG("free video memory 0x%x\n", item);
-                        via_mmFreeMem((PMemBlock)item);
-                        retval = via_setNext(set, &item);
-                }
-                via_setDestroy(set);
-	    
-                /* AGP Memory */
-                set = global_ppriv[i].sets[1];
-                retval = via_setFirst(set, &item);
-                while (retval) {
-                        DRM_DEBUG("free agp memory 0x%x\n", item);
-                        via_mmFreeMem((PMemBlock)item);
-                        retval = via_setNext(set, &item);
-                }
-                via_setDestroy(set);
-	
-                global_ppriv[i].used = 0;	  
-        }
-
+	int i;
+	for (i = 0; i < MAX_CONTEXT; i++)
+		if (global_ppriv[i].used &&
+		    (global_ppriv[i].context == context))
+			break;
+
+	if (i < MAX_CONTEXT) {
+		set_t *set;
+		unsigned int item;
+		int retval;
+
+		DRM_DEBUG("find socket %d, context = %d\n", i, context);
+
+		/* Video Memory */
+		set = global_ppriv[i].sets[0];
+		retval = via_setFirst(set, &item);
+		while (retval) {
+			DRM_DEBUG("free video memory 0x%x\n", item);
+			via_mmFreeMem((PMemBlock) item);
+			retval = via_setNext(set, &item);
+		}
+		via_setDestroy(set);
+
+		/* AGP Memory */
+		set = global_ppriv[i].sets[1];
+		retval = via_setFirst(set, &item);
+		while (retval) {
+			DRM_DEBUG("free agp memory 0x%x\n", item);
+			via_mmFreeMem((PMemBlock) item);
+			retval = via_setNext(set, &item);
+		}
+		via_setDestroy(set);
+
+		global_ppriv[i].used = 0;
+	}
 #if defined(__linux__)
-        /* Linux specific until context tracking code gets ported to BSD */
+	/* Linux specific until context tracking code gets ported to BSD */
 	/* Last context, perform cleanup */
 	if (dev->ctx_count == 1 && dev->dev_private) {
-		if (dev->irq) drm_irq_uninstall(dev);
+		if (dev->irq)
+			drm_irq_uninstall(dev);
 
 		via_do_cleanup_map(dev);
 	}
 #endif
-    
-        return 1;
+
+	return 1;
 }
-int via_mem_alloc( DRM_IOCTL_ARGS)
+
+int via_mem_alloc(DRM_IOCTL_ARGS)
 {
-        drm_via_mem_t mem;
-    
-        DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t *)data, sizeof(mem));
-        switch (mem.type) {
-        case VIDEO :
-                if (via_fb_alloc(&mem) < 0)
-                        return -EFAULT;
-                DRM_COPY_TO_USER_IOCTL((drm_via_mem_t *)data, mem, 
-                                       sizeof(mem));
-                return 0;
-        case AGP :
-                if (via_agp_alloc(&mem) < 0)
-                        return -EFAULT;
-                DRM_COPY_TO_USER_IOCTL((drm_via_mem_t *)data, mem, 
-                                       sizeof(mem));
-                return 0;
-        }
-
-        return -EFAULT;
+	drm_via_mem_t mem;
+
+	DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t *) data, sizeof(mem));
+	switch (mem.type) {
+	case VIDEO:
+		if (via_fb_alloc(&mem) < 0)
+			return -EFAULT;
+		DRM_COPY_TO_USER_IOCTL((drm_via_mem_t *) data, mem,
+				       sizeof(mem));
+		return 0;
+	case AGP:
+		if (via_agp_alloc(&mem) < 0)
+			return -EFAULT;
+		DRM_COPY_TO_USER_IOCTL((drm_via_mem_t *) data, mem,
+				       sizeof(mem));
+		return 0;
+	}
+
+	return -EFAULT;
 }
 
-int via_fb_alloc(drm_via_mem_t* mem)
+int via_fb_alloc(drm_via_mem_t * mem)
 {
-        drm_via_mm_t fb;
-        PMemBlock block;
-        int retval = 0;
-
-        if (!FBHeap)
-                return -1;
-
-        fb.size = mem->size;
-        fb.context = mem->context;
-
-        block = via_mmAllocMem(FBHeap, fb.size, 5, 0);
-        if (block) {
-                fb.offset = block->ofs;
-                fb.free = (unsigned int)block;
-                if (!add_alloc_set(fb.context, VIDEO, fb.free)) {
-                        DRM_DEBUG("adding to allocation set fails\n");
-                        via_mmFreeMem((PMemBlock)fb.free);
-                        retval = -1;
-                }
-        }
-        else {  
-                fb.offset = 0;
-                fb.size = 0;
-                fb.free = 0;
-                retval = -1;
-        }
-
-        mem->offset = fb.offset;
-        mem->index = fb.free;
-
-        DRM_DEBUG("alloc fb, size = %d, offset = %d\n", fb.size, 
-                  (int)fb.offset);
-
-        return retval;
+	drm_via_mm_t fb;
+	PMemBlock block;
+	int retval = 0;
+
+	if (!FBHeap)
+		return -1;
+
+	fb.size = mem->size;
+	fb.context = mem->context;
+
+	block = via_mmAllocMem(FBHeap, fb.size, 5, 0);
+	if (block) {
+		fb.offset = block->ofs;
+		fb.free = (unsigned int)block;
+		if (!add_alloc_set(fb.context, VIDEO, fb.free)) {
+			DRM_DEBUG("adding to allocation set fails\n");
+			via_mmFreeMem((PMemBlock) fb.free);
+			retval = -1;
+		}
+	} else {
+		fb.offset = 0;
+		fb.size = 0;
+		fb.free = 0;
+		retval = -1;
+	}
+
+	mem->offset = fb.offset;
+	mem->index = fb.free;
+
+	DRM_DEBUG("alloc fb, size = %d, offset = %d\n", fb.size,
+		  (int)fb.offset);
+
+	return retval;
 }
-int via_agp_alloc(drm_via_mem_t* mem)
+
+int via_agp_alloc(drm_via_mem_t * mem)
 {
-        drm_via_mm_t agp;
-        PMemBlock block;
-        int retval = 0;
-
-        if (!AgpHeap)
-                return -1;
-
-        agp.size = mem->size;
-        agp.context = mem->context;
-  
-        block = via_mmAllocMem(AgpHeap, agp.size, 5, 0);
-        if (block) {
-                agp.offset = block->ofs;
-                agp.free = (unsigned int)block;
-                if (!add_alloc_set(agp.context, AGP, agp.free)) {
-                        DRM_DEBUG("adding to allocation set fails\n");
-                        via_mmFreeMem((PMemBlock)agp.free);
-                        retval = -1;
-                }
-        }
-        else {  
-                agp.offset = 0;
-                agp.size = 0;
-                agp.free = 0;
-        }	
-
-        mem->offset = agp.offset;
-        mem->index = agp.free;
-
-        DRM_DEBUG("alloc agp, size = %d, offset = %d\n", agp.size, 
-                  (unsigned int)agp.offset);
-        return retval;
+	drm_via_mm_t agp;
+	PMemBlock block;
+	int retval = 0;
+
+	if (!AgpHeap)
+		return -1;
+
+	agp.size = mem->size;
+	agp.context = mem->context;
+
+	block = via_mmAllocMem(AgpHeap, agp.size, 5, 0);
+	if (block) {
+		agp.offset = block->ofs;
+		agp.free = (unsigned int)block;
+		if (!add_alloc_set(agp.context, AGP, agp.free)) {
+			DRM_DEBUG("adding to allocation set fails\n");
+			via_mmFreeMem((PMemBlock) agp.free);
+			retval = -1;
+		}
+	} else {
+		agp.offset = 0;
+		agp.size = 0;
+		agp.free = 0;
+	}
+
+	mem->offset = agp.offset;
+	mem->index = agp.free;
+
+	DRM_DEBUG("alloc agp, size = %d, offset = %d\n", agp.size,
+		  (unsigned int)agp.offset);
+	return retval;
 }
 
-int via_mem_free( DRM_IOCTL_ARGS )
+int via_mem_free(DRM_IOCTL_ARGS)
 {
-        drm_via_mem_t mem;
+	drm_via_mem_t mem;
 
-        DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t *)data, sizeof(mem));
+	DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t *) data, sizeof(mem));
 
-        switch (mem.type) {
+	switch (mem.type) {
 
-        case VIDEO :
-                if (via_fb_free(&mem) == 0)
-                        return 0;
-                break;
-        case AGP :
-                if (via_agp_free(&mem) == 0)
-                        return 0;
-                break;
-        }
+	case VIDEO:
+		if (via_fb_free(&mem) == 0)
+			return 0;
+		break;
+	case AGP:
+		if (via_agp_free(&mem) == 0)
+			return 0;
+		break;
+	}
 
-        return -EFAULT;
+	return -EFAULT;
 }
 
-int via_fb_free(drm_via_mem_t* mem)
+int via_fb_free(drm_via_mem_t * mem)
 {
-        drm_via_mm_t fb;
-        int retval = 0;
+	drm_via_mm_t fb;
+	int retval = 0;
 
+	if (!FBHeap) {
+		return -1;
+	}
 
-        if (!FBHeap) {
-                return -1;
-        }
-
-        fb.free = mem->index;
-        fb.context = mem->context;
+	fb.free = mem->index;
+	fb.context = mem->context;
 
-        if (!fb.free)
-                {
-                        return -1;
+	if (!fb.free) {
+		return -1;
 
-                }
+	}
 
-        via_mmFreeMem((PMemBlock)fb.free);
+	via_mmFreeMem((PMemBlock) fb.free);
 
-        if (!del_alloc_set(fb.context, VIDEO, fb.free))
-                {
-                        retval = -1;
-                }
+	if (!del_alloc_set(fb.context, VIDEO, fb.free)) {
+		retval = -1;
+	}
 
-        DRM_DEBUG("free fb, free = %d\n", fb.free);
+	DRM_DEBUG("free fb, free = %d\n", fb.free);
 
-        return retval;
+	return retval;
 }
 
-int via_agp_free(drm_via_mem_t* mem)
+int via_agp_free(drm_via_mem_t * mem)
 {
-        drm_via_mm_t agp;
+	drm_via_mm_t agp;
 
-        int retval = 0;
+	int retval = 0;
 
-        agp.free = mem->index;
-        agp.context = mem->context;
+	agp.free = mem->index;
+	agp.context = mem->context;
 
-        if (!agp.free)
-                return -1;
+	if (!agp.free)
+		return -1;
 
-        via_mmFreeMem((PMemBlock)agp.free);
+	via_mmFreeMem((PMemBlock) agp.free);
 
-        if (!del_alloc_set(agp.context, AGP, agp.free)) {
-                retval = -1;
+	if (!del_alloc_set(agp.context, AGP, agp.free)) {
+		retval = -1;
 	}
 
-        DRM_DEBUG("free agp, free = %d\n", agp.free);
+	DRM_DEBUG("free agp, free = %d\n", agp.free);
 
-        return retval;
+	return retval;
 }
-
diff --git a/shared-core/via_mm.h b/shared-core/via_mm.h
index c476ac6a..ea83a0ba 100644
--- a/shared-core/via_mm.h
+++ b/shared-core/via_mm.h
@@ -25,21 +25,21 @@
 #define _via_drm_mm_h_
 
 typedef struct {
-        unsigned int context;
-        unsigned int size;
-        unsigned long offset;
-        unsigned int free;
+	unsigned int context;
+	unsigned int size;
+	unsigned long offset;
+	unsigned int free;
 } drm_via_mm_t;
 
 typedef struct {
-        unsigned int size;
-        unsigned long handle;
-        void *virtual;
+	unsigned int size;
+	unsigned long handle;
+	void *virtual;
 } drm_via_dma_t;
 
-int via_fb_alloc(drm_via_mem_t *mem);
-int via_fb_free(drm_via_mem_t *mem);
-int via_agp_alloc(drm_via_mem_t *mem);
-int via_agp_free(drm_via_mem_t *mem);
+int via_fb_alloc(drm_via_mem_t * mem);
+int via_fb_free(drm_via_mem_t * mem);
+int via_agp_alloc(drm_via_mem_t * mem);
+int via_agp_free(drm_via_mem_t * mem);
 
 #endif