summaryrefslogtreecommitdiff
path: root/drivers/accel/ivpu/ivpu_hw.c
blob: 1c259d7178151bb2b8594bea0b4af2460dc49e0e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2020 - 2024 Intel Corporation
 */

#include "ivpu_drv.h"
#include "ivpu_hw.h"
#include "ivpu_hw_btrs.h"
#include "ivpu_hw_ip.h"

#include <linux/dmi.h>

static char *platform_to_str(u32 platform)
{
	switch (platform) {
	case IVPU_PLATFORM_SILICON:
		return "SILICON";
	case IVPU_PLATFORM_SIMICS:
		return "SIMICS";
	case IVPU_PLATFORM_FPGA:
		return "FPGA";
	default:
		return "Invalid platform";
	}
}

static const struct dmi_system_id dmi_platform_simulation[] = {
	{
		.ident = "Intel Simics",
		.matches = {
			DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"),
			DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
			DMI_MATCH(DMI_BOARD_SERIAL, "123456789"),
		},
	},
	{
		.ident = "Intel Simics",
		.matches = {
			DMI_MATCH(DMI_BOARD_NAME, "Simics"),
		},
	},
	{ }
};

static void platform_init(struct ivpu_device *vdev)
{
	if (dmi_check_system(dmi_platform_simulation))
		vdev->platform = IVPU_PLATFORM_SIMICS;
	else
		vdev->platform = IVPU_PLATFORM_SILICON;

	ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n",
		 platform_to_str(vdev->platform), vdev->platform);
}

static void wa_init(struct ivpu_device *vdev)
{
	vdev->wa.punit_disabled = ivpu_is_fpga(vdev);
	vdev->wa.clear_runtime_mem = false;

	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
		vdev->wa.interrupt_clear_with_0 = ivpu_hw_btrs_irqs_clear_with_0_mtl(vdev);

	if (ivpu_device_id(vdev) == PCI_DEVICE_ID_LNL &&
	    ivpu_revision(vdev) < IVPU_HW_IP_REV_LNL_B0)
		vdev->wa.disable_clock_relinquish = true;

	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
		vdev->wa.wp0_during_power_up = true;

	IVPU_PRINT_WA(punit_disabled);
	IVPU_PRINT_WA(clear_runtime_mem);
	IVPU_PRINT_WA(interrupt_clear_with_0);
	IVPU_PRINT_WA(disable_clock_relinquish);
	IVPU_PRINT_WA(wp0_during_power_up);
}

static void timeouts_init(struct ivpu_device *vdev)
{
	if (ivpu_test_mode & IVPU_TEST_MODE_DISABLE_TIMEOUTS) {
		vdev->timeout.boot = -1;
		vdev->timeout.jsm = -1;
		vdev->timeout.tdr = -1;
		vdev->timeout.autosuspend = -1;
		vdev->timeout.d0i3_entry_msg = -1;
	} else if (ivpu_is_fpga(vdev)) {
		vdev->timeout.boot = 100000;
		vdev->timeout.jsm = 50000;
		vdev->timeout.tdr = 2000000;
		vdev->timeout.autosuspend = -1;
		vdev->timeout.d0i3_entry_msg = 500;
		vdev->timeout.state_dump_msg = 10;
	} else if (ivpu_is_simics(vdev)) {
		vdev->timeout.boot = 50;
		vdev->timeout.jsm = 500;
		vdev->timeout.tdr = 10000;
		vdev->timeout.autosuspend = 100;
		vdev->timeout.d0i3_entry_msg = 100;
		vdev->timeout.state_dump_msg = 10;
	} else {
		vdev->timeout.boot = 1000;
		vdev->timeout.jsm = 500;
		vdev->timeout.tdr = 2000;
		if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
			vdev->timeout.autosuspend = 10;
		else
			vdev->timeout.autosuspend = 100;
		vdev->timeout.d0i3_entry_msg = 5;
		vdev->timeout.state_dump_msg = 10;
	}
}

static void memory_ranges_init(struct ivpu_device *vdev)
{
	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
		ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
		ivpu_hw_range_init(&vdev->hw->ranges.user,   0xc0000000, 255 * SZ_1M);
		ivpu_hw_range_init(&vdev->hw->ranges.shave, 0x180000000, SZ_2G);
		ivpu_hw_range_init(&vdev->hw->ranges.dma,   0x200000000, SZ_8G);
	} else {
		ivpu_hw_range_init(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
		ivpu_hw_range_init(&vdev->hw->ranges.user,   0x80000000, SZ_256M);
		ivpu_hw_range_init(&vdev->hw->ranges.shave,  0x80000000 + SZ_256M, SZ_2G - SZ_256M);
		ivpu_hw_range_init(&vdev->hw->ranges.dma,   0x200000000, SZ_8G);
	}
}

static int wp_enable(struct ivpu_device *vdev)
{
	return ivpu_hw_btrs_wp_drive(vdev, true);
}

static int wp_disable(struct ivpu_device *vdev)
{
	return ivpu_hw_btrs_wp_drive(vdev, false);
}

int ivpu_hw_power_up(struct ivpu_device *vdev)
{
	int ret;

	if (IVPU_WA(wp0_during_power_up)) {
		/* WP requests may fail when powering down, so issue WP 0 here */
		ret = wp_disable(vdev);
		if (ret)
			ivpu_warn(vdev, "Failed to disable workpoint: %d\n", ret);
	}

	ret = ivpu_hw_btrs_d0i3_disable(vdev);
	if (ret)
		ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);

	ret = wp_enable(vdev);
	if (ret) {
		ivpu_err(vdev, "Failed to enable workpoint: %d\n", ret);
		return ret;
	}

	if (ivpu_hw_btrs_gen(vdev) >= IVPU_HW_BTRS_LNL) {
		if (IVPU_WA(disable_clock_relinquish))
			ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev);
		ivpu_hw_btrs_profiling_freq_reg_set_lnl(vdev);
		ivpu_hw_btrs_ats_print_lnl(vdev);
	}

	ret = ivpu_hw_ip_host_ss_configure(vdev);
	if (ret) {
		ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
		return ret;
	}

	ivpu_hw_ip_idle_gen_disable(vdev);

	ret = ivpu_hw_btrs_wait_for_clock_res_own_ack(vdev);
	if (ret) {
		ivpu_err(vdev, "Timed out waiting for clock resource own ACK\n");
		return ret;
	}

	ret = ivpu_hw_ip_pwr_domain_enable(vdev);
	if (ret) {
		ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
		return ret;
	}

	ret = ivpu_hw_ip_host_ss_axi_enable(vdev);
	if (ret) {
		ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
		return ret;
	}

	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_LNL)
		ivpu_hw_btrs_set_port_arbitration_weights_lnl(vdev);

	ret = ivpu_hw_ip_top_noc_enable(vdev);
	if (ret)
		ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);

	return ret;
}

static void save_d0i3_entry_timestamp(struct ivpu_device *vdev)
{
	vdev->hw->d0i3_entry_host_ts = ktime_get_boottime();
	vdev->hw->d0i3_entry_vpu_ts = ivpu_hw_ip_read_perf_timer_counter(vdev);
}

int ivpu_hw_reset(struct ivpu_device *vdev)
{
	int ret = 0;

	if (ivpu_hw_btrs_ip_reset(vdev)) {
		ivpu_err(vdev, "Failed to reset NPU IP\n");
		ret = -EIO;
	}

	if (wp_disable(vdev)) {
		ivpu_err(vdev, "Failed to disable workpoint\n");
		ret = -EIO;
	}

	return ret;
}

int ivpu_hw_power_down(struct ivpu_device *vdev)
{
	int ret = 0;

	save_d0i3_entry_timestamp(vdev);

	if (!ivpu_hw_is_idle(vdev))
		ivpu_warn(vdev, "NPU not idle during power down\n");

	if (ivpu_hw_reset(vdev)) {
		ivpu_err(vdev, "Failed to reset NPU\n");
		ret = -EIO;
	}

	if (ivpu_hw_btrs_d0i3_enable(vdev)) {
		ivpu_err(vdev, "Failed to enter D0I3\n");
		ret = -EIO;
	}

	return ret;
}

int ivpu_hw_init(struct ivpu_device *vdev)
{
	ivpu_hw_btrs_info_init(vdev);
	ivpu_hw_btrs_freq_ratios_init(vdev);
	memory_ranges_init(vdev);
	platform_init(vdev);
	wa_init(vdev);
	timeouts_init(vdev);

	return 0;
}

int ivpu_hw_boot_fw(struct ivpu_device *vdev)
{
	int ret;

	ivpu_hw_ip_snoop_disable(vdev);
	ivpu_hw_ip_tbu_mmu_enable(vdev);
	ret = ivpu_hw_ip_soc_cpu_boot(vdev);
	if (ret)
		ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret);

	return ret;
}

void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable)
{
	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
		vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
		return;
	}

	if (enable)
		vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH;
	else
		vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
}

void ivpu_irq_handlers_init(struct ivpu_device *vdev)
{
	INIT_KFIFO(vdev->hw->irq.fifo);

	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
		vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_37xx;
	else
		vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_40xx;

	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
		vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_mtl;
	else
		vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_lnl;
}

void ivpu_hw_irq_enable(struct ivpu_device *vdev)
{
	kfifo_reset(&vdev->hw->irq.fifo);
	ivpu_hw_ip_irq_enable(vdev);
	ivpu_hw_btrs_irq_enable(vdev);
}

void ivpu_hw_irq_disable(struct ivpu_device *vdev)
{
	ivpu_hw_btrs_irq_disable(vdev);
	ivpu_hw_ip_irq_disable(vdev);
}

irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr)
{
	struct ivpu_device *vdev = ptr;
	bool ip_handled, btrs_handled;

	ivpu_hw_btrs_global_int_disable(vdev);

	btrs_handled = ivpu_hw_btrs_irq_handler(vdev, irq);
	if (!ivpu_hw_is_idle((vdev)) || !btrs_handled)
		ip_handled = ivpu_hw_ip_irq_handler(vdev, irq);
	else
		ip_handled = false;

	/* Re-enable global interrupts to re-trigger MSI for pending interrupts */
	ivpu_hw_btrs_global_int_enable(vdev);

	if (!kfifo_is_empty(&vdev->hw->irq.fifo))
		return IRQ_WAKE_THREAD;
	if (ip_handled || btrs_handled)
		return IRQ_HANDLED;
	return IRQ_NONE;
}