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AgeCommit message (Expand)AuthorFilesLines
2024-10-02move asm/unaligned.h to linux/unaligned.hAl Viro1-1/+1
2024-09-12cxl: Move mailbox related bits to the same contextDave Jiang1-11/+33
2024-09-09cxl/pci: Remove duplicated implementation of waiting for memory_info_validYanfei Xu1-2/+2
2024-09-03cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()Li Ming2-4/+4
2024-09-03tools/testing/cxl: Use dev_is_platform()Kunwu Chan1-1/+1
2024-08-09cxl/test: Skip cxl_setup_parent_dport() for emulated dportsLi Ming2-0/+13
2024-07-28Merge tag 'cxl-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-33/+36
2024-07-10cxl/test: Replace ENXIO with EBUSY for inject poison limit reachedAlison Schofield1-8/+7
2024-07-02cxl/events: Use a common struct for DRAM and General Media eventsFabio M. De Francesco1-25/+29
2024-06-25cxl/region: check interleave capabilityYao Xingtao1-0/+4
2024-05-28cxl/test: Add missing vmalloc.h for tools/testing/cxl/test/mem.cDave Jiang1-0/+1
2024-05-15Merge tag 'cxl-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-4/+15
2024-04-30cxl/test: Enhance event testingIra Weiny1-4/+15
2024-04-29cxl: Fix cxl_endpoint_get_perf_coordinate() support for RCHDave Jiang1-0/+7
2024-04-08cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coordDave Jiang1-4/+6
2024-02-16cxl/test: Add support for qos_class checkingDave Jiang4-9/+70
2024-01-22tools/testing/cxl: Disable "missing prototypes / declarations" warningsDan Williams2-0/+4
2024-01-09Merge branch 'for-6.8/cxl-cper' into for-6.8/cxlDan Williams1-70/+93
2024-01-09cxl/events: Create a CXL event unionIra Weiny1-13/+18
2024-01-09cxl/events: Separate UUID from event structuresIra Weiny1-54/+75
2024-01-09cxl/events: Create common event UUID definesIra Weiny1-6/+3
2023-12-22tools/testing/cxl: Add hostbridge UID string for cxl_test mock hb devicesDave Jiang1-0/+4
2023-12-22cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang1-0/+1
2023-12-04cxl: Add cxl_num_decoders_committed() usage to cxl_testDave Jiang3-2/+11
2023-10-31Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams1-3/+1
2023-10-27cxl/pci: Remove Component Register base address from struct cxl_dev_stateRobert Richter1-3/+1
2023-10-27tools/testing/cxl: Slow down the mock firmware transferVishal Verma1-0/+1
2023-10-27cxl/region: Fix x1 root-decoder granularity calculationsJim Harris1-1/+1
2023-10-09tools/testing/cxl: Add 'sanitize notifier' supportDan Williams1-1/+67
2023-10-09tools/testing/cxl: Make cxl_memdev_state available to other command emulationDan Williams1-3/+3
2023-10-06cxl/pci: Clarify devm host for memdev relative setupDan Williams1-2/+2
2023-07-20tools/testing/cxl: Remove unused SZ_512G macroXiao Yang1-4/+0
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams4-35/+45
2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams1-0/+1
2023-06-25Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams4-104/+79
2023-06-25Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxlDan Williams1-9/+183
2023-06-25tools/testing/cxl: add firmware update emulation to CXL memdevsVishal Verma1-0/+160
2023-06-25tools/testing/cxl: Use named effects for the Command Effect LogVishal Verma1-9/+23
2023-06-25tools/testing/cxl: Fix command effects for inject/clear poisonVishal Verma1-2/+2
2023-06-25cxl/test: Add Secure Erase opcode supportDavidlohr Bueso1-0/+27
2023-06-25cxl/test: Add Sanitize opcode supportDavidlohr Bueso1-0/+25
2023-06-25Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams2-16/+0
2023-06-25cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams1-3/+3
2023-06-25cxl/mbox: Move mailbox related driver state to its own data structureDan Williams1-19/+24
2023-06-25tools/testing/cxl: Remove unused @cxlds argumentDan Williams1-47/+39
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams2-15/+15
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams1-1/+3
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter4-21/+29
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron1-0/+1
2023-05-18cxl: Move cxl_await_media_ready() to before capacity info retrievalDave Jiang1-0/+1
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