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path: root/drivers/clk/tegra/clk-tegra-super-gen4.c
AgeCommit message (Expand)AuthorFilesLines
2019-11-11clk: tegra: clk-super: Fix to enable PLLP branches to CPUSowjanya Komatineni1-1/+6
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner1-12/+1
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko1-3/+5
2017-11-01clk: tegra: Mark APB clock as criticalJon Hunter1-1/+1
2017-08-23clk: tegra: Re-factor T210 PLLX registrationAlex Frid1-2/+9
2016-02-02clk: tegra: super: Fix sparse warnings for functions not declared as staticJon Hunter1-3/+3
2015-12-17clk: tegra: Add Super Gen5 LogicBill Huang1-13/+129
2015-08-25Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd1-1/+3
2015-07-20clk: tegra: Properly include clk.hStephen Boyd1-1/+0
2015-07-16clk: tegra: Add the DFLL as a possible parent of the cclk_g clockTuomas Tynkkynen1-1/+3
2014-02-17clk: tegra: cclk_lp has a pllx/2 dividerAndrew Bresticker1-1/+1
2013-11-26clk: tegra: introduce common gen4 super clockPeter De Schrijver1-0/+149