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path: root/drivers/clk/hisilicon/crg-hi3798cv200.c
AgeCommit message (Expand)AuthorFilesLines
2019-05-21treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13Thomas Gleixner1-13/+1
2018-05-15clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoCJianguo Sun1-0/+17
2018-03-12clk: hi3798cv200: add emmc sample and drive clocktianshuliang1-0/+20
2018-02-27clk: hi3798cv200: add COMBPHY0 clock supportJianguo Sun1-4/+11
2018-02-27clk: hi3798cv200: fix define indentationShawn Guo1-24/+24
2018-02-27clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLKShawn Guo1-0/+2
2018-02-27clk: hi3798cv200: correct IR clock parentYounian Wang1-1/+1
2018-02-27clk: hi3798cv200: fix unregister call sequence in error pathShawn Guo1-7/+6
2017-11-14clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'Shawn Guo1-1/+11
2017-06-21clk: hisilicon: add usb2 clocks for hi3798cv200 SoCJiancheng Xue1-0/+21
2016-11-11clk: hisilicon: add CRG driver for Hi3798CV200 SoCJiancheng Xue1-0/+337