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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2015-02-02 14:09:39 +0900
committerBjorn Helgaas <bhelgaas@google.com>2015-02-23 19:04:09 -0600
commit1fc6aa96ead7535e0fa7458881b07cbc58a9fd89 (patch)
tree5f97fb9f75e22750ab681aae9c895e1f149f07f6 /drivers/pci
parentc517d838eb7d07bbe9507871fab3931deccff539 (diff)
PCI: rcar: Fix position of MSI enable bit
The MSI enable is bit 31, not bit 28. Set the correct bit to initialize MSI. Per Phil, "this is odd as MSI works before and after your patch. Since bit 31 just represents the value of MSICAP0[16].MSIE, I think this may just be used for endpoints. However, you are correct that the bit used was wrong." Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pcie-rcar.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index c57bd0ac39a0..8f5490f443ff 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -501,7 +501,7 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
/* Enable MSI */
if (IS_ENABLED(CONFIG_PCI_MSI))
- rcar_pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
+ rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
/* Finish initialization - establish a PCI Express link */
rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);