diff options
author | Jacob Pan <jacob.jun.pan@linux.intel.com> | 2024-04-23 10:41:08 -0700 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2024-04-30 00:54:42 +0200 |
commit | 43650dcf6d6322ec2d0938bb51f755810ffa783a (patch) | |
tree | 2cd02699df1c194b5e3a0749d6a89f3e4d7d2a87 /arch/x86/include/asm/posted_intr.h | |
parent | f5a3562ec9dd29e61735ccf098d8ba05cf6c7c72 (diff) |
x86/irq: Set up per host CPU posted interrupt descriptors
To support posted MSIs, create a posted interrupt descriptor (PID) for each
host CPU. Later on, when setting up interrupt affinity, the IOMMU's
interrupt remapping table entry (IRTE) will point to the physical address
of the matching CPU's PID.
Each PID is initialized with the owner CPU's physical APICID as the
destination.
Originally-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240423174114.526704-7-jacob.jun.pan@linux.intel.com
Diffstat (limited to 'arch/x86/include/asm/posted_intr.h')
-rw-r--r-- | arch/x86/include/asm/posted_intr.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/include/asm/posted_intr.h b/arch/x86/include/asm/posted_intr.h index 20e31891de15..6f84f6739d99 100644 --- a/arch/x86/include/asm/posted_intr.h +++ b/arch/x86/include/asm/posted_intr.h @@ -91,4 +91,10 @@ static inline void __pi_clear_sn(struct pi_desc *pi_desc) pi_desc->notifications &= ~BIT(POSTED_INTR_SN); } +#ifdef CONFIG_X86_POSTED_MSI +extern void intel_posted_msi_init(void); +#else +static inline void intel_posted_msi_init(void) {}; +#endif /* X86_POSTED_MSI */ + #endif /* _X86_POSTED_INTR_H */ |