diff options
| author | Kan Liang <kan.liang@linux.intel.com> | 2020-02-06 08:15:27 -0800 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2020-02-11 13:23:49 +0100 |
| commit | fdb64822443ec9fb8c3a74b598a74790ae8d2e22 (patch) | |
| tree | b849b2362b4b2cfd428ea1a6df2c3ee0fe041f5f /arch/x86/events/intel/uncore.h | |
| parent | db278b90c326ce5895be09b6171f5ff3df1e3cca (diff) | |
perf/x86: Add Intel Tiger Lake uncore support
For MSR type of uncore units, there is no difference between Ice Lake
and Tiger Lake. Share the same code with Ice Lake.
Tiger Lake has two MCs. Both of them are located at 0:0:0. The BAR
offset is still 0x48. The offset of the two MCs is 0x10000.
Each MC has three counters to count every read/write/total issued by the
Memory Controller to DRAM. The counters can be accessed by MMIO.
They are free-running counters.
The offset of counters are different for TIGERLAKE_L and TIGERLAKE.
Add separated mmio_init() functions.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20200206161527.3529-1-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events/intel/uncore.h')
| -rw-r--r-- | arch/x86/events/intel/uncore.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index bbfdaa720b45..1204dcc9fe9b 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -527,6 +527,8 @@ void snb_uncore_cpu_init(void); void nhm_uncore_cpu_init(void); void skl_uncore_cpu_init(void); void icl_uncore_cpu_init(void); +void tgl_uncore_mmio_init(void); +void tgl_l_uncore_mmio_init(void); int snb_pci2phy_map_init(int devid); /* uncore_snbep.c */ |