summaryrefslogtreecommitdiff
path: root/arch/mips/lantiq
diff options
context:
space:
mode:
authorJohn Crispin <blogic@openwrt.org>2012-08-16 08:25:42 +0000
committerJohn Crispin <blogic@openwrt.org>2012-08-23 00:08:18 +0200
commitf40e1f9d856ec417468c090c4b56826171daa670 (patch)
tree473073168643374dfec8caca3199286c85705793 /arch/mips/lantiq
parent3a6ac5004c7c8b140319439f8b1f3f6d4cbfe67a (diff)
MIPS: lantiq: enable pci clk conditional for xrx200 SoC
The xrx200 SoC family has the same PCI clock register layout as the AR9. Enable the same quirk as for AR9 Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4235/
Diffstat (limited to 'arch/mips/lantiq')
-rw-r--r--arch/mips/lantiq/xway/sysctrl.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index befbb760ab76..67c3a91e54e7 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk)
{
unsigned int val = ltq_cgu_r32(ifccr);
/* set bus clock speed */
- if (of_machine_is_compatible("lantiq,ar9")) {
+ if (of_machine_is_compatible("lantiq,ar9") ||
+ of_machine_is_compatible("lantiq,vr9")) {
val &= ~0x1f00000;
if (clk->rate == CLOCK_33M)
val |= 0xe00000;