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authorJustin Swartz <justin.swartz@risingedge.co.za>2024-03-16 06:54:41 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2024-04-15 10:23:37 +0200
commitde56f781e5483fb3b3527aa280df2434f0cb2ace (patch)
tree30cbb15497fede68372e2d26ad237677c98d060e /arch/mips/boot
parentfdcb4f10723b5730842bc4419be635065f8e608b (diff)
mips: dts: ralink: mt7621: reorder pci?_phy attributes
Reorder the attributes of the PCIe PHY nodes node to match what the DTS style guide recommends. Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za> Reviewed-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/boot')
-rw-r--r--arch/mips/boot/dts/ralink/mt7621.dtsi8
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index aa06d12acacc..284811f32929 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -583,14 +583,18 @@
pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e149000 0x0700>;
- clocks = <&sysc MT7621_CLK_XTAL>;
+
#phy-cells = <1>;
+
+ clocks = <&sysc MT7621_CLK_XTAL>;
};
pcie2_phy: pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e14a000 0x0700>;
- clocks = <&sysc MT7621_CLK_XTAL>;
+
#phy-cells = <1>;
+
+ clocks = <&sysc MT7621_CLK_XTAL>;
};
};