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authorYuantian Tang <andy.tang@nxp.com>2017-11-22 09:40:53 +0800
committerStephen Boyd <sboyd@codeaurora.org>2017-12-21 15:57:28 -0800
commit36ab04671570fcd0e33868eba83f361d76c36bbf (patch)
tree545b657ecd4c004d8f3e1d63e4b1d76b696a7c2b
parent4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff)
clk: qoriq: add more divider clocks support
More divider clocks are needed by IP. So enlarge the PLL divider array to accommodate more divider clocks. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r--Documentation/devicetree/bindings/clock/qoriq-clock.txt1
-rw-r--r--drivers/clk/clk-qoriq.c9
2 files changed, 9 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 6498e1fdbb33..97f46adac85f 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -78,6 +78,7 @@ second cell is the clock index for the specified type.
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+ 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
5 coreclk must be 0
3. Example
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index b0ea753b8709..3a1812f65e5d 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -41,7 +41,7 @@ struct clockgen_pll_div {
};
struct clockgen_pll {
- struct clockgen_pll_div div[4];
+ struct clockgen_pll_div div[8];
};
#define CLKSEL_VALID 1
@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
struct clk *clk;
int ret;
+ /*
+ * For platform PLL, there are 8 divider clocks.
+ * For core PLL, there are 4 divider clocks at most.
+ */
+ if (idx != PLATFORM_PLL && i >= 4)
+ break;
+
snprintf(pll->div[i].name, sizeof(pll->div[i].name),
"cg-pll%d-div%d", idx, i + 1);