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ARM Mali Midgard GPU
====================
Required properties:
- compatible :
* Must contain one of the following:
+ "arm,mali-t604"
+ "arm,mali-t624"
+ "arm,mali-t628"
+ "arm,mali-t720"
+ "arm,mali-t760"
+ "arm,mali-t820"
+ "arm,mali-t830"
+ "arm,mali-t860"
+ "arm,mali-t880"
* which must be preceded by one of the following vendor specifics:
+ "allwinner,sun50i-h6-mali"
+ "amlogic,meson-gxm-mali"
+ "rockchip,rk3288-mali"
+ "rockchip,rk3399-mali"
- reg : Physical base address of the device and length of the register area.
- interrupts : Contains the three IRQ lines required by Mali Midgard devices.
- interrupt-names : Contains the names of IRQ resources in the order they were
provided in the interrupts property. Must contain: "job", "mmu", "gpu".
Optional properties:
- clocks : Phandle to clock for the Mali Midgard device.
- clock-names : Specify the names of the clocks specified in clocks
when multiple clocks are present.
* core: clock driving the GPU itself (When only one clock is present,
assume it's this clock.)
* bus: bus clock for the GPU
- mali-supply : Phandle to regulator for the Mali device. Refer to
Documentation/devicetree/bindings/regulator/regulator.txt for details.
- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
for details.
- #cooling-cells: Refer to Documentation/devicetree/bindings/thermal/thermal.txt
for details.
- resets : Phandle of the GPU reset line.
Vendor-specific bindings
------------------------
The Mali GPU is integrated very differently from one SoC to
another. In order to accommodate those differences, you have the option
to specify one more vendor-specific compatible, among:
- "allwinner,sun50i-h6-mali"
Required properties:
- clocks : phandles to core and bus clocks
- clock-names : must contain "core" and "bus"
- resets: phandle to GPU reset line
- "amlogic,meson-gxm-mali"
Required properties:
- resets : Should contain phandles of :
+ GPU reset line
+ GPU APB glue reset line
Example for a Mali-T760:
gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0xffa30000 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&cru ACLK_GPU>;
mali-supply = <&vdd_gpu>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power RK3288_PD_GPU>;
#cooling-cells = <2>;
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp@533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp@450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp@350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp@266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp@160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};
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