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path: root/drivers/cxl/cxl.h
AgeCommit message (Expand)AuthorFilesLines
2021-06-15cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams1-1/+11
2021-06-15cxl/pmem: Add initial infrastructure for pmem supportDan Williams1-0/+24
2021-06-15cxl/core: Add cxl-bus driver infrastructureDan Williams1-0/+22
2021-06-12cxl/hdm: Fix decoder count calculationBen Widawsky1-0/+7
2021-06-09cxl/acpi: Introduce cxl_decoder objectsDan Williams1-0/+63
2021-06-09cxl/acpi: Add downstream port data to cxl_port instancesDan Williams1-0/+21
2021-06-09cxl/acpi: Introduce the root of a cxl_port topologyDan Williams1-0/+31
2021-06-05cxl/pci: Add HDM decoder capabilitiesBen Widawsky1-6/+59
2021-06-05cxl/pci: Map registers based on capabilitiesIra Weiny1-5/+28
2021-05-14cxl/core: Refactor CXL register lookup for bridge reuseDan Williams1-0/+3
2021-05-14cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams1-0/+32
2021-05-14cxl/mem: Move some definitions to mem.hDan Williams1-57/+0
2021-02-16cxl/mem: Enable commands via CELBen Widawsky1-0/+2
2021-02-16cxl/mem: Register CXL memX devicesDan Williams1-0/+3
2021-02-16cxl/mem: Find device capabilitiesBen Widawsky1-0/+90