drm/drm-misc - Kernel DRM miscellaneous fixes and cross-tree changes

Age	Commit message (Expand)	Author	Files	Lines
2024-05-04	clk: rockchip: rk3568: Add PLL rate for 724 MHz	Lucas Stach	1	-0/+1
2024-05-04	clk: rockchip: Remove an unused field in struct rockchip_mmc_clock	Christophe JAILLET	1	-1/+0
2024-04-10	clk: rockchip: rk3588: Add reset line for HDMI Receiver	Shreeya Patel	1	-0/+1
2024-04-10	clk: rockchip: rk3568: Add missing USB480M_PHY mux	David Jander	1	-0/+4
2024-02-27	clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent	Ondrej Jirman	1	-3/+3
2024-02-27	clk: rockchip: rk3588: use linked clock ID for GATE_LINK	Sebastian Reichel	1	-23/+23
2024-02-27	clk: rockchip: rk3588: fix indent	Sebastian Reichel	1	-1/+1
2024-02-27	clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf	Sebastian Reichel	1	-6/+4
2024-02-27	Merge branch 'v6.9-shared/clkids' into v6.9-clk/next	Heiko Stuebner	3	-1/+23
2024-02-27	clk: rockchip: rk3588: fix CLK_NR_CLKS usage	Sebastian Reichel	3	-1/+23
2024-01-25	clk: rockchip: rk3568: Add PLL rate for 128MHz	Chris Morgan	1	-0/+1
2024-01-12	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	1	-0/+3
2023-12-05	clk: rockchip: rk3568: Mark pclk_usb as critical	Chris Morgan	1	-0/+1
2023-12-05	clk: rockchip: rk3568: Add PLL rate for 126.4MHz	Chris Morgan	1	-0/+1
2023-11-28	clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name	Alex Bee	1	-1/+1
2023-11-28	clk: rockchip: rk3128: Fix aclk_peri_src's parent	Finley Xiao	1	-13/+7
2023-11-16	clk: rockchip: rk3128: Fix HCLK_OTG gate register	Weihao Li	1	-1/+1
2023-11-16	clk: rockchip: rk3568: Add PLL rate for 292.5MHz	Chris Morgan	1	-0/+1
2023-11-16	clk: rockchip: rk3568: Add PLL rate for 115.2MHz	Chris Morgan	1	-0/+1
2023-10-23	clk: Use device_get_match_data()	Rob Herring	1	-7/+2
2023-08-30	Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...	Stephen Boyd	2	-1/+61
2023-08-10	clk: rockchip: rv1126: Add PD_VO clock tree	Jagan Teki	1	-0/+59
2023-07-19	clk: Explicitly include correct DT includes	Rob Herring	2	-2/+2
2023-07-10	clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz	Alibek Omarov	1	-1/+1
2023-07-10	clk: rockchip: rk3568: Add PLL rate for 101MHz	Alibek Omarov	1	-0/+1
2023-04-25	Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into cl...	Stephen Boyd	2	-17/+27
2023-04-18	clk: rockchip: rk3588: make gate linked clocks critical	Sebastian Reichel	1	-16/+26
2023-04-05	clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_div...	Christophe JAILLET	1	-2/+0
2023-03-07	clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent	Quentin Schulz	1	-1/+1
2022-12-12	Merge branches 'clk-spear', 'clk-fract', 'clk-rockchip' and 'clk-imx' into cl...	Stephen Boyd	9	-35/+3795
2022-11-23	clk: rockchip: Fix memory leak in rockchip_clk_register_pll()	Xiu Jianfeng	1	-0/+1
2022-11-22	clk: Remove a useless include	Christophe JAILLET	1	-1/+0
2022-11-15	clk: rockchip: add clock controller for the RK3588	Elaine Zhang	5	-1/+3447
2022-11-14	clk: rockchip: add lookup table support	Sebastian Reichel	2	-15/+40
2022-11-14	clk: rockchip: simplify rockchip_clk_add_lookup	Sebastian Reichel	2	-10/+6
2022-11-14	clk: rockchip: allow additional mux options for cpu-clock frequency changes	Elaine Zhang	2	-0/+43
2022-11-14	clk: rockchip: add pll type for RK3588	Elaine Zhang	2	-1/+235
2022-11-14	clk: rockchip: add register offset of the cores select parent	Elaine Zhang	2	-8/+23
2022-09-23	clk: rockchip: Add clock controller support for RV1126 SoC	Jagan Teki	4	-0/+1165
2022-09-13	clk: rockchip: Add MUXTBL variant	Elaine Zhang	2	-6/+38
2022-05-03	clk: rockchip: Mark hclk_vo as critical on rk3568	Sascha Hauer	1	-0/+1
2022-02-24	clk: rockchip: re-add rational best approximation algorithm to the fractional...	Quentin Schulz	1	-0/+3
2022-02-23	clk/rockchip: Use of_device_get_match_data()	Minghao Chi (CGEL ZTE)	1	-4/+2
2022-02-08	clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568	Sascha Hauer	1	-1/+1
2022-02-08	clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568	Sascha Hauer	1	-3/+3
2022-02-08	clk: rockchip: Add more PLL rates for rk3568	Sascha Hauer	1	-0/+6
2021-11-02	clk: rockchip: drop module parts from rk3399 and rk3568 drivers	Heiko Stuebner	3	-10/+2
2021-11-02	Revert "clk: rockchip: use module_platform_driver_probe"	Heiko Stuebner	2	-2/+2
2021-09-21	clk: rockchip: use module_platform_driver_probe	Miles Chen	2	-2/+2
2021-09-20	clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L}	Brian Norris	1	-2/+2