drm/drm-misc - Kernel DRM miscellaneous fixes and cross-tree changes

Age	Commit message (Expand)	Author	Files	Lines
2022-09-18	clk: renesas: r8a779g0: Add EtherAVB clocks	Geert Uytterhoeven	1	-0/+3
2022-09-18	clk: renesas: r8a779g0: Add PFC/GPIO clocks	Geert Uytterhoeven	1	-0/+4
2022-09-18	clk: renesas: r8a779g0: Add I2C clocks	Geert Uytterhoeven	1	-0/+6
2022-09-18	clk: renesas: r8a779g0: Add watchdog clock	Geert Uytterhoeven	1	-0/+1
2022-08-29	clk: renesas: r8a779f0: Add MSIOF clocks	Wolfram Sang	1	-0/+4
2022-08-29	clk: renesas: r9a09g011: Add IIC clock and reset entries	Phil Edworthy	1	-0/+4
2022-08-22	clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info	Biju Das	1	-0/+2
2022-08-22	clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks	Wolfram Sang	1	-0/+10
2022-08-15	clk: renesas: r8a779f0: Add CMT clocks	Wolfram Sang	1	-0/+4
2022-08-15	clk: renesas: r8a779f0: Add SDH0 clock	Wolfram Sang	1	-1/+2
2022-07-05	clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config	Andi Kleen	1	-1/+1
2022-07-05	clk: renesas: r9a07g043: Add support for RZ/Five SoC	Lad Prabhakar	1	-0/+32
2022-06-17	clk: renesas: r8a779f0: Add HSCIF clocks	Wolfram Sang	1	-0/+4
2022-06-17	clk: renesas: r8a779f0: Add PCIe clocks	Yoshihiro Shimoda	1	-0/+2
2022-06-17	clk: renesas: r8a779f0: Add Z0 and Z1 clock support	Geert Uytterhoeven	1	-0/+2
2022-06-13	clk: renesas: rza1: Remove struct rz_cpg	Geert Uytterhoeven	1	-18/+15
2022-06-13	clk: renesas: r8a7779: Remove struct r8a7779_cpg	Geert Uytterhoeven	1	-18/+9
2022-06-13	clk: renesas: r8a7778: Remove struct r8a7778_cpg	Geert Uytterhoeven	1	-22/+9
2022-06-13	clk: renesas: sh73a0: Remove sh73a0_cpg.reg	Geert Uytterhoeven	1	-13/+13
2022-06-13	clk: renesas: r8a7740: Remove r8a7740_cpg.reg	Geert Uytterhoeven	1	-10/+10
2022-06-13	clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg	Geert Uytterhoeven	1	-11/+11
2022-06-13	clk: renesas: r8a779f0: Add SDHI0 clock	Wolfram Sang	1	-0/+1
2022-06-13	clk: renesas: r8a779f0: Add thermal clock	Wolfram Sang	1	-0/+1
2022-06-07	clk: renesas: rzg2l: Fix reset status function	Biju Das	1	-1/+1
2022-06-06	clk: renesas: r9a06g032: Fix UART clkgrp bitsel	Ralph Siemsen	1	-4/+4
2022-06-06	clk: renesas: r9a06g032: Drop some unused fields	Ralph Siemsen	1	-13/+11
2022-06-06	clk: renesas: r9a09g011: Add WDT clock and reset entries	Phil Edworthy	1	-0/+3
2022-06-06	clk: renesas: r9a09g011: Add PFC clock and reset entries	Phil Edworthy	1	-0/+2
2022-06-06	clk: renesas: r9a07g044: Add POEG clock and reset entries	Biju Das	1	-1/+13
2022-06-06	clk: renesas: r9a07g044: Add GPT clock and reset entry	Biju Das	1	-1/+4
2022-05-29	Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	1	-1/+39
2022-05-19	clk: renesas: r9a06g032: Probe possible children	Miquel Raynal	1	-0/+5
2022-05-19	clk: renesas: r9a06g032: Export function to set dmamux	Miquel Raynal	1	-1/+34
2022-05-06	clk: renesas: r9a09g011: Add eth clock and reset entries	Phil Edworthy	1	-5/+9
2022-05-06	clk: renesas: Add RZ/V2M support using the rzg2l driver	Phil Edworthy	5	-0/+181
2022-05-05	clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg	Phil Edworthy	2	-3/+17
2022-05-05	clk: renesas: rzg2l: Make use of CLK_MON registers optional	Phil Edworthy	4	-1/+16
2022-05-05	clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers	Phil Edworthy	3	-31/+19
2022-05-05	clk: renesas: rzg2l: Add read only versions of the clk macros	Phil Edworthy	3	-6/+12
2022-05-05	clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro	Phil Edworthy	3	-22/+19
2022-05-05	clk: renesas: r9a07g044: Fix OSTM1 module clock name	Geert Uytterhoeven	1	-1/+1
2022-05-05	clk: renesas: r9a07g043: Add clock and reset entries for ADC	Biju Das	1	-0/+6
2022-05-05	clk: renesas: r9a07g043: Add TSU clock and reset entry	Biju Das	1	-0/+6
2022-05-05	clk: renesas: r9a07g043: Add RSPI clock and reset entries	Biju Das	1	-0/+9
2022-05-05	clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...	Biju Das	1	-0/+18
2022-05-05	clk: renesas: r9a07g044: Add DSI clock and reset entries	Biju Das	1	-1/+16
2022-05-05	clk: renesas: r9a07g044: Add LCDC clock and reset entries	Biju Das	1	-1/+8
2022-05-05	clk: renesas: r9a07g044: Add M4 Clock support	Biju Das	1	-1/+18
2022-05-05	clk: renesas: r9a07g044: Add M3 Clock support	Biju Das	1	-1/+4
2022-05-05	clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support	Biju Das	1	-1/+4