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path: root/drivers/clk/meson
AgeCommit message (Expand)AuthorFilesLines
2024-05-03clk: meson: s4: fix module autoloadingKrzysztof Kozlowski2-0/+2
2024-04-10clk: meson: fix module license to GPL onlyNeil Armstrong18-18/+18
2024-04-10clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCFNeil Armstrong2-20/+57
2024-04-10clk: meson: add vclk driverNeil Armstrong4-0/+197
2024-03-29clk: meson: pll: print out pll name when unable to lock itDmitry Rokosov1-2/+2
2024-03-29clk: meson: s4: pll: determine maximum register in regmap configDmitry Rokosov1-0/+1
2024-03-29clk: meson: s4: peripherals: determine maximum register in regmap configDmitry Rokosov1-0/+1
2024-03-29clk: meson: a1: pll: determine maximum register in regmap configDmitry Rokosov1-0/+1
2024-03-29clk: meson: a1: peripherals: determine maximum register in regmap configDmitry Rokosov1-0/+1
2024-02-05clk: meson: Add missing clocks to axg_clk_regmapsIgor Prusov1-0/+2
2023-11-24clk: meson: g12a: add CSI & ISP gates clocksNeil Armstrong1-0/+9
2023-11-24clk: meson: g12a: add MIPI ISP clocksNeil Armstrong2-0/+67
2023-11-24clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocksNeil Armstrong1-0/+40
2023-10-23clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILSArnd Bergmann1-0/+2
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controllerYu Tu4-0/+3881
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC PLL clock driverYu Tu4-0/+918
2023-08-30Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds28-3287/+2727
2023-08-30Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd28-3279/+2719
2023-08-08clk: meson: axg-audio: move bindings include to main driverNeil Armstrong2-3/+2
2023-08-08clk: meson: meson8b: move bindings include to main driverNeil Armstrong2-7/+3
2023-08-08clk: meson: a1: move bindings include to main driverNeil Armstrong4-6/+4
2023-08-08clk: meson: eeclk: move bindings include to main driverNeil Armstrong6-9/+6
2023-08-08clk: meson: aoclk: move bindings include to main driverNeil Armstrong6-45/+9
2023-08-08dt-bindings: clk: axg-audio-clkc: expose all clock idsNeil Armstrong1-70/+0
2023-08-08dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock idsNeil Armstrong1-15/+0
2023-08-08dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock idsNeil Armstrong1-63/+0
2023-08-08dt-bindings: clk: meson8b-clkc: expose all clock idsNeil Armstrong1-108/+0
2023-08-08dt-bindings: clk: g12a-aoclkc: expose all clock idsNeil Armstrong1-17/+0
2023-08-08dt-bindings: clk: g12a-clks: expose all clock idsNeil Armstrong1-140/+0
2023-08-08dt-bindings: clk: axg-clkc: expose all clock idsNeil Armstrong1-58/+0
2023-08-08dt-bindings: clk: gxbb-clkc: expose all clock idsNeil Armstrong1-76/+0
2023-08-08clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKSNeil Armstrong3-428/+424
2023-08-08clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKSNeil Armstrong3-658/+660
2023-08-08clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKSNeil Armstrong5-180/+183
2023-08-08clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong9-73/+68
2023-08-08clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong9-1323/+1312
2023-08-08clk: meson: introduce meson-clkc-utilsNeil Armstrong4-0/+48
2023-07-19clk: Explicitly include correct DT includesRob Herring8-8/+8
2023-07-11clk: meson: change usleep_range() to udelay() for atomic contextDmitry Rokosov1-2/+2
2023-06-15clk: meson: pll: remove unneeded semicolonJiapeng Chong1-1/+1
2023-06-12clk: meson: a1: Staticize rtc clkStephen Boyd1-1/+1
2023-05-30clk: meson: a1: add Amlogic A1 Peripherals clock controller driverDmitry Rokosov4-0/+2367
2023-05-30clk: meson: a1: add Amlogic A1 PLL clock controller driverDmitry Rokosov4-0/+414
2023-05-30clk: meson: introduce new pll power-on sequence for A1 SoC familyDmitry Rokosov2-0/+25
2023-05-30clk: meson: make pll rst bit as optionalDmitry Rokosov1-7/+17
2023-01-13clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rateMartin Blumenstingl1-5/+4
2023-01-13clk: meson: sclk-div: switch from .round_rate to .determine_rateMartin Blumenstingl1-5/+6
2023-01-13clk: meson: dualdiv: switch from .round_rate to .determine_rateMartin Blumenstingl1-8/+13
2023-01-13clk: meson: mpll: Switch from .round_rate to .determine_rateMartin Blumenstingl1-7/+13
2022-12-12Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' ...Stephen Boyd1-8/+12