drm/drm-misc - Kernel DRM miscellaneous fixes and cross-tree changes

Age	Commit message (Expand)	Author	Files	Lines
2023-11-08	Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	1	-27/+29
2023-10-27	riscv: Use separate IRQ shadow call stacks	Sami Tolvanen	1	-0/+21
2023-10-27	riscv: Deduplicate IRQ stack switching	Sami Tolvanen	1	-27/+8
2023-10-12	RISC-V: Fix wrong use of CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK	Jiexun Wang	1	-2/+2
2023-08-16	riscv: stack: Fixup independent softirq stack for CONFIG_FRAME_POINTER=n	Guo Ren	1	-0/+3
2023-06-22	riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACK	Guo Ren	1	-0/+35
2023-06-22	riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACK	Guo Ren	1	-0/+33
2023-04-08	RISC-V: Treat IPIs as normal Linux IRQs	Anup Patel	1	-1/+2
2023-04-08	irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode	Anup Patel	1	-0/+18
2020-06-09	RISC-V: Remove do_IRQ() function	Anup Patel	1	-6/+0
2020-06-09	irqchip: RISC-V per-HART local interrupt controller driver	Anup Patel	1	-30/+3
2020-06-09	RISC-V: self-contained IPI handling routine	Anup Patel	1	-6/+10
2020-01-04	riscv: prefix IRQ_ macro names with an RV_ namespace	Paul Walmsley	1	-3/+3
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	1	-12/+5
2019-10-28	riscv: for C functions called only from assembly, mark with __visible	Paul Walmsley	1	-1/+1
2019-05-16	RISC-V: Add interrupt related SCAUSE defines in asm/csr.h	Anup Patel	1	-12/+4
2019-04-25	riscv: print the unexpected interrupt cause	Christoph Hellwig	1	-1/+2
2018-10-22	RISC-V: Show IPI stats	Anup Patel	1	-0/+8
2018-10-22	RISC-V: No need to pass scause as arg to do_IRQ()	Anup Patel	1	-2/+2
2018-08-13	clocksource: new RISC-V SBI timer driver	Palmer Dabbelt	1	-0/+3
2018-08-13	RISC-V: implement low-level interrupt handling	Christoph Hellwig	1	-9/+43
2018-07-04	RISC-V: Don't include irq-riscv-intc.h	Palmer Dabbelt	1	-4/+0
2018-03-14	RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler	Palmer Dabbelt	1	-13/+0
2017-09-26	RISC-V: Init and Halt Code	Palmer Dabbelt	1	-0/+39