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path: root/arch/arc/include/asm/arcregs.h
AgeCommit message (Expand)AuthorFilesLines
2019-02-25ARC: boot log: cut down on verbosityVineet Gupta1-9/+0
2019-02-25ARCv2: boot log: refurbish HS core/release identificationVineet Gupta1-1/+1
2019-02-25ARCv2: Add explcit unaligned access support (and ability to disable too)Eugeniy Paltsev1-0/+1
2019-02-21ARCv2: don't assume core 0x54 has dual issueVineet Gupta1-0/+8
2019-01-17ARC: boot log: print Action point detailsVineet Gupta1-1/+9
2019-01-17ARCv2: boot log: BPU return stack depthVineet Gupta1-1/+1
2017-11-13ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop BufferVineet Gupta1-1/+32
2017-10-03ARCv2: boot log: identify HS48 cores (dual issue)Vineet Gupta1-1/+2
2017-10-03ARC: boot log: decontaminate ARCv2 ISA_CONFIG registerVineet Gupta1-4/+4
2017-02-06ARCv2: intc: Use ARC_REG_STATUS32 for addressing STATUS32 regYuriy Kolerov1-0/+3
2016-12-19ARC: mm: No need to save cache version in @cpuinfoVineet Gupta1-1/+1
2016-11-30ARC: breakout timer include code into separate header ...Vineet Gupta1-8/+1
2016-11-30ARC: breakout aux handling into a separate headerVineet Gupta1-84/+1
2016-11-07ARC: change return value of userspace cmpxchg assist syscallVineet Gupta1-0/+2
2016-10-28ARC: boot log: refactor cpu name/release printingVineet Gupta1-1/+1
2016-10-28ARC: boot log: don't assume SWAPE instruction supportVineet Gupta1-1/+1
2016-10-28ARC: boot log: refactor printing abt features not captured in BCRsVineet Gupta1-0/+1
2016-09-30ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 coresVineet Gupta1-9/+1
2016-03-12ARC: build: Better way to detect ISA compatible toolchainVineet Gupta1-6/+0
2016-02-18ARCv2: boot report CCMs (Closely Coupled Memories)Vineet Gupta1-12/+20
2016-01-29ARC: shrink cpuinfo by not saving full timer BCRVineet Gupta1-2/+1
2015-10-17ARC: boot log: decode more mmu config itemsVineet Gupta1-1/+1
2015-10-17ARC: mm: compute TLB size as needed from ways * setsVineet Gupta1-2/+2
2015-10-17ARC: make write_aux_reg safer against macro substitutionVineet Gupta1-1/+1
2015-08-20ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin1-0/+1
2015-08-03ARCv2: Fix the peripheral address space detectionVineet Gupta1-4/+3
2015-06-22ARCv2: MMUv4: cache programming model changesVineet Gupta1-2/+3
2015-06-22ARCv2: MMUv4: TLB programming Model changesVineet Gupta1-1/+1
2015-06-22ARCv2: Support for ARCv2 ISA and HS38x coresVineet Gupta1-4/+49
2015-06-22ARCv2: [intc] HS38 core interrupt controllerVineet Gupta1-0/+1
2015-06-22ARC: uncached base is hard constant for ARC, don't save itVineet Gupta1-1/+0
2015-06-19ARC: entry.S: Introduce INTERRUPT_{PROLOGUE,EPILOGUE}Vineet Gupta1-3/+0
2015-06-19ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)Vineet Gupta1-1/+2
2015-04-13ARC: Fix RTT boot printingVineet Gupta1-0/+1
2015-04-13ARC: cosmetic: Remove unused ECR bitfield masksVineet Gupta1-6/+3
2015-04-13ARC: Fix WRITE_BCRVineet Gupta1-2/+2
2014-10-13ARC: boot: cpu feature print enhancementsVineet Gupta1-24/+53
2014-10-13ARC: unbork FPU save/restoreVineet Gupta1-8/+0
2014-10-13ARC: remove extraneous __KERNEL__ guardsVineet Gupta1-4/+0
2014-07-23ARC: cache boot reporting updatesVineet Gupta1-1/+1
2013-06-26ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth valuesVineet Gupta1-0/+4
2013-06-22ARC: Entry Handler tweaks: Avoid hardcoded LIMMS for ECR valuesVineet Gupta1-0/+5
2013-06-22ARC: cache detection code bitrotVineet Gupta1-1/+1
2013-06-22ARC: Disintegrate arcregs.hVineet Gupta1-116/+0
2013-02-15ARC: Boot #2: Verbose Boot reporting / feature verificationVineet Gupta1-10/+112
2013-02-15ARC: Boot #1: low-level, setup_arch(), /proc/cpuinfo, mem initVineet Gupta1-0/+5
2013-02-15ARC: MMU Exception HandlingVineet Gupta1-0/+91
2013-02-15ARC: MMU Context ManagementVineet Gupta1-0/+7
2013-02-15ARC: Cache Flush ManagementVineet Gupta1-0/+80
2013-02-11ARC: Timers/counters/delay managementVineet Gupta1-0/+11
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