diff options
| author | Nicolin Chen <nicoleotsuka@gmail.com> | 2015-03-04 21:05:04 -0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-03-05 12:23:29 +0000 |
| commit | 6c8ca30eec7b6f8eb09c957e8dcced89e5f100c7 (patch) | |
| tree | 9ba443b8cc08266aa667f5acf1f7db6b21fb335e /sound/soc/fsl | |
| parent | 90aff15b3e0858eaefdcd390e64849542845d489 (diff) | |
ASoC: fsl_ssi: Don't try to round-up for PM divisor calculation
According to i.MX6 Series Reference Manual, the formula to calculate
the sys clock is
sysclk rate = bclk rate * (div2 + 1) * (7 * psr + 1) * (pm + 1) * 2
Commit aafa85e71a75 ("ASoC: fsl_ssi: Add DAI master mode support for
SSI on i.MX series") added the divisor calculation which relies on
the clk_round_rate(). However, at that time, clk_round_rate() didn't
provide closest clock rates for some cases because it might not use
a correct rounding policy. So using the original formula (pm + 1) for
PM divisor was not able to give us a desired clock rate. And then we
used (pm + 2) to do the trick.
However, the clk-divider driver has been refined a lot since commit
b11d282dbea2 ("clk: divider: fix rate calculation for fractional rates")
Now using (pm + 2) trick would result an incorrect clock rate.
So this patch fixes the problem by removing the useless trick.
Reported-by: Stephane Cerveau <scerveau@voxtok.com>
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/fsl')
| -rw-r--r-- | sound/soc/fsl/fsl_ssi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 134388f7d1b8..7eebc0889c9d 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -603,7 +603,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, factor = (div2 + 1) * (7 * psr + 1) * 2; for (i = 0; i < 255; i++) { - tmprate = freq * factor * (i + 2); + tmprate = freq * factor * (i + 1); if (baudclk_is_used) clkrate = clk_get_rate(ssi_private->baudclk); |