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authorPeter De Schrijver <pdeschrijver@nvidia.com>2017-02-23 12:44:39 +0200
committerThierry Reding <treding@nvidia.com>2017-03-20 14:04:45 +0100
commit34ac2c278b306cc3006dd5cbfaff4ec52065bf6f (patch)
tree1cac5e108c4f0c050fa796ed682777126beab16c /samples/kprobes
parent9326947f2215e1816a9133b0b47e4c9200552777 (diff)
clk: tegra: Fix ISP clock modelling
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model this as 1 mux/divider clock and child gate clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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