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| author | Herve Codina <herve.codina@bootlin.com> | 2024-08-08 09:11:00 +0200 |
|---|---|---|
| committer | Christophe Leroy <christophe.leroy@csgroup.eu> | 2024-09-03 07:49:18 +0200 |
| commit | a0bbe77fafbc7e5eb41fbf3dc5cdb3608d8778a3 (patch) | |
| tree | 38919a8e688878c5b25288b3f5293c8644d8578d /kernel/trace | |
| parent | a68757abc0d5df7142720d030276f9693e4958af (diff) | |
dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) TSA controller
Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM TSA, this QE TSA can handle
up to 4 TDMs instead of 2 and allows to configure the logic level of
sync signals.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-8-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Diffstat (limited to 'kernel/trace')
0 files changed, 0 insertions, 0 deletions