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authorSascha Hauer <s.hauer@pengutronix.de>2022-04-14 18:22:39 +0200
committerMark Brown <broonie@kernel.org>2022-04-19 12:06:20 +0100
commit824a0a02cd74776461aaa30d792b1ed9111c9aa5 (patch)
tree94dce22588b75d02997021177c3c81eaa4927f51 /include/linux/dma
parent625d8936c3378016ec8c480a00432034bcb813c9 (diff)
dmaengine: imx-sdma: Add multi fifo support
The i.MX SDMA engine can read from / write to multiple successive hardware FIFO registers, referred to as "Multi FIFO support". This is needed for the micfil driver and certain configurations of the SAI driver. This patch adds support for this feature. The number of FIFOs to read from / write to must be communicated from the client driver to the SDMA engine. For this the struct dma_slave_config::peripheral_config field is used. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-By: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220414162249.3934543-12-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux/dma')
-rw-r--r--include/linux/dma/imx-dma.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/include/linux/dma/imx-dma.h b/include/linux/dma/imx-dma.h
index b06cba85a6d4..8887762360d4 100644
--- a/include/linux/dma/imx-dma.h
+++ b/include/linux/dma/imx-dma.h
@@ -39,6 +39,7 @@ enum sdma_peripheral_type {
IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
IMX_DMATYPE_ASRC_SP, /* Shared ASRC */
IMX_DMATYPE_SAI, /* SAI */
+ IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */
};
enum imx_dma_prio {
@@ -65,4 +66,23 @@ static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
!strcmp(chan->device->dev->driver->name, "imx-dma");
}
+/**
+ * struct sdma_peripheral_config - SDMA config for audio
+ * @n_fifos_src: Number of FIFOs for recording
+ * @n_fifos_dst: Number of FIFOs for playback
+ * @sw_done: Use software done. Needed for PDM (micfil)
+ *
+ * Some i.MX Audio devices (SAI, micfil) have multiple successive FIFO
+ * registers. For multichannel recording/playback the SAI/micfil have
+ * one FIFO register per channel and the SDMA engine has to read/write
+ * the next channel from/to the next register and wrap around to the
+ * first register when all channels are handled. The number of active
+ * channels must be communicated to the SDMA engine using this struct.
+ */
+struct sdma_peripheral_config {
+ int n_fifos_src;
+ int n_fifos_dst;
+ bool sw_done;
+};
+
#endif /* __LINUX_DMA_IMX_H */