diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2023-01-30 16:08:36 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2023-01-30 16:08:36 +0100 |
| commit | 75dae633c9c0c8d106e97bcf17bec79f652feb2c (patch) | |
| tree | df078f9e7a6e83762ace244a035cd487891691e5 /include/dt-bindings | |
| parent | 0d01e09022c558c54fa2d5fb7fe7e32b7a9a8554 (diff) | |
| parent | f3460326e38d6a084fb5b3348125a802567a3690 (diff) | |
Merge tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V SoC drivers for v6.3-mw0
It's all StarFive stuff this time:
Their new JH7110 SoC uses a SiFive core complex, and therefore a
SiFive cache controller too. That needed a compatible added to both the
binding and driver.
The JH7110 also has power domains, which are supported by a new driver
and a corresponding dt-binding.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
soc: starfive: Add StarFive JH71XX pmu driver
dt-bindings: power: Add starfive,jh7110-pmu
soc: sifive: ccache: Add StarFive JH7110 support
dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
Link: https://lore.kernel.org/r/Y9LNIm9pkr+Owv/e@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/power/starfive,jh7110-pmu.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h new file mode 100644 index 000000000000..132bfe401fc8 --- /dev/null +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Walker Chen <walker.chen@starfivetech.com> + */ +#ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__ +#define __DT_BINDINGS_POWER_JH7110_POWER_H__ + +#define JH7110_PD_SYSTOP 0 +#define JH7110_PD_CPU 1 +#define JH7110_PD_GPUA 2 +#define JH7110_PD_VDEC 3 +#define JH7110_PD_VOUT 4 +#define JH7110_PD_ISP 5 +#define JH7110_PD_VENC 6 + +#endif |