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authorLinus Torvalds <torvalds@linux-foundation.org>2020-12-16 15:02:49 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2020-12-16 15:02:49 -0800
commitf68e4041ef63f03091e44b4eebf1ab5c5d427e6f (patch)
tree9ff864e69caf508408f98fefedb15a5098910587 /drivers
parenta701262c02cec71dc29b10fe910ba3c2298f5ba3 (diff)
parent3df09cb8c92e2bdfb78c81f678f6990bd780f09a (diff)
Merge tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.11 kernel. Drivers, drivers and drivers. Not a single core change. Some new stuff, especially a bunch of new Intel, Qualcomm and Ocelot SoCs. As part of the modularization attempt, I applied one patch affecting the firmware subsystem as a functional (not syntactic/semantic) dependency and then it blew up in our face, so I had to revert it, bummer. It will come in later, through that subsystem, I guess. New drivers: - New driver for the Microchip Serial GPIO "SGPIO". - Qualcomm SM8250 LPASS (Low Power Audio Subsystem) GPIO driver. New subdrivers: - Intel Lakefield subdriver. - Intel Elkhart Lake subdriver. - Intel Alder Lake-S subdriver. - Qualcomm MSM8953 subdriver. - Qualcomm SDX55 subdriver. - Qualcomm SDX55 PMIC subdriver. - Ocelot Luton SoC subdriver. - Ocelot Serval SoC subdriver. Modularization: - The Meson driver can now be built as modules. - The Qualcomm driver(s) can now be built as modules. Incremental improvements: - The Intel driver now supports pin configuration for GPIO-related configurations. - A bunch of Renesas PFC drivers have been augmented with support for QSPI pins, groups and functions. - Non-critical fixes to the irq handling in the Allwinner Sunxi driver" * tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits) pinctrl/spear: simplify the return expression of spear300_pinctrl_probe() pinctrl: mediatek: simplify the return expression of mtk_pinconf_bias_disable_set_rev1() dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5) pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings pinctrl: qcom-pmic-gpio: Add support for pmx55 dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx55 support pinctrl: pinctrl-microchip-sgpio: Mark some symbols with static keyword pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error pinctrl: mtk: Fix low level output voltage issue pinctrl: falcon: add missing put_device() call in pinctrl_falcon_probe() pinctrl: actions: pinctrl-s500: Constify s500_padinfo[] pinctrl: pinctrl-microchip-sgpio: Add OF config dependency pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver pinctrl: at91-pio4: add support for fewer lines on last PIO bank pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pinctrl/Kconfig20
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/actions/pinctrl-s500.c2
-rw-r--r--drivers/pinctrl/core.c2
-rw-r--r--drivers/pinctrl/freescale/Kconfig7
-rw-r--r--drivers/pinctrl/freescale/Makefile1
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx21.c330
-rw-r--r--drivers/pinctrl/intel/Kconfig25
-rw-r--r--drivers/pinctrl/intel/Makefile3
-rw-r--r--drivers/pinctrl/intel/pinctrl-alderlake.c437
-rw-r--r--drivers/pinctrl/intel/pinctrl-elkhartlake.c513
-rw-r--r--drivers/pinctrl/intel/pinctrl-lakefield.c375
-rw-r--r--drivers/pinctrl/intel/pinctrl-lynxpoint.c10
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt7622.c13
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c10
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-paris.c8
-rw-r--r--drivers/pinctrl/meson/Kconfig17
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-a1.c4
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c3
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-axg.c4
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-g12a.c4
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-gxbb.c4
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-gxl.c4
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.c8
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.h1
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8-pmx.c2
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c10
-rw-r--r--drivers/pinctrl/pinctrl-amd.c43
-rw-r--r--drivers/pinctrl/pinctrl-at91-pio4.c22
-rw-r--r--drivers/pinctrl/pinctrl-falcon.c14
-rw-r--r--drivers/pinctrl/pinctrl-ingenic.c1267
-rw-r--r--drivers/pinctrl/pinctrl-microchip-sgpio.c892
-rw-r--r--drivers/pinctrl/pinctrl-ocelot.c186
-rw-r--r--drivers/pinctrl/qcom/Kconfig88
-rw-r--r--drivers/pinctrl/qcom/Makefile4
-rw-r--r--drivers/pinctrl/qcom/pinctrl-lpass-lpi.c695
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8953.c1844
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sc7280.c1495
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sdx55.c1018
-rw-r--r--drivers/pinctrl/qcom/pinctrl-spmi-gpio.c2
-rw-r--r--drivers/pinctrl/renesas/core.c2
-rw-r--r--drivers/pinctrl/renesas/core.h4
-rw-r--r--drivers/pinctrl/renesas/gpio.c2
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a7778.c55
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a7790.c146
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a7791.c18
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a77950.c45
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a77951.c134
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a7796.c132
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a77965.c132
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a77990.c132
-rw-r--r--drivers/pinctrl/renesas/pfc-sh73a0.c2
-rw-r--r--drivers/pinctrl/renesas/pinctrl-rza1.c1
-rw-r--r--drivers/pinctrl/renesas/pinctrl.c68
-rw-r--r--drivers/pinctrl/renesas/sh_pfc.h12
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c24xx.c5
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear300.c8
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c9
60 files changed, 8759 insertions, 1540 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 453acce3d0c3..d4b2f2e2ed75 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -82,6 +82,7 @@ config PINCTRL_AT91
config PINCTRL_AT91PIO4
bool "AT91 PIO4 pinctrl driver"
depends on OF
+ depends on HAS_IOMEM
depends on ARCH_AT91 || COMPILE_TEST
select PINMUX
select GENERIC_PINCONF
@@ -374,6 +375,25 @@ config PINCTRL_OCELOT
select OF_GPIO
select REGMAP_MMIO
+config PINCTRL_MICROCHIP_SGPIO
+ bool "Pinctrl driver for Microsemi/Microchip Serial GPIO"
+ depends on OF
+ depends on HAS_IOMEM
+ select GPIOLIB
+ select GPIOLIB_IRQCHIP
+ select GENERIC_PINCONF
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select OF_GPIO
+ help
+ Support for the serial GPIO interface used on Microsemi and
+ Microchip SoC's. By using a serial interface, the SIO
+ controller significantly extends the number of available
+ GPIOs with a minimum number of additional pins on the
+ device. The primary purpose of the SIO controller is to
+ connect control signals from SFP modules and to act as an
+ LED controller.
+
source "drivers/pinctrl/actions/Kconfig"
source "drivers/pinctrl/aspeed/Kconfig"
source "drivers/pinctrl/bcm/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 3cdb6529db95..5bb9bb6cc3ce 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
+obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
obj-y += actions/
diff --git a/drivers/pinctrl/actions/pinctrl-s500.c b/drivers/pinctrl/actions/pinctrl-s500.c
index 38e30914af6e..ced778079b76 100644
--- a/drivers/pinctrl/actions/pinctrl-s500.c
+++ b/drivers/pinctrl/actions/pinctrl-s500.c
@@ -1485,7 +1485,7 @@ static PAD_PULLCTL_CONF(DNAND_D6, 2, 2, 1);
static PAD_PULLCTL_CONF(DNAND_D7, 2, 2, 1);
/* Pad info table */
-static struct owl_padinfo s500_padinfo[NUM_PADS] = {
+static const struct owl_padinfo s500_padinfo[NUM_PADS] = {
[DNAND_DQS] = PAD_INFO_PULLCTL(DNAND_DQS),
[DNAND_DQSN] = PAD_INFO_PULLCTL(DNAND_DQSN),
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 3663d87f51a0..9fc4433fece4 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -1602,9 +1602,11 @@ static int pinctrl_pins_show(struct seq_file *s, void *what)
struct pinctrl_dev *pctldev = s->private;
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
unsigned i, pin;
+#ifdef CONFIG_GPIOLIB
struct pinctrl_gpio_range *range;
unsigned int gpio_num;
struct gpio_chip *chip;
+#endif
seq_printf(s, "registered pins: %d\n", pctldev->desc->npins);
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index a1fbb3b9ae34..f294336430cc 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -24,13 +24,6 @@ config PINCTRL_IMX1
help
Say Y here to enable the imx1 pinctrl driver
-config PINCTRL_IMX21
- bool "i.MX21 pinctrl driver"
- depends on SOC_IMX21
- select PINCTRL_IMX1_CORE
- help
- Say Y here to enable the i.MX21 pinctrl driver
-
config PINCTRL_IMX27
bool "IMX27 pinctrl driver"
depends on SOC_IMX27
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index c61722565289..e476cb671037 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -4,7 +4,6 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
-obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx21.c b/drivers/pinctrl/freescale/pinctrl-imx21.c
deleted file mode 100644
index 8a102275a053..000000000000
--- a/drivers/pinctrl/freescale/pinctrl-imx21.c
+++ /dev/null
@@ -1,330 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// i.MX21 pinctrl driver based on imx pinmux core
-//
-// Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
-
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx1.h"
-
-#define PAD_ID(port, pin) ((port) * 32 + (pin))
-#define PA 0
-#define PB 1
-#define PC 2
-#define PD 3
-#define PE 4
-#define PF 5
-
-enum imx21_pads {
- MX21_PAD_LSCLK = PAD_ID(PA, 5),
- MX21_PAD_LD0 = PAD_ID(PA, 6),
- MX21_PAD_LD1 = PAD_ID(PA, 7),
- MX21_PAD_LD2 = PAD_ID(PA, 8),
- MX21_PAD_LD3 = PAD_ID(PA, 9),
- MX21_PAD_LD4 = PAD_ID(PA, 10),
- MX21_PAD_LD5 = PAD_ID(PA, 11),
- MX21_PAD_LD6 = PAD_ID(PA, 12),
- MX21_PAD_LD7 = PAD_ID(PA, 13),
- MX21_PAD_LD8 = PAD_ID(PA, 14),
- MX21_PAD_LD9 = PAD_ID(PA, 15),
- MX21_PAD_LD10 = PAD_ID(PA, 16),
- MX21_PAD_LD11 = PAD_ID(PA, 17),
- MX21_PAD_LD12 = PAD_ID(PA, 18),
- MX21_PAD_LD13 = PAD_ID(PA, 19),
- MX21_PAD_LD14 = PAD_ID(PA, 20),
- MX21_PAD_LD15 = PAD_ID(PA, 21),
- MX21_PAD_LD16 = PAD_ID(PA, 22),
- MX21_PAD_LD17 = PAD_ID(PA, 23),
- MX21_PAD_REV = PAD_ID(PA, 24),
- MX21_PAD_CLS = PAD_ID(PA, 25),
- MX21_PAD_PS = PAD_ID(PA, 26),
- MX21_PAD_SPL_SPR = PAD_ID(PA, 27),
- MX21_PAD_HSYNC = PAD_ID(PA, 28),
- MX21_PAD_VSYNC = PAD_ID(PA, 29),
- MX21_PAD_CONTRAST = PAD_ID(PA, 30),
- MX21_PAD_OE_ACD = PAD_ID(PA, 31),
- MX21_PAD_SD2_D0 = PAD_ID(PB, 4),
- MX21_PAD_SD2_D1 = PAD_ID(PB, 5),
- MX21_PAD_SD2_D2 = PAD_ID(PB, 6),
- MX21_PAD_SD2_D3 = PAD_ID(PB, 7),
- MX21_PAD_SD2_CMD = PAD_ID(PB, 8),
- MX21_PAD_SD2_CLK = PAD_ID(PB, 9),
- MX21_PAD_CSI_D0 = PAD_ID(PB, 10),
- MX21_PAD_CSI_D1 = PAD_ID(PB, 11),
- MX21_PAD_CSI_D2 = PAD_ID(PB, 12),
- MX21_PAD_CSI_D3 = PAD_ID(PB, 13),
- MX21_PAD_CSI_D4 = PAD_ID(PB, 14),
- MX21_PAD_CSI_MCLK = PAD_ID(PB, 15),
- MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
- MX21_PAD_CSI_D5 = PAD_ID(PB, 17),
- MX21_PAD_CSI_D6 = PAD_ID(PB, 18),
- MX21_PAD_CSI_D7 = PAD_ID(PB, 19),
- MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20),
- MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21),
- MX21_PAD_USB_BYP = PAD_ID(PB, 22),
- MX21_PAD_USB_PWR = PAD_ID(PB, 23),
- MX21_PAD_USB_OC = PAD_ID(PB, 24),
- MX21_PAD_USBH_ON = PAD_ID(PB, 25),
- MX21_PAD_USBH1_FS = PAD_ID(PB, 26),
- MX21_PAD_USBH1_OE = PAD_ID(PB, 27),
- MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28),
- MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29),
- MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30),
- MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31),
- MX21_PAD_USBG_SDA = PAD_ID(PC, 5),
- MX21_PAD_USBG_SCL = PAD_ID(PC, 6),
- MX21_PAD_USBG_ON = PAD_ID(PC, 7),
- MX21_PAD_USBG_FS = PAD_ID(PC, 8),
- MX21_PAD_USBG_OE = PAD_ID(PC, 9),
- MX21_PAD_USBG_TXDM = PAD_ID(PC, 10),
- MX21_PAD_USBG_TXDP = PAD_ID(PC, 11),
- MX21_PAD_USBG_RXDM = PAD_ID(PC, 12),
- MX21_PAD_USBG_RXDP = PAD_ID(PC, 13),
- MX21_PAD_TOUT = PAD_ID(PC, 14),
- MX21_PAD_TIN = PAD_ID(PC, 15),
- MX21_PAD_SAP_FS = PAD_ID(PC, 16),
- MX21_PAD_SAP_RXD = PAD_ID(PC, 17),
- MX21_PAD_SAP_TXD = PAD_ID(PC, 18),
- MX21_PAD_SAP_CLK = PAD_ID(PC, 19),
- MX21_PAD_SSI1_FS = PAD_ID(PC, 20),
- MX21_PAD_SSI1_RXD = PAD_ID(PC, 21),
- MX21_PAD_SSI1_TXD = PAD_ID(PC, 22),
- MX21_PAD_SSI1_CLK = PAD_ID(PC, 23),
- MX21_PAD_SSI2_FS = PAD_ID(PC, 24),
- MX21_PAD_SSI2_RXD = PAD_ID(PC, 25),
- MX21_PAD_SSI2_TXD = PAD_ID(PC, 26),
- MX21_PAD_SSI2_CLK = PAD_ID(PC, 27),
- MX21_PAD_SSI3_FS = PAD_ID(PC, 28),
- MX21_PAD_SSI3_RXD = PAD_ID(PC, 29),
- MX21_PAD_SSI3_TXD = PAD_ID(PC, 30),
- MX21_PAD_SSI3_CLK = PAD_ID(PC, 31),
- MX21_PAD_I2C_DATA = PAD_ID(PD, 17),
- MX21_PAD_I2C_CLK = PAD_ID(PD, 18),
- MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
- MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
- MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
- MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
- MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23),
- MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
- MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25),
- MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
- MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
- MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
- MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
- MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30),
- MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
- MX21_PAD_TEST_WB2 = PAD_ID(PE, 0),
- MX21_PAD_TEST_WB1 = PAD_ID(PE, 1),
- MX21_PAD_TEST_WB0 = PAD_ID(PE, 2),
- MX21_PAD_UART2_CTS = PAD_ID(PE, 3),
- MX21_PAD_UART2_RTS = PAD_ID(PE, 4),
- MX21_PAD_PWMO = PAD_ID(PE, 5),
- MX21_PAD_UART2_TXD = PAD_ID(PE, 6),
- MX21_PAD_UART2_RXD = PAD_ID(PE, 7),
- MX21_PAD_UART3_TXD = PAD_ID(PE, 8),
- MX21_PAD_UART3_RXD = PAD_ID(PE, 9),
- MX21_PAD_UART3_CTS = PAD_ID(PE, 10),
- MX21_PAD_UART3_RTS = PAD_ID(PE, 11),
- MX21_PAD_UART1_TXD = PAD_ID(PE, 12),
- MX21_PAD_UART1_RXD = PAD_ID(PE, 13),
- MX21_PAD_UART1_CTS = PAD_ID(PE, 14),
- MX21_PAD_UART1_RTS = PAD_ID(PE, 15),
- MX21_PAD_RTCK = PAD_ID(PE, 16),
- MX21_PAD_RESET_OUT = PAD_ID(PE, 17),
- MX21_PAD_SD1_D0 = PAD_ID(PE, 18),
- MX21_PAD_SD1_D1 = PAD_ID(PE, 19),
- MX21_PAD_SD1_D2 = PAD_ID(PE, 20),
- MX21_PAD_SD1_D3 = PAD_ID(PE, 21),
- MX21_PAD_SD1_CMD = PAD_ID(PE, 22),
- MX21_PAD_SD1_CLK = PAD_ID(PE, 23),
- MX21_PAD_NFRB = PAD_ID(PF, 0),
- MX21_PAD_NFCE = PAD_ID(PF, 1),
- MX21_PAD_NFWP = PAD_ID(PF, 2),
- MX21_PAD_NFCLE = PAD_ID(PF, 3),
- MX21_PAD_NFALE = PAD_ID(PF, 4),
- MX21_PAD_NFRE = PAD_ID(PF, 5),
- MX21_PAD_NFWE = PAD_ID(PF, 6),
- MX21_PAD_NFIO0 = PAD_ID(PF, 7),
- MX21_PAD_NFIO1 = PAD_ID(PF, 8),
- MX21_PAD_NFIO2 = PAD_ID(PF, 9),
- MX21_PAD_NFIO3 = PAD_ID(PF, 10),
- MX21_PAD_NFIO4 = PAD_ID(PF, 11),
- MX21_PAD_NFIO5 = PAD_ID(PF, 12),
- MX21_PAD_NFIO6 = PAD_ID(PF, 13),
- MX21_PAD_NFIO7 = PAD_ID(PF, 14),
- MX21_PAD_CLKO = PAD_ID(PF, 15),
- MX21_PAD_RESERVED = PAD_ID(PF, 16),
- MX21_PAD_CS4 = PAD_ID(PF, 21),
- MX21_PAD_CS5 = PAD_ID(PF, 22),
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX21_PAD_LSCLK),
- IMX_PINCTRL_PIN(MX21_PAD_LD0),
- IMX_PINCTRL_PIN(MX21_PAD_LD1),
- IMX_PINCTRL_PIN(MX21_PAD_LD2),
- IMX_PINCTRL_PIN(MX21_PAD_LD3),
- IMX_PINCTRL_PIN(MX21_PAD_LD4),
- IMX_PINCTRL_PIN(MX21_PAD_LD5),
- IMX_PINCTRL_PIN(MX21_PAD_LD6),
- IMX_PINCTRL_PIN(MX21_PAD_LD7),
- IMX_PINCTRL_PIN(MX21_PAD_LD8),
- IMX_PINCTRL_PIN(MX21_PAD_LD9),
- IMX_PINCTRL_PIN(MX21_PAD_LD10),
- IMX_PINCTRL_PIN(MX21_PAD_LD11),
- IMX_PINCTRL_PIN(MX21_PAD_LD12),
- IMX_PINCTRL_PIN(MX21_PAD_LD13),
- IMX_PINCTRL_PIN(MX21_PAD_LD14),
- IMX_PINCTRL_PIN(MX21_PAD_LD15),
- IMX_PINCTRL_PIN(MX21_PAD_LD16),
- IMX_PINCTRL_PIN(MX21_PAD_LD17),
- IMX_PINCTRL_PIN(MX21_PAD_REV),
- IMX_PINCTRL_PIN(MX21_PAD_CLS),
- IMX_PINCTRL_PIN(MX21_PAD_PS),
- IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR),
- IMX_PINCTRL_PIN(MX21_PAD_HSYNC),
- IMX_PINCTRL_PIN(MX21_PAD_VSYNC),
- IMX_PINCTRL_PIN(MX21_PAD_CONTRAST),
- IMX_PINCTRL_PIN(MX21_PAD_OE_ACD),
- IMX_PINCTRL_PIN(MX21_PAD_SD2_D0),
- IMX_PINCTRL_PIN(MX21_PAD_SD2_D1),
- IMX_PINCTRL_PIN(MX21_PAD_SD2_D2),
- IMX_PINCTRL_PIN(MX21_PAD_SD2_D3),
- IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD),
- IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_D0),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_D1),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_D2),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_D3),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_D4),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_D5),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_D6),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_D7),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC),
- IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC),
- IMX_PINCTRL_PIN(MX21_PAD_USB_BYP),
- IMX_PINCTRL_PIN(MX21_PAD_USB_PWR),
- IMX_PINCTRL_PIN(MX21_PAD_USB_OC),
- IMX_PINCTRL_PIN(MX21_PAD_USBH_ON),
- IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS),
- IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE),
- IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM),
- IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP),
- IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM),
- IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP),
- IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA),
- IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL),
- IMX_PINCTRL_PIN(MX21_PAD_USBG_ON),
- IMX_PINCTRL_PIN(MX21_PAD_USBG_FS),
- IMX_PINCTRL_PIN(MX21_PAD_USBG_OE),
- IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM),
- IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP),
- IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM),
- IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP),
- IMX_PINCTRL_PIN(MX21_PAD_TOUT),
- IMX_PINCTRL_PIN(MX21_PAD_TIN),
- IMX_PINCTRL_PIN(MX21_PAD_SAP_FS),
- IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD),
- IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD),
- IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK),
- IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS),
- IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD),
- IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD),
- IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK),
- IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS),
- IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD),
- IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD),
- IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK),
- IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS),
- IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD),
- IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD),
- IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK),
- IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA),
- IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO),
- IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI),
- IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2),
- IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1),
- IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0),
- IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS),
- IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS),
- IMX_PINCTRL_PIN(MX21_PAD_PWMO),
- IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD),
- IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD),
- IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD),
- IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD),
- IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS),
- IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS),
- IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD),
- IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD),
- IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS),
- IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS),
- IMX_PINCTRL_PIN(MX21_PAD_RTCK),
- IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT),
- IMX_PINCTRL_PIN(MX21_PAD_SD1_D0),
- IMX_PINCTRL_PIN(MX21_PAD_SD1_D1),
- IMX_PINCTRL_PIN(MX21_PAD_SD1_D2),
- IMX_PINCTRL_PIN(MX21_PAD_SD1_D3),
- IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX21_PAD_NFRB),
- IMX_PINCTRL_PIN(MX21_PAD_NFCE),
- IMX_PINCTRL_PIN(MX21_PAD_NFWP),
- IMX_PINCTRL_PIN(MX21_PAD_NFCLE),
- IMX_PINCTRL_PIN(MX21_PAD_NFALE),
- IMX_PINCTRL_PIN(MX21_PAD_NFRE),
- IMX_PINCTRL_PIN(MX21_PAD_NFWE),
- IMX_PINCTRL_PIN(MX21_PAD_NFIO0),
- IMX_PINCTRL_PIN(MX21_PAD_NFIO1),
- IMX_PINCTRL_PIN(MX21_PAD_NFIO2),
- IMX_PINCTRL_PIN(MX21_PAD_NFIO3),
- IMX_PINCTRL_PIN(MX21_PAD_NFIO4),
- IMX_PINCTRL_PIN(MX21_PAD_NFIO5),
- IMX_PINCTRL_PIN(MX21_PAD_NFIO6),
- IMX_PINCTRL_PIN(MX21_PAD_NFIO7),
- IMX_PINCTRL_PIN(MX21_PAD_CLKO),
- IMX_PINCTRL_PIN(MX21_PAD_RESERVED),
- IMX_PINCTRL_PIN(MX21_PAD_CS4),
- IMX_PINCTRL_PIN(MX21_PAD_CS5),
-};
-
-static struct imx1_pinctrl_soc_info imx21_pinctrl_info = {
- .pins = imx21_pinctrl_pads,
- .npins = ARRAY_SIZE(imx21_pinctrl_pads),
-};
-
-static int __init imx21_pinctrl_probe(struct platform_device *pdev)
-{
- return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info);
-}
-
-static const struct of_device_id imx21_pinctrl_of_match[] = {
- { .compatible = "fsl,imx21-iomuxc", },
- { }
-};
-
-static struct platform_driver imx21_pinctrl_driver = {
- .driver = {
- .name = "imx21-pinctrl",
- .of_match_table = imx21_pinctrl_of_match,
- },
-};
-builtin_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe);
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 28e5f824ba45..fb1495bd77c4 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -55,6 +55,14 @@ config PINCTRL_INTEL
select GPIOLIB
select GPIOLIB_IRQCHIP
+config PINCTRL_ALDERLAKE
+ tristate "Intel Alder Lake pinctrl and GPIO driver"
+ depends on ACPI
+ select PINCTRL_INTEL
+ help
+ This pinctrl driver provides an interface that allows configuring
+ of Intel Alder Lake PCH pins and using them as GPIOs.
+
config PINCTRL_BROXTON
tristate "Intel Broxton pinctrl and GPIO driver"
depends on ACPI
@@ -87,6 +95,14 @@ config PINCTRL_DENVERTON
This pinctrl driver provides an interface that allows configuring
of Intel Denverton SoC pins and using them as GPIOs.
+config PINCTRL_ELKHARTLAKE
+ tristate "Intel Elkhart Lake SoC pinctrl and GPIO driver"
+ depends on ACPI
+ select PINCTRL_INTEL
+ help
+ This pinctrl driver provides an interface that allows configuring
+ of Intel Elkhart Lake SoC pins and using them as GPIOs.
+
config PINCTRL_EMMITSBURG
tristate "Intel Emmitsburg pinctrl and GPIO driver"
depends on ACPI
@@ -119,6 +135,14 @@ config PINCTRL_JASPERLAKE
This pinctrl driver provides an interface that allows configuring
of Intel Jasper Lake PCH pins and using them as GPIOs.
+config PINCTRL_LAKEFIELD
+ tristate "Intel Lakefield SoC pinctrl and GPIO driver"
+ depends on ACPI
+ select PINCTRL_INTEL
+ help
+ This pinctrl driver provides an interface that allows configuring
+ of Intel Lakefield SoC pins and using them as GPIOs.
+
config PINCTRL_LEWISBURG
tristate "Intel Lewisburg pinctrl and GPIO driver"
depends on ACPI
@@ -143,4 +167,5 @@ config PINCTRL_TIGERLAKE
help
This pinctrl driver provides an interface that allows configuring
of Intel Tiger Lake PCH pins and using them as GPIOs.
+
endif
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index 1c1c316f98b9..181ffcf34d62 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -6,14 +6,17 @@ obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o
obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
+obj-$(CONFIG_PINCTRL_ALDERLAKE) += pinctrl-alderlake.o
obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o
obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o
+obj-$(CONFIG_PINCTRL_ELKHARTLAKE) += pinctrl-elkhartlake.o
obj-$(CONFIG_PINCTRL_EMMITSBURG) += pinctrl-emmitsburg.o
obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o
obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o
+obj-$(CONFIG_PINCTRL_LAKEFIELD) += pinctrl-lakefield.o
obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o
diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c
new file mode 100644
index 000000000000..efb664f12b5d
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-alderlake.c
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel Alder Lake PCH pinctrl/GPIO driver
+ *
+ * Copyright (C) 2020, Intel Corporation
+ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-intel.h"
+
+#define ADL_PAD_OWN 0x0a0
+#define ADL_PADCFGLOCK 0x110
+#define ADL_HOSTSW_OWN 0x150
+#define ADL_GPI_IS 0x200
+#define ADL_GPI_IE 0x220
+
+#define ADL_GPP(r, s, e, g) \
+ { \
+ .reg_num = (r), \
+ .base = (s), \
+ .size = ((e) - (s) + 1), \
+ .gpio_base = (g), \
+ }
+
+#define ADL_COMMUNITY(b, s, e, g) \
+ { \
+ .barno = (b), \
+ .padown_offset = ADL_PAD_OWN, \
+ .padcfglock_offset = ADL_PADCFGLOCK, \
+ .hostown_offset = ADL_HOSTSW_OWN, \
+ .is_offset = ADL_GPI_IS, \
+ .ie_offset = ADL_GPI_IE, \
+ .pin_base = (s), \
+ .npins = ((e) - (s) + 1), \
+ .gpps = (g), \
+ .ngpps = ARRAY_SIZE(g), \
+ }
+
+/* Alder Lake-S */
+static const struct pinctrl_pin_desc adls_pins[] = {
+ /* GPP_I */
+ PINCTRL_PIN(0, "EXT_PWR_GATEB"),
+ PINCTRL_PIN(1, "DDSP_HPD_1"),
+ PINCTRL_PIN(2, "DDSP_HPD_2"),
+ PINCTRL_PIN(3, "DDSP_HPD_3"),
+ PINCTRL_PIN(4, "DDSP_HPD_4"),
+ PINCTRL_PIN(5, "DDPB_CTRLCLK"),
+ PINCTRL_PIN(6, "DDPB_CTRLDATA"),
+ PINCTRL_PIN(7, "DDPC_CTRLCLK"),
+ PINCTRL_PIN(8, "DDPC_CTRLDATA"),
+ PINCTRL_PIN(9, "GSPI0_CS1B"),
+ PINCTRL_PIN(10, "GSPI1_CS1B"),
+ PINCTRL_PIN(11, "USB2_OCB_4"),
+ PINCTRL_PIN(12, "USB2_OCB_5"),
+ PINCTRL_PIN(13, "USB2_OCB_6"),
+ PINCTRL_PIN(14, "USB2_OCB_7"),
+ PINCTRL_PIN(15, "GSPI0_CS0B"),
+ PINCTRL_PIN(16, "GSPI0_CLK"),
+ PINCTRL_PIN(17, "GSPI0_MISO"),
+ PINCTRL_PIN(18, "GSPI0_MOSI"),
+ PINCTRL_PIN(19, "GSPI1_CS0B"),
+ PINCTRL_PIN(20, "GSPI1_CLK"),
+ PINCTRL_PIN(21, "GSPI1_MISO"),
+ PINCTRL_PIN(22, "GSPI1_MOSI"),
+ PINCTRL_PIN(23, "GSPI0_CLK_LOOPBK"),
+ PINCTRL_PIN(24, "GSPI1_CLK_LOOPBK"),
+ /* GPP_R */
+ PINCTRL_PIN(25, "HDA_BCLK"),
+ PINCTRL_PIN(26, "HDA_SYNC"),
+ PINCTRL_PIN(27, "HDA_SDO"),
+ PINCTRL_PIN(28, "HDA_SDI_0"),
+ PINCTRL_PIN(29, "HDA_RSTB"),
+ PINCTRL_PIN(30, "HDA_SDI_1"),
+ PINCTRL_PIN(31, "GPP_R_6"),
+ PINCTRL_PIN(32, "GPP_R_7"),
+ PINCTRL_PIN(33, "GPP_R_8"),
+ PINCTRL_PIN(34, "DDSP_HPD_A"),
+ PINCTRL_PIN(35, "DDSP_HPD_B"),
+ PINCTRL_PIN(36, "DDSP_HPD_C"),
+ PINCTRL_PIN(37, "ISH_SPI_CSB"),
+ PINCTRL_PIN(38, "ISH_SPI_CLK"),
+ PINCTRL_PIN(39, "ISH_SPI_MISO"),
+ PINCTRL_PIN(40, "ISH_SPI_MOSI"),
+ PINCTRL_PIN(41, "DDP1_CTRLCLK"),
+ PINCTRL_PIN(42, "DDP1_CTRLDATA"),
+ PINCTRL_PIN(43, "DDP2_CTRLCLK"),
+ PINCTRL_PIN(44, "DDP2_CTRLDATA"),
+ PINCTRL_PIN(45, "DDPA_CTRLCLK"),
+ PINCTRL_PIN(46, "DDPA_CTRLDATA"),
+ PINCTRL_PIN(47, "GSPI2_CLK_LOOPBK"),
+ /* GPP_J */
+ PINCTRL_PIN(48, "CNV_PA_BLANKING"),
+ PINCTRL_PIN(49, "CPU_C10_GATEB"),
+ PINCTRL_PIN(50, "CNV_BRI_DT"),
+ PINCTRL_PIN(51, "CNV_BRI_RSP"),
+ PINCTRL_PIN(52, "CNV_RGI_DT"),
+ PINCTRL_PIN(53, "CNV_RGI_RSP"),
+ PINCTRL_PIN(54, "CNV_MFUART2_RXD"),
+ PINCTRL_PIN(55, "CNV_MFUART2_TXD"),
+ PINCTRL_PIN(56, "SRCCLKREQB_16"),
+ PINCTRL_PIN(57, "SRCCLKREQB_17"),
+ PINCTRL_PIN(58, "BSSB_LS_RX"),
+ PINCTRL_PIN(59, "BSSB_LS_TX"),
+ /* vGPIO */
+ PINCTRL_PIN(60, "CNV_BTEN"),
+ PINCTRL_PIN(61, "CNV_BT_HOST_WAKEB"),
+ PINCTRL_PIN(62, "CNV_BT_IF_SELECT"),
+ PINCTRL_PIN(63, "vCNV_BT_UART_TXD"),
+ PINCTRL_PIN(64, "vCNV_BT_UART_RXD"),
+ PINCTRL_PIN(65, "vCNV_BT_UART_CTS_B"),
+ PINCTRL_PIN(66, "vCNV_BT_UART_RTS_B"),
+ PINCTRL_PIN(67, "vCNV_MFUART1_TXD"),
+ PINCTRL_PIN(68, "vCNV_MFUART1_RXD"),
+ PINCTRL_PIN(69, "vCNV_MFUART1_CTS_B"),
+ PINCTRL_PIN(70, "vCNV_MFUART1_RTS_B"),
+ PINCTRL_PIN(71, "vUART0_TXD"),
+ PINCTRL_PIN(72, "vUART0_RXD"),
+ PINCTRL_PIN(73, "vUART0_CTS_B"),
+ PINCTRL_PIN(74, "vUART0_RTS_B"),
+ PINCTRL_PIN(75, "vISH_UART0_TXD"),
+ PINCTRL_PIN(76, "vISH_UART0_RXD"),
+ PINCTRL_PIN(77, "vISH_UART0_CTS_B"),
+ PINCTRL_PIN(78, "vISH_UART0_RTS_B"),
+ PINCTRL_PIN(79, "vCNV_BT_I2S_BCLK"),
+ PINCTRL_PIN(80, "vCNV_BT_I2S_WS_SYNC"),
+ PINCTRL_PIN(81, "vCNV_BT_I2S_SDO"),
+ PINCTRL_PIN(82, "vCNV_BT_I2S_SDI"),
+ PINCTRL_PIN(83, "vI2S2_SCLK"),
+ PINCTRL_PIN(84, "vI2S2_SFRM"),
+ PINCTRL_PIN(85, "vI2S2_TXD"),
+ PINCTRL_PIN(86, "vI2S2_RXD"),
+ /* vGPIO_0 */
+ PINCTRL_PIN(87, "ESPI_USB_OCB_0"),
+ PINCTRL_PIN(88, "ESPI_USB_OCB_1"),
+ PINCTRL_PIN(89, "ESPI_USB_OCB_2"),
+ PINCTRL_PIN(90, "ESPI_USB_OCB_3"),
+ PINCTRL_PIN(91, "USB_CPU_OCB_0"),
+ PINCTRL_PIN(92, "USB_CPU_OCB_1"),
+ PINCTRL_PIN(93, "USB_CPU_OCB_2"),
+ PINCTRL_PIN(94, "USB_CPU_OCB_3"),
+ /* GPP_B */
+ PINCTRL_PIN(95, "PCIE_LNK_DOWN"),
+ PINCTRL_PIN(96, "ISH_UART0_RTSB"),
+ PINCTRL_PIN(97, "VRALERTB"),
+ PINCTRL_PIN(98, "CPU_GP_2"),
+ PINCTRL_PIN(99, "CPU_GP_3"),
+ PINCTRL_PIN(100, "SX_EXIT_HOLDOFFB"),
+ PINCTRL_PIN(101, "CLKOUT_48"),
+ PINCTRL_PIN(102, "ISH_GP_7"),
+ PINCTRL_PIN(103, "ISH_GP_0"),
+ PINCTRL_PIN(104, "ISH_GP_1"),
+ PINCTRL_PIN(105, "ISH_GP_2"),
+ PINCTRL_PIN(106, "I2S_MCLK"),
+ PINCTRL_PIN(107, "SLP_S0B"),
+ PINCTRL_PIN(108, "PLTRSTB"),
+ PINCTRL_PIN(109, "SPKR"),
+ PINCTRL_PIN(110, "ISH_GP_3"),
+ PINCTRL_PIN(111, "ISH_GP_4"),
+ PINCTRL_PIN(112, "ISH_GP_5"),
+ PINCTRL_PIN(113, "PMCALERTB"),
+ PINCTRL_PIN(114, "FUSA_DIAGTEST_EN"),
+ PINCTRL_PIN(115, "FUSA_DIAGTEST_MODE"),
+ PINCTRL_PIN(116, "GPP_B_21"),
+ PINCTRL_PIN(117, "GPP_B_22"),
+ PINCTRL_PIN(118, "SML1ALERTB"),
+ /* GPP_G */
+ PINCTRL_PIN(119, "GPP_G_0"),
+ PINCTRL_PIN(120, "GPP_G_1"),
+ PINCTRL_PIN(121, "DNX_FORCE_RELOAD"),
+ PINCTRL_PIN(122, "GMII_MDC_0"),
+ PINCTRL_PIN(123, "GMII_MDIO_0"),
+ PINCTRL_PIN(124, "SLP_DRAMB"),
+ PINCTRL_PIN(125, "GPP_G_6"),
+ PINCTRL_PIN(126, "GPP_G_7"),
+ /* GPP_H */
+ PINCTRL_PIN(127, "SRCCLKREQB_18"),
+ PINCTRL_PIN(128, "GPP_H_1"),
+ PINCTRL_PIN(129, "SRCCLKREQB_8"),
+ PINCTRL_PIN(130, "SRCCLKREQB_9"),
+ PINCTRL_PIN(131, "SRCCLKREQB_10"),
+ PINCTRL_PIN(132, "SRCCLKREQB_11"),
+ PINCTRL_PIN(133, "SRCCLKREQB_12"),
+ PINCTRL_PIN(134, "SRCCLKREQB_13"),
+ PINCTRL_PIN(135, "SRCCLKREQB_14"),
+ PINCTRL_PIN(136, "SRCCLKREQB_15"),
+ PINCTRL_PIN(137, "SML2CLK"),
+ PINCTRL_PIN(138, "SML2DATA"),
+ PINCTRL_PIN(139, "SML2ALERTB"),
+ PINCTRL_PIN(140, "SML3CLK"),
+ PINCTRL_PIN(141, "SML3DATA"),
+ PINCTRL_PIN(142, "SML3ALERTB"),
+ PINCTRL_PIN(143, "SML4CLK"),
+ PINCTRL_PIN(144, "SML4DATA"),
+ PINCTRL_PIN(145, "SML4ALERTB"),
+ PINCTRL_PIN(146, "ISH_I2C0_SDA"),
+ PINCTRL_PIN(147, "ISH_I2C0_SCL"),
+ PINCTRL_PIN(148, "ISH_I2C1_SDA"),
+ PINCTRL_PIN(149, "ISH_I2C1_SCL"),
+ PINCTRL_PIN(150, "TIME_SYNC_0"),
+ /* SPI0 */
+ PINCTRL_PIN(151, "SPI0_IO_2"),
+ PINCTRL_PIN(152, "SPI0_IO_3"),
+ PINCTRL_PIN(153, "SPI0_MOSI_IO_0"),
+ PINCTRL_PIN(154, "SPI0_MISO_IO_1"),
+ PINCTRL_PIN(155, "SPI0_TPM_CSB"),
+ PINCTRL_PIN(156, "SPI0_FLASH_0_CSB"),
+ PINCTRL_PIN(157, "SPI0_FLASH_1_CSB"),
+ PINCTRL_PIN(158, "SPI0_CLK"),
+ PINCTRL_PIN(159, "SPI0_CLK_LOOPBK"),
+ /* GPP_A */
+ PINCTRL_PIN(160, "ESPI_IO_0"),
+ PINCTRL_PIN(161, "ESPI_IO_1"),
+ PINCTRL_PIN(162, "ESPI_IO_2"),
+ PINCTRL_PIN(163, "ESPI_IO_3"),
+ PINCTRL_PIN(164, "ESPI_CS0B"),
+ PINCTRL_PIN(165, "ESPI_CLK"),
+ PINCTRL_PIN(166, "ESPI_RESETB"),
+ PINCTRL_PIN(167, "ESPI_CS1B"),
+ PINCTRL_PIN(168, "ESPI_CS2B"),
+ PINCTRL_PIN(169, "ESPI_CS3B"),
+ PINCTRL_PIN(170, "ESPI_ALERT0B"),
+ PINCTRL_PIN(171, "ESPI_ALERT1B"),
+ PINCTRL_PIN(172, "ESPI_ALERT2B"),
+ PINCTRL_PIN(173, "ESPI_ALERT3B"),
+ PINCTRL_PIN(174, "GPP_A_14"),
+ PINCTRL_PIN(175, "ESPI_CLK_LOOPBK"),
+ /* GPP_C */
+ PINCTRL_PIN(176, "SMBCLK"),
+ PINCTRL_PIN(177, "SMBDATA"),
+ PINCTRL_PIN(178, "SMBALERTB"),
+ PINCTRL_PIN(179, "ISH_UART0_RXD"),
+ PINCTRL_PIN(180, "ISH_UART0_TXD"),
+ PINCTRL_PIN(181, "SML0ALERTB"),
+ PINCTRL_PIN(182, "ISH_I2C2_SDA"),
+ PINCTRL_PIN(183, "ISH_I2C2_SCL"),
+ PINCTRL_PIN(184, "UART0_RXD"),
+ PINCTRL_PIN(185, "UART0_TXD"),
+ PINCTRL_PIN(186, "UART0_RTSB"),
+ PINCTRL_PIN(187, "UART0_CTSB"),
+ PINCTRL_PIN(188, "UART1_RXD"),
+ PINCTRL_PIN(189, "UART1_TXD"),
+ PINCTRL_PIN(190, "UART1_RTSB"),
+ PINCTRL_PIN(191, "UART1_CTSB"),
+ PINCTRL_PIN(192, "I2C0_SDA"),
+ PINCTRL_PIN(193, "I2C0_SCL"),
+ PINCTRL_PIN(194, "I2C1_SDA"),
+ PINCTRL_PIN(195, "I2C1_SCL"),
+ PINCTRL_PIN(196, "UART2_RXD"),
+ PINCTRL_PIN(197, "UART2_TXD"),
+ PINCTRL_PIN(198, "UART2_RTSB"),
+ PINCTRL_PIN(199, "UART2_CTSB"),
+ /* GPP_S */
+ PINCTRL_PIN(200, "SNDW1_CLK"),
+ PINCTRL_PIN(201, "SNDW1_DATA"),
+ PINCTRL_PIN(202, "SNDW2_CLK"),
+ PINCTRL_PIN(203, "SNDW2_DATA"),
+ PINCTRL_PIN(204, "SNDW3_CLK"),
+ PINCTRL_PIN(205, "SNDW3_DATA"),
+ PINCTRL_PIN(206, "SNDW4_CLK"),
+ PINCTRL_PIN(207, "SNDW4_DATA"),
+ /* GPP_E */
+ PINCTRL_PIN(208, "SATAXPCIE_0"),
+ PINCTRL_PIN(209, "SATAXPCIE_1"),
+ PINCTRL_PIN(210, "SATAXPCIE_2"),
+ PINCTRL_PIN(211, "CPU_GP_0"),
+ PINCTRL_PIN(212, "SATA_DEVSLP_0"),
+ PINCTRL_PIN(213, "SATA_DEVSLP_1"),
+ PINCTRL_PIN(214, "SATA_DEVSLP_2"),
+ PINCTRL_PIN(215, "CPU_GP_1"),
+ PINCTRL_PIN(216, "SATA_LEDB"),
+ PINCTRL_PIN(217, "USB2_OCB_0"),
+ PINCTRL_PIN(218, "USB2_OCB_1"),
+ PINCTRL_PIN(219, "USB2_OCB_2"),
+ PINCTRL_PIN(220, "USB2_OCB_3"),
+ PINCTRL_PIN(221, "SPI1_CSB"),
+ PINCTRL_PIN(222, "SPI1_CLK"),
+ PINCTRL_PIN(223, "SPI1_MISO_IO_1"),
+ PINCTRL_PIN(224, "SPI1_MOSI_IO_0"),
+ PINCTRL_PIN(225, "SPI1_IO_2"),
+ PINCTRL_PIN(226, "SPI1_IO_3"),
+ PINCTRL_PIN(227, "GPP_E_19"),
+ PINCTRL_PIN(228, "GPP_E_20"),
+ PINCTRL_PIN(229, "ISH_UART0_CTSB"),
+ PINCTRL_PIN(230, "SPI1_CLK_LOOPBK"),
+ /* GPP_K */
+ PINCTRL_PIN(231, "GSXDOUT"),
+ PINCTRL_PIN(232, "GSXSLOAD"),
+ PINCTRL_PIN(233, "GSXDIN"),
+ PINCTRL_PIN(234, "GSXSRESETB"),
+ PINCTRL_PIN(235, "GSXCLK"),
+ PINCTRL_PIN(236, "ADR_COMPLETE"),
+ PINCTRL_PIN(237, "GPP_K_6"),
+ PINCTRL_PIN(238, "GPP_K_7"),
+ PINCTRL_PIN(239, "CORE_VID_0"),
+ PINCTRL_PIN(240, "CORE_VID_1"),
+ PINCTRL_PIN(241, "GPP_K_10"),
+ PINCTRL_PIN(242, "GPP_K_11"),
+ PINCTRL_PIN(243, "SYS_PWROK"),
+ PINCTRL_PIN(244, "SYS_RESETB"),
+ PINCTRL_PIN(245, "MLK_RSTB"),
+ /* GPP_F */
+ PINCTRL_PIN(246, "SATAXPCIE_3"),
+ PINCTRL_PIN(247, "SATAXPCIE_4"),
+ PINCTRL_PIN(248, "SATAXPCIE_5"),
+ PINCTRL_PIN(249, "SATAXPCIE_6"),
+ PINCTRL_PIN(250, "SATAXPCIE_7"),
+ PINCTRL_PIN(251, "SATA_DEVSLP_3"),
+ PINCTRL_PIN(252, "SATA_DEVSLP_4"),
+ PINCTRL_PIN(253, "SATA_DEVSLP_5"),
+ PINCTRL_PIN(254, "SATA_DEVSLP_6"),
+ PINCTRL_PIN(255, "SATA_DEVSLP_7"),
+ PINCTRL_PIN(256, "SATA_SCLOCK"),
+ PINCTRL_PIN(257, "SATA_SLOAD"),
+ PINCTRL_PIN(258, "SATA_SDATAOUT1"),
+ PINCTRL_PIN(259, "SATA_SDATAOUT0"),
+ PINCTRL_PIN(260, "PS_ONB"),
+ PINCTRL_PIN(261, "M2_SKT2_CFG_0"),
+ PINCTRL_PIN(262, "M2_SKT2_CFG_1"),
+ PINCTRL_PIN(263, "M2_SKT2_CFG_2"),
+ PINCTRL_PIN(264, "M2_SKT2_CFG_3"),
+ PINCTRL_PIN(265, "L_VDDEN"),
+ PINCTRL_PIN(266, "L_BKLTEN"),
+ PINCTRL_PIN(267, "L_BKLTCTL"),
+ PINCTRL_PIN(268, "VNN_CTRL"),
+ PINCTRL_PIN(269, "GPP_F_23"),
+ /* GPP_D */
+ PINCTRL_PIN(270, "SRCCLKREQB_0"),
+ PINCTRL_PIN(271, "SRCCLKREQB_1"),
+ PINCTRL_PIN(272, "SRCCLKREQB_2"),
+ PINCTRL_PIN(273, "SRCCLKREQB_3"),
+ PINCTRL_PIN(274, "SML1CLK"),
+ PINCTRL_PIN(275, "I2S2_SFRM"),
+ PINCTRL_PIN(276, "I2S2_TXD"),
+ PINCTRL_PIN(277, "I2S2_RXD"),
+ PINCTRL_PIN(278, "I2S2_SCLK"),
+ PINCTRL_PIN(279, "SML0CLK"),
+ PINCTRL_PIN(280, "SML0DATA"),
+ PINCTRL_PIN(281, "SRCCLKREQB_4"),
+ PINCTRL_PIN(282, "SRCCLKREQB_5"),
+ PINCTRL_PIN(283, "SRCCLKREQB_6"),
+ PINCTRL_PIN(284, "SRCCLKREQB_7"),
+ PINCTRL_PIN(285, "SML1DATA"),
+ PINCTRL_PIN(286, "GSPI3_CS0B"),
+ PINCTRL_PIN(287, "GSPI3_CLK"),
+ PINCTRL_PIN(288, "GSPI3_MISO"),
+ PINCTRL_PIN(289, "GSPI3_MOSI"),
+ PINCTRL_PIN(290, "UART3_RXD"),
+ PINCTRL_PIN(291, "UART3_TXD"),
+ PINCTRL_PIN(292, "UART3_RTSB"),
+ PINCTRL_PIN(293, "UART3_CTSB"),
+ PINCTRL_PIN(294, "GSPI3_CLK_LOOPBK"),
+ /* JTAG */
+ PINCTRL_PIN(295, "JTAG_TDO"),
+ PINCTRL_PIN(296, "JTAGX"),
+ PINCTRL_PIN(297, "PRDYB"),
+ PINCTRL_PIN(298, "PREQB"),
+ PINCTRL_PIN(299, "JTAG_TDI"),
+ PINCTRL_PIN(300, "JTAG_TMS"),
+ PINCTRL_PIN(301, "JTAG_TCK"),
+ PINCTRL_PIN(302, "DBG_PMODE"),
+ PINCTRL_PIN(303, "CPU_TRSTB"),
+};
+
+static const struct intel_padgroup adls_community0_gpps[] = {
+ ADL_GPP(0, 0, 24, 0), /* GPP_I */
+ ADL_GPP(1, 25, 47, 32), /* GPP_R */
+ ADL_GPP(2, 48, 59, 64), /* GPP_J */
+ ADL_GPP(3, 60, 86, 96), /* vGPIO */
+ ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */
+};
+
+static const struct intel_padgroup adls_community1_gpps[] = {
+ ADL_GPP(0, 95, 118, 160), /* GPP_B */
+ ADL_GPP(1, 119, 126, 192), /* GPP_G */
+ ADL_GPP(2, 127, 150, 224), /* GPP_H */
+};
+
+static const struct intel_padgroup adls_community3_gpps[] = {
+ ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */
+ ADL_GPP(1, 160, 175, 256), /* GPP_A */
+ ADL_GPP(2, 176, 199, 288), /* GPP_C */
+};
+
+static const struct intel_padgroup adls_community4_gpps[] = {
+ ADL_GPP(0, 200, 207, 320), /* GPP_S */
+ ADL_GPP(1, 208, 230, 352), /* GPP_E */
+ ADL_GPP(2, 231, 245, 384), /* GPP_K */
+ ADL_GPP(3, 246, 269, 416), /* GPP_F */
+};
+
+static const struct intel_padgroup adls_community5_gpps[] = {
+ ADL_GPP(0, 270, 294, 448), /* GPP_D */
+ ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */
+};
+
+static const struct intel_community adls_communities[] = {
+ ADL_COMMUNITY(0, 0, 94, adls_community0_gpps),
+ ADL_COMMUNITY(1, 95, 150, adls_community1_gpps),
+ ADL_COMMUNITY(2, 151, 199, adls_community3_gpps),
+ ADL_COMMUNITY(3, 200, 269, adls_community4_gpps),
+ ADL_COMMUNITY(4, 270, 303, adls_community5_gpps),
+};
+
+static const struct intel_pinctrl_soc_data adls_soc_data = {
+ .pins = adls_pins,
+ .npins = ARRAY_SIZE(adls_pins),
+ .communities = adls_communities,
+ .ncommunities = ARRAY_SIZE(adls_communities),
+};
+
+static const struct acpi_device_id adl_pinctrl_acpi_match[] = {
+ { "INTC1056", (kernel_ulong_t)&adls_soc_data },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match);
+
+static INTEL_PINCTRL_PM_OPS(adl_pinctrl_pm_ops);
+
+static struct platform_driver adl_pinctrl_driver = {
+ .probe = intel_pinctrl_probe_by_hid,
+ .driver = {
+ .name = "alderlake-pinctrl",
+ .acpi_match_table = adl_pinctrl_acpi_match,
+ .pm = &adl_pinctrl_pm_ops,
+ },
+};
+module_platform_driver(adl_pinctrl_driver);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_DESCRIPTION("Intel Alder Lake PCH pinctrl/GPIO driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/pinctrl-elkhartlake.c b/drivers/pinctrl/intel/pinctrl-elkhartlake.c
new file mode 100644
index 000000000000..4702bdfa10e3
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-elkhartlake.c
@@ -0,0 +1,513 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel Elkhart Lake PCH pinctrl/GPIO driver
+ *
+ * Copyright (C) 2019, Intel Corporation
+ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-intel.h"
+
+#define EHL_PAD_OWN 0x020
+#define EHL_PADCFGLOCK 0x080
+#define EHL_HOSTSW_OWN 0x0b0
+#define EHL_GPI_IS 0x100
+#define EHL_GPI_IE 0x120
+
+#define EHL_GPP(r, s, e) \
+ { \
+ .reg_num = (r), \
+ .base = (s), \
+ .size = ((e) - (s) + 1), \
+ }
+
+#define EHL_COMMUNITY(s, e, g) \
+ { \
+ .padown_offset = EHL_PAD_OWN, \
+ .padcfglock_offset = EHL_PADCFGLOCK, \
+ .hostown_offset = EHL_HOSTSW_OWN, \
+ .is_offset = EHL_GPI_IS, \
+ .ie_offset = EHL_GPI_IE, \
+ .pin_base = (s), \
+ .npins = ((e) - (s) + 1), \
+ .gpps = (g), \
+ .ngpps = ARRAY_SIZE(g), \
+ }
+
+/* Elkhart Lake */
+static const struct pinctrl_pin_desc ehl_community0_pins[] = {
+ /* GPP_B */
+ PINCTRL_PIN(0, "CORE_VID_0"),
+ PINCTRL_PIN(1, "CORE_VID_1"),
+ PINCTRL_PIN(2, "VRALERTB"),
+ PINCTRL_PIN(3, "CPU_GP_2"),
+ PINCTRL_PIN(4, "CPU_GP_3"),
+ PINCTRL_PIN(5, "OSE_I2C0_SCLK"),
+ PINCTRL_PIN(6, "OSE_I2C0_SDAT"),
+ PINCTRL_PIN(7, "OSE_I2C1_SCLK"),
+ PINCTRL_PIN(8, "OSE_I2C1_SDAT"),
+ PINCTRL_PIN(9, "I2C5_SDA"),
+ PINCTRL_PIN(10, "I2C5_SCL"),
+ PINCTRL_PIN(11, "PMCALERTB"),
+ PINCTRL_PIN(12, "SLP_S0B"),
+ PINCTRL_PIN(13, "PLTRSTB"),
+ PINCTRL_PIN(14, "SPKR"),
+ PINCTRL_PIN(15, "GSPI0_CS0B"),
+ PINCTRL_PIN(16, "GSPI0_CLK"),
+ PINCTRL_PIN(17, "GSPI0_MISO"),
+ PINCTRL_PIN(18, "GSPI0_MOSI"),
+ PINCTRL_PIN(19, "GSPI1_CS0B"),
+ PINCTRL_PIN(20, "GSPI1_CLK"),
+ PINCTRL_PIN(21, "GSPI1_MISO"),
+ PINCTRL_PIN(22, "GSPI1_MOSI"),
+ PINCTRL_PIN(23, "GPPC_B_23"),
+ PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
+ PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
+ /* GPP_T */
+ PINCTRL_PIN(26, "OSE_QEPA_2"),
+ PINCTRL_PIN(27, "OSE_QEPB_2"),
+ PINCTRL_PIN(28, "OSE_QEPI_2"),
+ PINCTRL_PIN(29, "GPPC_T_3"),
+ PINCTRL_PIN(30, "RGMII0_INT"),
+ PINCTRL_PIN(31, "RGMII0_RESETB"),
+ PINCTRL_PIN(32, "RGMII0_AUXTS"),
+ PINCTRL_PIN(33, "RGMII0_PPS"),
+ PINCTRL_PIN(34, "USB2_OCB_2"),
+ PINCTRL_PIN(35, "OSE_HSUART2_EN"),
+ PINCTRL_PIN(36, "OSE_HSUART2_RE"),
+ PINCTRL_PIN(37, "USB2_OCB_3"),
+ PINCTRL_PIN(38, "OSE_UART2_RXD"),
+ PINCTRL_PIN(39, "OSE_UART2_TXD"),
+ PINCTRL_PIN(40, "OSE_UART2_RTSB"),
+ PINCTRL_PIN(41, "OSE_UART2_CTSB"),
+ /* GPP_G */
+ PINCTRL_PIN(42, "SD3_CMD"),
+ PINCTRL_PIN(43, "SD3_D0"),
+ PINCTRL_PIN(44, "SD3_D1"),
+ PINCTRL_PIN(45, "SD3_D2"),
+ PINCTRL_PIN(46, "SD3_D3"),
+ PINCTRL_PIN(47, "SD3_CDB"),
+ PINCTRL_PIN(48, "SD3_CLK"),
+ PINCTRL_PIN(49, "I2S2_SCLK"),
+ PINCTRL_PIN(50, "I2S2_SFRM"),
+ PINCTRL_PIN(51, "I2S2_TXD"),
+ PINCTRL_PIN(52, "I2S2_RXD"),
+ PINCTRL_PIN(53, "I2S3_SCLK"),
+ PINCTRL_PIN(54, "I2S3_SFRM"),
+ PINCTRL_PIN(55, "I2S3_TXD"),
+ PINCTRL_PIN(56, "I2S3_RXD"),
+ PINCTRL_PIN(57, "ESPI_IO_0"),
+ PINCTRL_PIN(58, "ESPI_IO_1"),
+ PINCTRL_PIN(59, "ESPI_IO_2"),
+ PINCTRL_PIN(60, "ESPI_IO_3"),
+ PINCTRL_PIN(61, "I2S1_SCLK"),
+ PINCTRL_PIN(62, "ESPI_CSB"),
+ PINCTRL_PIN(63, "ESPI_CLK"),
+ PINCTRL_PIN(64, "ESPI_RESETB"),
+ PINCTRL_PIN(65, "SD3_WP"),
+ PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
+};
+
+static const struct intel_padgroup ehl_community0_gpps[] = {
+ EHL_GPP(0, 0, 25), /* GPP_B */
+ EHL_GPP(1, 26, 41), /* GPP_T */
+ EHL_GPP(2, 42, 66), /* GPP_G */
+};
+
+static const struct intel_community ehl_community0[] = {
+ EHL_COMMUNITY(0, 66, ehl_community0_gpps),
+};
+
+static const struct intel_pinctrl_soc_data ehl_community0_soc_data = {
+ .uid = "0",
+ .pins = ehl_community0_pins,
+ .npins = ARRAY_SIZE(ehl_community0_pins),
+ .communities = ehl_community0,
+ .ncommunities = ARRAY_SIZE(ehl_community0),
+};
+
+static const struct pinctrl_pin_desc ehl_community1_pins[] = {
+ /* GPP_V */
+ PINCTRL_PIN(0, "EMMC_CMD"),
+ PINCTRL_PIN(1, "EMMC_DATA0"),
+ PINCTRL_PIN(2, "EMMC_DATA1"),
+ PINCTRL_PIN(3, "EMMC_DATA2"),
+ PINCTRL_PIN(4, "EMMC_DATA3"),
+ PINCTRL_PIN(5, "EMMC_DATA4"),
+ PINCTRL_PIN(6, "EMMC_DATA5"),
+ PINCTRL_PIN(7, "EMMC_DATA6"),
+ PINCTRL_PIN(8, "EMMC_DATA7"),
+ PINCTRL_PIN(9, "EMMC_RCLK"),
+ PINCTRL_PIN(10, "EMMC_CLK"),
+ PINCTRL_PIN(11, "EMMC_RESETB"),
+ PINCTRL_PIN(12, "OSE_TGPIO0"),
+ PINCTRL_PIN(13, "OSE_TGPIO1"),
+ PINCTRL_PIN(14, "OSE_TGPIO2"),
+ PINCTRL_PIN(15, "OSE_TGPIO3"),
+ /* GPP_H */
+ PINCTRL_PIN(16, "RGMII1_INT"),
+ PINCTRL_PIN(17, "RGMII1_RESETB"),
+ PINCTRL_PIN(18, "RGMII1_AUXTS"),
+ PINCTRL_PIN(19, "RGMII1_PPS"),
+ PINCTRL_PIN(20, "I2C2_SDA"),
+ PINCTRL_PIN(21, "I2C2_SCL"),
+ PINCTRL_PIN(22, "I2C3_SDA"),
+ PINCTRL_PIN(23, "I2C3_SCL"),
+ PINCTRL_PIN(24, "I2C4_SDA"),
+ PINCTRL_PIN(25, "I2C4_SCL"),
+ PINCTRL_PIN(26, "SRCCLKREQB_4"),
+ PINCTRL_PIN(27, "SRCCLKREQB_5"),
+ PINCTRL_PIN(28, "OSE_UART1_RXD"),
+ PINCTRL_PIN(29, "OSE_UART1_TXD"),
+ PINCTRL_PIN(30, "GPPC_H_14"),
+ PINCTRL_PIN(31, "OSE_UART1_CTSB"),
+ PINCTRL_PIN(32, "PCIE_LNK_DOWN"),
+ PINCTRL_PIN(33, "SD_PWR_EN_B"),
+ PINCTRL_PIN(34, "CPU_C10_GATEB"),
+ PINCTRL_PIN(35, "GPPC_H_19"),
+ PINCTRL_PIN(36, "OSE_PWM7"),
+ PINCTRL_PIN(37, "OSE_HSUART1_DE"),
+ PINCTRL_PIN(38, "OSE_HSUART1_RE"),
+ PINCTRL_PIN(39, "OSE_HSUART1_EN"),
+ /* GPP_D */
+ PINCTRL_PIN(40, "OSE_QEPA_0"),
+ PINCTRL_PIN(41, "OSE_QEPB_0"),
+ PINCTRL_PIN(42, "OSE_QEPI_0"),
+ PINCTRL_PIN(43, "OSE_PWM6"),
+ PINCTRL_PIN(44, "OSE_PWM2"),
+ PINCTRL_PIN(45, "SRCCLKREQB_0"),
+ PINCTRL_PIN(46, "SRCCLKREQB_1"),
+ PINCTRL_PIN(47, "SRCCLKREQB_2"),
+ PINCTRL_PIN(48, "SRCCLKREQB_3"),
+ PINCTRL_PIN(49, "OSE_SPI0_CSB"),
+ PINCTRL_PIN(50, "OSE_SPI0_SCLK"),
+ PINCTRL_PIN(51, "OSE_SPI0_MISO"),
+ PINCTRL_PIN(52, "OSE_SPI0_MOSI"),
+ PINCTRL_PIN(53, "OSE_QEPA_1"),
+ PINCTRL_PIN(54, "OSE_QEPB_1"),
+ PINCTRL_PIN(55, "OSE_PWM3"),
+ PINCTRL_PIN(56, "OSE_QEPI_1"),
+ PINCTRL_PIN(57, "OSE_PWM4"),
+ PINCTRL_PIN(58, "OSE_PWM5"),
+ PINCTRL_PIN(59, "I2S_MCLK1_OUT"),
+ PINCTRL_PIN(60, "GSPI2_CLK_LOOPBK"),
+ /* GPP_U */
+ PINCTRL_PIN(61, "RGMII2_INT"),
+ PINCTRL_PIN(62, "RGMII2_RESETB"),
+ PINCTRL_PIN(63, "RGMII2_PPS"),
+ PINCTRL_PIN(64, "RGMII2_AUXTS"),
+ PINCTRL_PIN(65, "ISI_SPIM_CS"),
+ PINCTRL_PIN(66, "ISI_SPIM_SCLK"),
+ PINCTRL_PIN(67, "ISI_SPIM_MISO"),
+ PINCTRL_PIN(68, "OSE_QEPA_3"),
+ PINCTRL_PIN(69, "ISI_SPIS_CS"),
+ PINCTRL_PIN(70, "ISI_SPIS_SCLK"),
+ PINCTRL_PIN(71, "ISI_SPIS_MISO"),
+ PINCTRL_PIN(72, "OSE_QEPB_3"),
+ PINCTRL_PIN(73, "ISI_CHX_OKNOK_0"),
+ PINCTRL_PIN(74, "ISI_CHX_OKNOK_1"),
+ PINCTRL_PIN(75, "ISI_CHX_RLY_SWTCH"),
+ PINCTRL_PIN(76, "ISI_CHX_PMIC_EN"),
+ PINCTRL_PIN(77, "ISI_OKNOK_0"),
+ PINCTRL_PIN(78, "ISI_OKNOK_1"),
+ PINCTRL_PIN(79, "ISI_ALERT"),
+ PINCTRL_PIN(80, "OSE_QEPI_3"),
+ PINCTRL_PIN(81, "GSPI3_CLK_LOOPBK"),
+ PINCTRL_PIN(82, "GSPI4_CLK_LOOPBK"),
+ PINCTRL_PIN(83, "GSPI5_CLK_LOOPBK"),
+ PINCTRL_PIN(84, "GSPI6_CLK_LOOPBK"),
+ /* vGPIO */
+ PINCTRL_PIN(85, "CNV_BTEN"),
+ PINCTRL_PIN(86, "CNV_BT_HOST_WAKEB"),
+ PINCTRL_PIN(87, "CNV_BT_IF_SELECT"),
+ PINCTRL_PIN(88, "vCNV_BT_UART_TXD"),
+ PINCTRL_PIN(89, "vCNV_BT_UART_RXD"),
+ PINCTRL_PIN(90, "vCNV_BT_UART_CTS_B"),
+ PINCTRL_PIN(91, "vCNV_BT_UART_RTS_B"),
+ PINCTRL_PIN(92, "vCNV_MFUART1_TXD"),
+ PINCTRL_PIN(93, "vCNV_MFUART1_RXD"),
+ PINCTRL_PIN(94, "vCNV_MFUART1_CTS_B"),
+ PINCTRL_PIN(95, "vCNV_MFUART1_RTS_B"),
+ PINCTRL_PIN(96, "vUART0_TXD"),
+ PINCTRL_PIN(97, "vUART0_RXD"),
+ PINCTRL_PIN(98, "vUART0_CTS_B"),
+ PINCTRL_PIN(99, "vUART0_RTS_B"),
+ PINCTRL_PIN(100, "vOSE_UART0_TXD"),
+ PINCTRL_PIN(101, "vOSE_UART0_RXD"),
+ PINCTRL_PIN(102, "vOSE_UART0_CTS_B"),
+ PINCTRL_PIN(103, "vOSE_UART0_RTS_B"),
+ PINCTRL_PIN(104, "vCNV_BT_I2S_BCLK"),
+ PINCTRL_PIN(105, "vCNV_BT_I2S_WS_SYNC"),
+ PINCTRL_PIN(106, "vCNV_BT_I2S_SDO"),
+ PINCTRL_PIN(107, "vCNV_BT_I2S_SDI"),
+ PINCTRL_PIN(108, "vI2S2_SCLK"),
+ PINCTRL_PIN(109, "vI2S2_SFRM"),
+ PINCTRL_PIN(110, "vI2S2_TXD"),
+ PINCTRL_PIN(111, "vI2S2_RXD"),
+ PINCTRL_PIN(112, "vSD3_CD_B"),
+};
+
+static const struct intel_padgroup ehl_community1_gpps[] = {
+ EHL_GPP(0, 0, 15), /* GPP_V */
+ EHL_GPP(1, 16, 39), /* GPP_H */
+ EHL_GPP(2, 40, 60), /* GPP_D */
+ EHL_GPP(3, 61, 84), /* GPP_U */
+ EHL_GPP(4, 85, 112), /* vGPIO */
+};
+
+static const struct intel_community ehl_community1[] = {
+ EHL_COMMUNITY(0, 112, ehl_community1_gpps),
+};
+
+static const struct intel_pinctrl_soc_data ehl_community1_soc_data = {
+ .uid = "1",
+ .pins = ehl_community1_pins,
+ .npins = ARRAY_SIZE(ehl_community1_pins),
+ .communities = ehl_community1,
+ .ncommunities = ARRAY_SIZE(ehl_community1),
+};
+
+static const struct pinctrl_pin_desc ehl_community3_pins[] = {
+ /* CPU */
+ PINCTRL_PIN(0, "HDACPU_SDI"),
+ PINCTRL_PIN(1, "HDACPU_SDO"),
+ PINCTRL_PIN(2, "HDACPU_BCLK"),
+ PINCTRL_PIN(3, "PM_SYNC"),
+ PINCTRL_PIN(4, "PECI"),
+ PINCTRL_PIN(5, "CPUPWRGD"),
+ PINCTRL_PIN(6, "THRMTRIPB"),
+ PINCTRL_PIN(7, "PLTRST_CPUB"),
+ PINCTRL_PIN(8, "PM_DOWN"),
+ PINCTRL_PIN(9, "TRIGGER_IN"),
+ PINCTRL_PIN(10, "TRIGGER_OUT"),
+ PINCTRL_PIN(11, "UFS_RESETB"),
+ PINCTRL_PIN(12, "CLKOUT_CPURTC"),
+ PINCTRL_PIN(13, "VCCST_OVERRIDE"),
+ PINCTRL_PIN(14, "C10_WAKE"),
+ PINCTRL_PIN(15, "PROCHOTB"),
+ PINCTRL_PIN(16, "CATERRB"),
+ /* GPP_S */
+ PINCTRL_PIN(17, "UFS_REF_CLK_0"),
+ PINCTRL_PIN(18, "UFS_REF_CLK_1"),
+ /* GPP_A */
+ PINCTRL_PIN(19, "RGMII0_TXDATA_3"),
+ PINCTRL_PIN(20, "RGMII0_TXDATA_2"),
+ PINCTRL_PIN(21, "RGMII0_TXDATA_1"),
+ PINCTRL_PIN(22, "RGMII0_TXDATA_0"),
+ PINCTRL_PIN(23, "RGMII0_TXCLK"),
+ PINCTRL_PIN(24, "RGMII0_TXCTL"),
+ PINCTRL_PIN(25, "RGMII0_RXCLK"),
+ PINCTRL_PIN(26, "RGMII0_RXDATA_3"),
+ PINCTRL_PIN(27, "RGMII0_RXDATA_2"),
+ PINCTRL_PIN(28, "RGMII0_RXDATA_1"),
+ PINCTRL_PIN(29, "RGMII0_RXDATA_0"),
+ PINCTRL_PIN(30, "RGMII1_TXDATA_3"),
+ PINCTRL_PIN(31, "RGMII1_TXDATA_2"),
+ PINCTRL_PIN(32, "RGMII1_TXDATA_1"),
+ PINCTRL_PIN(33, "RGMII1_TXDATA_0"),
+ PINCTRL_PIN(34, "RGMII1_TXCLK"),
+ PINCTRL_PIN(35, "RGMII1_TXCTL"),
+ PINCTRL_PIN(36, "RGMII1_RXCLK"),
+ PINCTRL_PIN(37, "RGMII1_RXCTL"),
+ PINCTRL_PIN(38, "RGMII1_RXDATA_3"),
+ PINCTRL_PIN(39, "RGMII1_RXDATA_2"),
+ PINCTRL_PIN(40, "RGMII1_RXDATA_1"),
+ PINCTRL_PIN(41, "RGMII1_RXDATA_0"),
+ PINCTRL_PIN(42, "RGMII0_RXCTL"),
+ /* vGPIO_3 */
+ PINCTRL_PIN(43, "ESPI_USB_OCB_0"),
+ PINCTRL_PIN(44, "ESPI_USB_OCB_1"),
+ PINCTRL_PIN(45, "ESPI_USB_OCB_2"),
+ PINCTRL_PIN(46, "ESPI_USB_OCB_3"),
+};
+
+static const struct intel_padgroup ehl_community3_gpps[] = {
+ EHL_GPP(0, 0, 16), /* CPU */
+ EHL_GPP(1, 17, 18), /* GPP_S */
+ EHL_GPP(2, 19, 42), /* GPP_A */
+ EHL_GPP(3, 43, 46), /* vGPIO_3 */
+};
+
+static const struct intel_community ehl_community3[] = {
+ EHL_COMMUNITY(0, 46, ehl_community3_gpps),
+};
+
+static const struct intel_pinctrl_soc_data ehl_community3_soc_data = {
+ .uid = "3",
+ .pins = ehl_community3_pins,
+ .npins = ARRAY_SIZE(ehl_community3_pins),
+ .communities = ehl_community3,
+ .ncommunities = ARRAY_SIZE(ehl_community3),
+};
+
+static const struct pinctrl_pin_desc ehl_community4_pins[] = {
+ /* GPP_C */
+ PINCTRL_PIN(0, "SMBCLK"),
+ PINCTRL_PIN(1, "SMBDATA"),
+ PINCTRL_PIN(2, "OSE_PWM0"),
+ PINCTRL_PIN(3, "RGMII0_MDC"),
+ PINCTRL_PIN(4, "RGMII0_MDIO"),
+ PINCTRL_PIN(5, "OSE_PWM1"),
+ PINCTRL_PIN(6, "RGMII1_MDC"),
+ PINCTRL_PIN(7, "RGMII1_MDIO"),
+ PINCTRL_PIN(8, "OSE_TGPIO4"),
+ PINCTRL_PIN(9, "OSE_HSUART0_EN"),
+ PINCTRL_PIN(10, "OSE_TGPIO5"),
+ PINCTRL_PIN(11, "OSE_HSUART0_RE"),
+ PINCTRL_PIN(12, "OSE_UART0_RXD"),
+ PINCTRL_PIN(13, "OSE_UART0_TXD"),
+ PINCTRL_PIN(14, "OSE_UART0_RTSB"),
+ PINCTRL_PIN(15, "OSE_UART0_CTSB"),
+ PINCTRL_PIN(16, "RGMII2_MDIO"),
+ PINCTRL_PIN(17, "RGMII2_MDC"),
+ PINCTRL_PIN(18, "OSE_I2C4_SDAT"),
+ PINCTRL_PIN(19, "OSE_I2C4_SCLK"),
+ PINCTRL_PIN(20, "OSE_UART4_RXD"),
+ PINCTRL_PIN(21, "OSE_UART4_TXD"),
+ PINCTRL_PIN(22, "OSE_UART4_RTSB"),
+ PINCTRL_PIN(23, "OSE_UART4_CTSB"),
+ /* GPP_F */
+ PINCTRL_PIN(24, "CNV_BRI_DT"),
+ PINCTRL_PIN(25, "CNV_BRI_RSP"),
+ PINCTRL_PIN(26, "CNV_RGI_DT"),
+ PINCTRL_PIN(27, "CNV_RGI_RSP"),
+ PINCTRL_PIN(28, "CNV_RF_RESET_B"),
+ PINCTRL_PIN(29, "EMMC_HIP_MON"),
+ PINCTRL_PIN(30, "CNV_PA_BLANKING"),
+ PINCTRL_PIN(31, "OSE_I2S1_SCLK"),
+ PINCTRL_PIN(32, "I2S_MCLK2_INOUT"),
+ PINCTRL_PIN(33, "BOOTMPC"),
+ PINCTRL_PIN(34, "OSE_I2S1_SFRM"),
+ PINCTRL_PIN(35, "GPPC_F_11"),
+ PINCTRL_PIN(36, "GSXDOUT"),
+ PINCTRL_PIN(37, "GSXSLOAD"),
+ PINCTRL_PIN(38, "GSXDIN"),
+ PINCTRL_PIN(39, "GSXSRESETB"),
+ PINCTRL_PIN(40, "GSXCLK"),
+ PINCTRL_PIN(41, "GPPC_F_17"),
+ PINCTRL_PIN(42, "OSE_I2S1_TXD"),
+ PINCTRL_PIN(43, "OSE_I2S1_RXD"),
+ PINCTRL_PIN(44, "EXT_PWR_GATEB"),
+ PINCTRL_PIN(45, "EXT_PWR_GATE2B"),
+ PINCTRL_PIN(46, "VNN_CTRL"),
+ PINCTRL_PIN(47, "V1P05_CTRL"),
+ PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"),
+ /* HVCMOS */
+ PINCTRL_PIN(49, "L_BKLTEN"),
+ PINCTRL_PIN(50, "L_BKLTCTL"),
+ PINCTRL_PIN(51, "L_VDDEN"),
+ PINCTRL_PIN(52, "SYS_PWROK"),
+ PINCTRL_PIN(53, "SYS_RESETB"),
+ PINCTRL_PIN(54, "MLK_RSTB"),
+ /* GPP_E */
+ PINCTRL_PIN(55, "SATA_LEDB"),
+ PINCTRL_PIN(56, "GPPC_E_1"),
+ PINCTRL_PIN(57, "GPPC_E_2"),
+ PINCTRL_PIN(58, "DDSP_HPD_B"),
+ PINCTRL_PIN(59, "SATA_DEVSLP_0"),
+ PINCTRL_PIN(60, "DDPB_CTRLDATA"),
+ PINCTRL_PIN(61, "GPPC_E_6"),
+ PINCTRL_PIN(62, "DDPB_CTRLCLK"),
+ PINCTRL_PIN(63, "GPPC_E_8"),
+ PINCTRL_PIN(64, "USB2_OCB_0"),
+ PINCTRL_PIN(65, "GPPC_E_10"),
+ PINCTRL_PIN(66, "GPPC_E_11"),
+ PINCTRL_PIN(67, "GPPC_E_12"),
+ PINCTRL_PIN(68, "GPPC_E_13"),
+ PINCTRL_PIN(69, "DDSP_HPD_A"),
+ PINCTRL_PIN(70, "OSE_I2S0_RXD"),
+ PINCTRL_PIN(71, "OSE_I2S0_TXD"),
+ PINCTRL_PIN(72, "DDSP_HPD_C"),
+ PINCTRL_PIN(73, "DDPA_CTRLDATA"),
+ PINCTRL_PIN(74, "DDPA_CTRLCLK"),
+ PINCTRL_PIN(75, "OSE_I2S0_SCLK"),
+ PINCTRL_PIN(76, "OSE_I2S0_SFRM"),
+ PINCTRL_PIN(77, "DDPC_CTRLDATA"),
+ PINCTRL_PIN(78, "DDPC_CTRLCLK"),
+ PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"),
+};
+
+static const struct intel_padgroup ehl_community4_gpps[] = {
+ EHL_GPP(0, 0, 23), /* GPP_C */
+ EHL_GPP(1, 24, 48), /* GPP_F */
+ EHL_GPP(2, 49, 54), /* HVCMOS */
+ EHL_GPP(3, 55, 79), /* GPP_E */
+};
+
+static const struct intel_community ehl_community4[] = {
+ EHL_COMMUNITY(0, 79, ehl_community4_gpps),
+};
+
+static const struct intel_pinctrl_soc_data ehl_community4_soc_data = {
+ .uid = "4",
+ .pins = ehl_community4_pins,
+ .npins = ARRAY_SIZE(ehl_community4_pins),
+ .communities = ehl_community4,
+ .ncommunities = ARRAY_SIZE(ehl_community4),
+};
+
+static const struct pinctrl_pin_desc ehl_community5_pins[] = {
+ /* GPP_R */
+ PINCTRL_PIN(0, "HDA_BCLK"),
+ PINCTRL_PIN(1, "HDA_SYNC"),
+ PINCTRL_PIN(2, "HDA_SDO"),
+ PINCTRL_PIN(3, "HDA_SDI_0"),
+ PINCTRL_PIN(4, "HDA_RSTB"),
+ PINCTRL_PIN(5, "HDA_SDI_1"),
+ PINCTRL_PIN(6, "GPP_R_6"),
+ PINCTRL_PIN(7, "GPP_R_7"),
+};
+
+static const struct intel_padgroup ehl_community5_gpps[] = {
+ EHL_GPP(0, 0, 7), /* GPP_R */
+};
+
+static const struct intel_community ehl_community5[] = {
+ EHL_COMMUNITY(0, 7, ehl_community5_gpps),
+};
+
+static const struct intel_pinctrl_soc_data ehl_community5_soc_data = {
+ .uid = "5",
+ .pins = ehl_community5_pins,
+ .npins = ARRAY_SIZE(ehl_community5_pins),
+ .communities = ehl_community5,
+ .ncommunities = ARRAY_SIZE(ehl_community5),
+};
+
+static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = {
+ &ehl_community0_soc_data,
+ &ehl_community1_soc_data,
+ &ehl_community3_soc_data,
+ &ehl_community4_soc_data,
+ &ehl_community5_soc_data,
+ NULL
+};
+
+static const struct acpi_device_id ehl_pinctrl_acpi_match[] = {
+ { "INTC1020", (kernel_ulong_t)ehl_soc_data_array },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, ehl_pinctrl_acpi_match);
+
+static INTEL_PINCTRL_PM_OPS(ehl_pinctrl_pm_ops);
+
+static struct platform_driver ehl_pinctrl_driver = {
+ .probe = intel_pinctrl_probe_by_uid,
+ .driver = {
+ .name = "elkhartlake-pinctrl",
+ .acpi_match_table = ehl_pinctrl_acpi_match,
+ .pm = &ehl_pinctrl_pm_ops,
+ },
+};
+
+module_platform_driver(ehl_pinctrl_driver);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_DESCRIPTION("Intel Elkhart Lake PCH pinctrl/GPIO driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/pinctrl-lakefield.c b/drivers/pinctrl/intel/pinctrl-lakefield.c
new file mode 100644
index 000000000000..3c6283c4827f
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-lakefield.c
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel Lakefield PCH pinctrl/GPIO driver
+ *
+ * Copyright (C) 2020, Intel Corporation
+ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-intel.h"
+
+#define LKF_PAD_OWN 0x020
+#define LKF_PADCFGLOCK 0x070
+#define LKF_HOSTSW_OWN 0x090
+#define LKF_GPI_IS 0x100
+#define LKF_GPI_IE 0x110
+
+#define LKF_GPP(r, s, e, g) \
+ { \
+ .reg_num = (r), \
+ .base = (s), \
+ .size = ((e) - (s) + 1), \
+ .gpio_base = (g), \
+ }
+
+#define LKF_COMMUNITY(b, s, e, g) \
+ { \
+ .barno = (b), \
+ .padown_offset = LKF_PAD_OWN, \
+ .padcfglock_offset = LKF_PADCFGLOCK, \
+ .hostown_offset = LKF_HOSTSW_OWN, \
+ .is_offset = LKF_GPI_IS, \
+ .ie_offset = LKF_GPI_IE, \
+ .pin_base = (s), \
+ .npins = ((e) - (s) + 1), \
+ .gpps = (g), \
+ .ngpps = ARRAY_SIZE(g), \
+ }
+
+/* Lakefield */
+static const struct pinctrl_pin_desc lkf_pins[] = {
+ /* EAST */
+ PINCTRL_PIN(0, "MDSI_A_TE0"),
+ PINCTRL_PIN(1, "MDSI_A_TE1"),
+ PINCTRL_PIN(2, "PANEL0_AVDD_EN"),
+ PINCTRL_PIN(3, "PANEL0_BKLTEN"),
+ PINCTRL_PIN(4, "PANEL0_BKLTCTL"),
+ PINCTRL_PIN(5, "PANEL1_AVDD_EN"),
+ PINCTRL_PIN(6, "PANEL1_BKLTEN"),
+ PINCTRL_PIN(7, "PANEL1_BKLTCTL"),
+ PINCTRL_PIN(8, "THC0_SPI1_IO_0"),
+ PINCTRL_PIN(9, "THC0_SPI1_IO_1"),
+ PINCTRL_PIN(10, "THC0_SPI1_IO_2"),
+ PINCTRL_PIN(11, "THC0_SPI1_IO_3"),
+ PINCTRL_PIN(12, "THC0_SPI1_CSB"),
+ PINCTRL_PIN(13, "THC0_SPI1_CLK"),
+ PINCTRL_PIN(14, "THC0_SPI1_RESETB"),
+ PINCTRL_PIN(15, "THC0_SPI1_CLK_FB"),
+ PINCTRL_PIN(16, "SPI_TOUCH_CLK_FB"),
+ PINCTRL_PIN(17, "THC1_SPI2_IO_0"),
+ PINCTRL_PIN(18, "THC1_SPI2_IO_1"),
+ PINCTRL_PIN(19, "THC1_SPI2_IO_2"),
+ PINCTRL_PIN(20, "THC1_SPI2_IO_3"),
+ PINCTRL_PIN(21, "THC1_SPI2_CSB"),
+ PINCTRL_PIN(22, "THC1_SPI2_CLK"),
+ PINCTRL_PIN(23, "THC1_SPI2_RESETB"),
+ PINCTRL_PIN(24, "THC1_SPI2_CLK_FB"),
+ PINCTRL_PIN(25, "eSPI_IO_0"),
+ PINCTRL_PIN(26, "eSPI_IO_1"),
+ PINCTRL_PIN(27, "eSPI_IO_2"),
+ PINCTRL_PIN(28, "eSPI_IO_3"),
+ PINCTRL_PIN(29, "eSPI_CSB"),
+ PINCTRL_PIN(30, "eSPI_RESETB"),
+ PINCTRL_PIN(31, "eSPI_CLK"),
+ PINCTRL_PIN(32, "eSPI_CLK_FB"),
+ PINCTRL_PIN(33, "FAST_SPI0_IO_0"),
+ PINCTRL_PIN(34, "FAST_SPI0_IO_1"),
+ PINCTRL_PIN(35, "FAST_SPI0_IO_2"),
+ PINCTRL_PIN(36, "FAST_SPI0_IO_3"),
+ PINCTRL_PIN(37, "FAST_SPI0_CSB_0"),
+ PINCTRL_PIN(38, "FAST_SPI0_CSB_2"),
+ PINCTRL_PIN(39, "FAST_SPI0_CLK"),
+ PINCTRL_PIN(40, "FAST_SPI_CLK_FB"),
+ PINCTRL_PIN(41, "FAST_SPI0_CSB_1"),
+ PINCTRL_PIN(42, "ISH_GP_12"),
+ PINCTRL_PIN(43, "THC0_SPI1_INTB"),
+ PINCTRL_PIN(44, "THC1_SPI2_INTB"),
+ PINCTRL_PIN(45, "PANEL0_AVEE_EN"),
+ PINCTRL_PIN(46, "PANEL0_VIO_EN"),
+ PINCTRL_PIN(47, "PANEL1_AVEE_EN"),
+ PINCTRL_PIN(48, "PANEL1_VIO_EN"),
+ PINCTRL_PIN(49, "PANEL0_RESET"),
+ PINCTRL_PIN(50, "PANEL1_RESET"),
+ PINCTRL_PIN(51, "ISH_GP_15"),
+ PINCTRL_PIN(52, "ISH_GP_16"),
+ PINCTRL_PIN(53, "ISH_GP_17"),
+ PINCTRL_PIN(54, "ISH_GP_18"),
+ PINCTRL_PIN(55, "ISH_GP_19"),
+ PINCTRL_PIN(56, "ISH_GP_20"),
+ PINCTRL_PIN(57, "ISH_GP_21"),
+ PINCTRL_PIN(58, "ISH_GP_22"),
+ PINCTRL_PIN(59, "ISH_GP_23"),
+ /* NORTHWEST */
+ PINCTRL_PIN(60, "MCSI_GPIO_0"),
+ PINCTRL_PIN(61, "MCSI_GPIO_1"),
+ PINCTRL_PIN(62, "MCSI_GPIO_2"),
+ PINCTRL_PIN(63, "MCSI_GPIO_3"),
+ PINCTRL_PIN(64, "LPSS_I2C0_SDA"),
+ PINCTRL_PIN(65, "LPSS_I2C0_SCL"),
+ PINCTRL_PIN(66, "LPSS_I2C1_SDA"),
+ PINCTRL_PIN(67, "LPSS_I2C1_SCL"),
+ PINCTRL_PIN(68, "LPSS_I2C2_SDA"),
+ PINCTRL_PIN(69, "LPSS_I2C2_SCL"),
+ PINCTRL_PIN(70, "LPSS_I2C3_SDA"),
+ PINCTRL_PIN(71, "LPSS_I2C3_SCL"),
+ PINCTRL_PIN(72, "LPSS_I2C4_SDA"),
+ PINCTRL_PIN(73, "LPSS_I2C4_SCL"),
+ PINCTRL_PIN(74, "LPSS_I2C5_SDA"),
+ PINCTRL_PIN(75, "LPSS_I2C5_SCL"),
+ PINCTRL_PIN(76, "LPSS_I3C0_SDA"),
+ PINCTRL_PIN(77, "LPSS_I3C0_SCL"),
+ PINCTRL_PIN(78, "LPSS_I3C0_SCL_FB"),
+ PINCTRL_PIN(79, "LPSS_I3C1_SDA"),
+ PINCTRL_PIN(80, "LPSS_I3C1_SCL"),
+ PINCTRL_PIN(81, "LPSS_I3C1_SCL_FB"),
+ PINCTRL_PIN(82, "ISH_I2C0_SDA"),
+ PINCTRL_PIN(83, "ISH_I2C0_SCL"),
+ PINCTRL_PIN(84, "ISH_I2C1_SCL"),
+ PINCTRL_PIN(85, "ISH_I2C1_SDA"),
+ PINCTRL_PIN(86, "DBG_PMODE"),
+ PINCTRL_PIN(87, "BJTAG_TCK"),
+ PINCTRL_PIN(88, "BJTAG_TDI"),
+ PINCTRL_PIN(89, "BJTAGX"),
+ PINCTRL_PIN(90, "BPREQ_B"),
+ PINCTRL_PIN(91, "BJTAG_TMS"),
+ PINCTRL_PIN(92, "BPRDY_B"),
+ PINCTRL_PIN(93, "BJTAG_TDO"),
+ PINCTRL_PIN(94, "BJTAG_TRST_B_0"),
+ PINCTRL_PIN(95, "ISH_I3C0_SDA"),
+ PINCTRL_PIN(96, "ISH_I3C0_SCL"),
+ PINCTRL_PIN(97, "ISH_I3C0_SCL_FB"),
+ PINCTRL_PIN(98, "AVS_I2S_BCLK_0"),
+ PINCTRL_PIN(99, "AVS_I2S_MCLK_0"),
+ PINCTRL_PIN(100, "AVS_I2S_SFRM_0"),
+ PINCTRL_PIN(101, "AVS_I2S_RXD_0"),
+ PINCTRL_PIN(102, "AVS_I2S_TXD_0"),
+ PINCTRL_PIN(103, "AVS_I2S_BCLK_1"),
+ PINCTRL_PIN(104, "AVS_I2S_SFRM_1"),
+ PINCTRL_PIN(105, "AVS_I2S_RXD_1"),
+ PINCTRL_PIN(106, "AVS_I2S_TXD_1"),
+ PINCTRL_PIN(107, "AVS_I2S_BCLK_2"),
+ PINCTRL_PIN(108, "AVS_I2S_SFRM_2"),
+ PINCTRL_PIN(109, "AVS_I2S_RXD_2"),
+ PINCTRL_PIN(110, "AVS_I2S_TXD_2"),
+ PINCTRL_PIN(111, "AVS_I2S_BCLK_3"),
+ PINCTRL_PIN(112, "AVS_I2S_SFRM_3"),
+ PINCTRL_PIN(113, "AVS_I2S_RXD_3"),
+ PINCTRL_PIN(114, "AVS_I2S_TXD_3"),
+ PINCTRL_PIN(115, "AVS_I2S_BCLK_4"),
+ PINCTRL_PIN(116, "AVS_I2S_SFRM_4"),
+ PINCTRL_PIN(117, "AVS_I2S_RXD_4"),
+ PINCTRL_PIN(118, "AVS_I2S_TXD_4"),
+ PINCTRL_PIN(119, "AVS_I2S_SFRM_5"),
+ PINCTRL_PIN(120, "AVS_I2S_RXD_5"),
+ PINCTRL_PIN(121, "AVS_I2S_TXD_5"),
+ PINCTRL_PIN(122, "AVS_I2S_BCLK_5"),
+ PINCTRL_PIN(123, "AVS_SNDW_CLK_0"),
+ PINCTRL_PIN(124, "AVS_SNDW_DATA_0"),
+ PINCTRL_PIN(125, "AVS_SNDW_CLK_1"),
+ PINCTRL_PIN(126, "AVS_SNDW_DATA_1"),
+ PINCTRL_PIN(127, "AVS_SNDW_CLK_2"),
+ PINCTRL_PIN(128, "AVS_SNDW_DATA_2"),
+ PINCTRL_PIN(129, "AVS_SNDW_CLK_3"),
+ PINCTRL_PIN(130, "AVS_SNDW_DATA_3"),
+ PINCTRL_PIN(131, "VISA_PTI_CH0_D0_internal"),
+ PINCTRL_PIN(132, "VISA_PTI_CH0_D1_internal"),
+ PINCTRL_PIN(133, "VISA_PTI_CH0_D2_internal"),
+ PINCTRL_PIN(134, "VISA_PTI_CH0_D3_internal"),
+ PINCTRL_PIN(135, "VISA_PTI_CH0_D4_internal"),
+ PINCTRL_PIN(136, "VISA_PTI_CH0_D5_internal"),
+ PINCTRL_PIN(137, "VISA_PTI_CH0_D6_internal"),
+ PINCTRL_PIN(138, "VISA_PTI_CH0_D7_internal"),
+ PINCTRL_PIN(139, "VISA_PTI_CH0_CLK_internal"),
+ PINCTRL_PIN(140, "VISA_PTI_CH1_D0_internal"),
+ PINCTRL_PIN(141, "VISA_PTI_CH1_D1_internal"),
+ PINCTRL_PIN(142, "VISA_PTI_CH1_D2_internal"),
+ PINCTRL_PIN(143, "VISA_PTI_CH1_D3_internal"),
+ PINCTRL_PIN(144, "VISA_PTI_CH1_D4_internal"),
+ PINCTRL_PIN(145, "VISA_PTI_CH1_D5_internal"),
+ PINCTRL_PIN(146, "VISA_PTI_CH1_D6_internal"),
+ PINCTRL_PIN(147, "VISA_PTI_CH1_D7_internal"),
+ PINCTRL_PIN(148, "VISA_PTI_CH1_CLK_internal"),
+ /* WEST */
+ PINCTRL_PIN(149, "LPSS_UART0_TXD"),
+ PINCTRL_PIN(150, "LPSS_UART0_RXD"),
+ PINCTRL_PIN(151, "LPSS_UART0_RTS_B"),
+ PINCTRL_PIN(152, "LPSS_UART0_CTS_B"),
+ PINCTRL_PIN(153, "LPSS_UART1_RXD"),
+ PINCTRL_PIN(154, "LPSS_UART1_TXD"),
+ PINCTRL_PIN(155, "LPSS_UART1_RTS_B"),
+ PINCTRL_PIN(156, "LPSS_UART1_CTS_B"),
+ PINCTRL_PIN(157, "ISH_UART0_RXD"),
+ PINCTRL_PIN(158, "ISH_UART0_TXD"),
+ PINCTRL_PIN(159, "ISH_UART0_RTSB"),
+ PINCTRL_PIN(160, "ISH_UART0_CTSB"),
+ PINCTRL_PIN(161, "LPSS_SSP_0_CLK"),
+ PINCTRL_PIN(162, "LPSS_SSP_0_CLK_FB"),
+ PINCTRL_PIN(163, "LPSS_SSP_0_FS0"),
+ PINCTRL_PIN(164, "LPSS_SSP_0_FS1"),
+ PINCTRL_PIN(165, "LPSS_SSP_0_RXD"),
+ PINCTRL_PIN(166, "LPSS_SSP_0_TXD"),
+ PINCTRL_PIN(167, "ISH_UART1_RXD"),
+ PINCTRL_PIN(168, "ISH_UART1_TXD"),
+ PINCTRL_PIN(169, "ISH_UART1_RTSB"),
+ PINCTRL_PIN(170, "ISH_UART1_CTSB"),
+ PINCTRL_PIN(171, "LPSS_SSP_1_FS0"),
+ PINCTRL_PIN(172, "LPSS_SSP_1_FS1"),
+ PINCTRL_PIN(173, "LPSS_SSP_1_CLK"),
+ PINCTRL_PIN(174, "LPSS_SSP_1_CLK_FB"),
+ PINCTRL_PIN(175, "LPSS_SSP_1_RXD"),
+ PINCTRL_PIN(176, "LPSS_SSP_1_TXD"),
+ PINCTRL_PIN(177, "LPSS_SSP_2_CLK"),
+ PINCTRL_PIN(178, "LPSS_SSP_2_CLK_FB"),
+ PINCTRL_PIN(179, "LPSS_SSP_2_FS0"),
+ PINCTRL_PIN(180, "LPSS_SSP_2_FS1"),
+ PINCTRL_PIN(181, "LPSS_SSP_2_RXD"),
+ PINCTRL_PIN(182, "LPSS_SSP_2_TXD"),
+ PINCTRL_PIN(183, "ISH_SPI0_CSB0"),
+ PINCTRL_PIN(184, "ISH_SPI0_CSB1"),
+ PINCTRL_PIN(185, "ISH_SPI0_CLK"),
+ PINCTRL_PIN(186, "ISH_SPI0_MISO"),
+ PINCTRL_PIN(187, "ISH_SPI0_MOSI"),
+ PINCTRL_PIN(188, "ISH_GP_0"),
+ PINCTRL_PIN(189, "ISH_GP_1"),
+ PINCTRL_PIN(190, "ISH_GP_2"),
+ PINCTRL_PIN(191, "ISH_GP_13"),
+ PINCTRL_PIN(192, "ISH_GP_3"),
+ PINCTRL_PIN(193, "ISH_GP_4"),
+ PINCTRL_PIN(194, "ISH_GP_5"),
+ PINCTRL_PIN(195, "ISH_GP_6"),
+ PINCTRL_PIN(196, "ISH_GP_7"),
+ PINCTRL_PIN(197, "ISH_GP_8"),
+ PINCTRL_PIN(198, "ISH_GP_9"),
+ PINCTRL_PIN(199, "ISH_GP_10"),
+ PINCTRL_PIN(200, "ISH_GP_11"),
+ PINCTRL_PIN(201, "ISH_GP_14"),
+ PINCTRL_PIN(202, "ISH_GP_15"),
+ PINCTRL_PIN(203, "ISH_GP_22"),
+ PINCTRL_PIN(204, "ISH_GP_12"),
+ PINCTRL_PIN(205, "ISH_GP_30_USB_OC"),
+ PINCTRL_PIN(206, "LPDDRx_RESET0_n"),
+ PINCTRL_PIN(207, "UFS_RESET_B"),
+ PINCTRL_PIN(208, "UFS_REFCLK0"),
+ PINCTRL_PIN(209, "EMMC_SD_CLK"),
+ PINCTRL_PIN(210, "EMMC_SD_D0"),
+ PINCTRL_PIN(211, "EMMC_SD_D1"),
+ PINCTRL_PIN(212, "EMMC_SD_D2"),
+ PINCTRL_PIN(213, "EMMC_SD_D3"),
+ PINCTRL_PIN(214, "EMMC_D4"),
+ PINCTRL_PIN(215, "EMMC_D5"),
+ PINCTRL_PIN(216, "EMMC_D6"),
+ PINCTRL_PIN(217, "EMMC_D7"),
+ PINCTRL_PIN(218, "EMMC_SD_CMD"),
+ PINCTRL_PIN(219, "EMMC_RCLK"),
+ PINCTRL_PIN(220, "SDCARD_CLK_FB"),
+ PINCTRL_PIN(221, "SD_Virtual_GPIO"),
+ PINCTRL_PIN(222, "OSC_CLK_OUT_NFC"),
+ PINCTRL_PIN(223, "OSC_CLK_OUT_CAM_0"),
+ PINCTRL_PIN(224, "OSC_CLK_OUT_CAM_1"),
+ PINCTRL_PIN(225, "OSC_CLK_OUT_CAM_2"),
+ PINCTRL_PIN(226, "OSC_CLK_OUT_CAM_3"),
+ PINCTRL_PIN(227, "PCIe_LINKDOWN"),
+ PINCTRL_PIN(228, "NFC_CLK_REQ"),
+ PINCTRL_PIN(229, "PCIE_CLKREQ_N_DEV2"),
+ PINCTRL_PIN(230, "PCIE_CLKREQ_N_DEV3"),
+ PINCTRL_PIN(231, "PCIE_CLKREQ_N_DEV4"),
+ PINCTRL_PIN(232, "PCIE_CLKREQ_N_DEV1"),
+ PINCTRL_PIN(233, "PCIE_CLKREQ_N_DEV0"),
+ PINCTRL_PIN(234, "GMBUS_1_SCL"),
+ PINCTRL_PIN(235, "GMBUS_1_SDA"),
+ PINCTRL_PIN(236, "GMBUS_0_SCL"),
+ PINCTRL_PIN(237, "GMBUS_0_SDA"),
+ /* SOUTHEAST */
+ PINCTRL_PIN(238, "COMPUTE_PMIC_SVID_DATA"),
+ PINCTRL_PIN(239, "COMPUTE_PMIC_SVID_CLK"),
+ PINCTRL_PIN(240, "COMPUTE_PMIC_SVID_ALERT_B"),
+ PINCTRL_PIN(241, "ROP_PMIC_I2C_SCL"),
+ PINCTRL_PIN(242, "ROP_PMIC_I2C_SDA"),
+ PINCTRL_PIN(243, "ISH_TYPEC_I2C2_SDA"),
+ PINCTRL_PIN(244, "ISH_TYPEC_I2C2_SCL"),
+ PINCTRL_PIN(245, "COMPUTE_PMU_PROCHOT_B"),
+ PINCTRL_PIN(246, "PMU_CATERR_B"),
+ PINCTRL_PIN(247, "COMPUTE_PMIC_VR_READY"),
+ PINCTRL_PIN(248, "FORCE_FW_RELOAD"),
+ PINCTRL_PIN(249, "ROP_PMIC_IRQ_ISH_GPIO31_TPC_ALERT_B"),
+ PINCTRL_PIN(250, "ROP_PMIC_RESET_B"),
+ PINCTRL_PIN(251, "ROP_PMIC_STNBY_SLP_S0_B"),
+ PINCTRL_PIN(252, "ROP_PMIC_THERMTRIP_B"),
+ PINCTRL_PIN(253, "MODEM_CLKREQ"),
+ PINCTRL_PIN(254, "TPC0_BSSB_SBU1"),
+ PINCTRL_PIN(255, "TPC0_BSSB_SBU2"),
+ PINCTRL_PIN(256, "OSC_CLK_OUT_CAM_4"),
+ PINCTRL_PIN(257, "HPD1"),
+ PINCTRL_PIN(258, "HPD0"),
+ PINCTRL_PIN(259, "PMC_TIME_SYNC_0"),
+ PINCTRL_PIN(260, "PMC_TIME_SYNC_1"),
+ PINCTRL_PIN(261, "OSC_CLK_OUT_CAM_5"),
+ PINCTRL_PIN(262, "ISH_GP_20"),
+ PINCTRL_PIN(263, "ISH_GP_16"),
+ PINCTRL_PIN(264, "ISH_GP_17"),
+ PINCTRL_PIN(265, "ISH_GP_18"),
+ PINCTRL_PIN(266, "ISH_GP_19"),
+};
+
+static const struct intel_padgroup lkf_community0_gpps[] = {
+ LKF_GPP(0, 0, 31, 0), /* EAST_0 */
+ LKF_GPP(1, 32, 59, 32), /* EAST_1 */
+};
+
+static const struct intel_padgroup lkf_community1_gpps[] = {
+ LKF_GPP(0, 60, 91, 64), /* NORTHWEST_0 */
+ LKF_GPP(1, 92, 123, 96), /* NORTHWEST_1 */
+ LKF_GPP(2, 124, 148, 128), /* NORTHWEST_2 */
+};
+
+static const struct intel_padgroup lkf_community2_gpps[] = {
+ LKF_GPP(0, 149, 180, 160), /* WEST_0 */
+ LKF_GPP(1, 181, 212, 192), /* WEST_1 */
+ LKF_GPP(2, 213, 237, 224), /* WEST_2 */
+};
+
+static const struct intel_padgroup lkf_community3_gpps[] = {
+ LKF_GPP(0, 238, 266, 256), /* SOUTHEAST */
+};
+
+static const struct intel_community lkf_communities[] = {
+ LKF_COMMUNITY(0, 0, 59, lkf_community0_gpps), /* EAST */
+ LKF_COMMUNITY(1, 60, 148, lkf_community1_gpps), /* NORTHWEST */
+ LKF_COMMUNITY(2, 149, 237, lkf_community2_gpps), /* WEST */
+ LKF_COMMUNITY(3, 238, 266, lkf_community3_gpps), /* SOUTHEAST */
+};
+
+static const struct intel_pinctrl_soc_data lkf_soc_data = {
+ .pins = lkf_pins,
+ .npins = ARRAY_SIZE(lkf_pins),
+ .communities = lkf_communities,
+ .ncommunities = ARRAY_SIZE(lkf_communities),
+};
+
+static const struct acpi_device_id lkf_pinctrl_acpi_match[] = {
+ { "INT34C4", (kernel_ulong_t)&lkf_soc_data },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, lkf_pinctrl_acpi_match);
+
+static INTEL_PINCTRL_PM_OPS(lkf_pinctrl_pm_ops);
+
+static struct platform_driver lkf_pinctrl_driver = {
+ .probe = intel_pinctrl_probe_by_hid,
+ .driver = {
+ .name = "lakefield-pinctrl",
+ .acpi_match_table = lkf_pinctrl_acpi_match,
+ .pm = &lkf_pinctrl_pm_ops,
+ },
+};
+module_platform_driver(lkf_pinctrl_driver);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_DESCRIPTION("Intel Lakefield PCH pinctrl/GPIO driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index 96589d01fe35..0a48ca46ab59 100644
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -496,7 +496,7 @@ static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned long flags;
u32 value, pull;
- u16 arg = 0;
+ u16 arg;
raw_spin_lock_irqsave(&lg->lock, flags);
value = ioread32(conf2);
@@ -506,8 +506,9 @@ static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
- if (pull)
+ if (pull != GPIWP_NONE)
return -EINVAL;
+ arg = 0;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (pull != GPIWP_DOWN)
@@ -550,6 +551,7 @@ static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
value &= ~GPIWP_MASK;
+ value |= GPIWP_NONE;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
value &= ~GPIWP_MASK;
@@ -872,6 +874,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
gc->direction_output = lp_gpio_direction_output;
gc->get = lp_gpio_get;
gc->set = lp_gpio_set;
+ gc->set_config = gpiochip_generic_config;
gc->get_direction = lp_gpio_get_direction;
gc->base = -1;
gc->ngpio = LP_NUM_GPIO;
@@ -967,13 +970,12 @@ static int __init lp_gpio_init(void)
{
return platform_driver_register(&lp_gpio_driver);
}
+subsys_initcall(lp_gpio_init);
static void __exit lp_gpio_exit(void)
{
platform_driver_unregister(&lp_gpio_driver);
}
-
-subsys_initcall(lp_gpio_init);
module_exit(lp_gpio_exit);
MODULE_AUTHOR("Mathias Nyman (Intel)");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
index 38c5e166fd0f..68eee881ee3d 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
@@ -501,12 +501,6 @@ static int mt7622_pwm_ch6_2_pins[] = { 81, };
static int mt7622_pwm_ch6_2_funcs[] = { 4, };
static int mt7622_pwm_ch6_3_pins[] = { 100, };
static int mt7622_pwm_ch6_3_funcs[] = { 0, };
-static int mt7622_pwm_ch7_0_pins[] = { 70, };
-static int mt7622_pwm_ch7_0_funcs[] = { 3, };
-static int mt7622_pwm_ch7_1_pins[] = { 82, };
-static int mt7622_pwm_ch7_1_funcs[] = { 4, };
-static int mt7622_pwm_ch7_2_pins[] = { 101, };
-static int mt7622_pwm_ch7_2_funcs[] = { 0, };
/* SD */
static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
@@ -703,9 +697,6 @@ static const struct group_desc mt7622_groups[] = {
PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
- PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
- PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
- PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
@@ -802,9 +793,7 @@ static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
"pwm_ch4_3", "pwm_ch5_0",
"pwm_ch5_1", "pwm_ch5_2",
"pwm_ch6_0", "pwm_ch6_1",
- "pwm_ch6_2", "pwm_ch6_3",
- "pwm_ch7_0", "pwm_ch7_1",
- "pwm_ch7_2", };
+ "pwm_ch6_2", "pwm_ch6_3", };
static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", };
static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0",
"spic1_1", "spic2_0",
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index 7e950f5d62d0..7aeb552d16ce 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -488,14 +488,8 @@ EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get);
int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc)
{
- int err;
-
- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
- MTK_DISABLE);
- if (err)
- return err;
-
- return 0;
+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
+ MTK_DISABLE);
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1);
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 623af4410b07..039ce9be19c5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -247,13 +247,13 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
break;
case PIN_CONFIG_OUTPUT:
- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
- MTK_OUTPUT);
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
+ arg);
if (err)
goto err;
- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
- arg);
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
+ MTK_OUTPUT);
break;
case PIN_CONFIG_INPUT_SCHMITT:
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index 3cb119105ddb..b2855e341a75 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -1,8 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig PINCTRL_MESON
- bool "Amlogic SoC pinctrl drivers"
+ tristate "Amlogic SoC pinctrl drivers"
depends on ARCH_MESON
depends on OF
+ default y
select PINMUX
select PINCONF
select GENERIC_PINCONF
@@ -25,37 +26,37 @@ config PINCTRL_MESON8B
default y
config PINCTRL_MESON_GXBB
- bool "Meson gxbb SoC pinctrl driver"
+ tristate "Meson gxbb SoC pinctrl driver"
depends on ARM64
select PINCTRL_MESON8_PMX
default y
config PINCTRL_MESON_GXL
- bool "Meson gxl SoC pinctrl driver"
+ tristate "Meson gxl SoC pinctrl driver"
depends on ARM64
select PINCTRL_MESON8_PMX
default y
config PINCTRL_MESON8_PMX
- bool
+ tristate
config PINCTRL_MESON_AXG
- bool "Meson axg Soc pinctrl driver"
+ tristate "Meson axg Soc pinctrl driver"
depends on ARM64
select PINCTRL_MESON_AXG_PMX
default y
config PINCTRL_MESON_AXG_PMX
- bool
+ tristate
config PINCTRL_MESON_G12A
- bool "Meson g12a Soc pinctrl driver"
+ tristate "Meson g12a Soc pinctrl driver"
depends on ARM64
select PINCTRL_MESON_AXG_PMX
default y
config PINCTRL_MESON_A1
- bool "Meson a1 Soc pinctrl driver"
+ tristate "Meson a1 Soc pinctrl driver"
depends on ARM64
select PINCTRL_MESON_AXG_PMX
default y
diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c
index 8abf750eac7e..79f5d753d7e1 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-a1.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c
@@ -925,6 +925,7 @@ static const struct of_device_id meson_a1_pinctrl_dt_match[] = {
},
{ },
};
+MODULE_DEVICE_TABLE(of, meson_a1_pinctrl_dt_match);
static struct platform_driver meson_a1_pinctrl_driver = {
.probe = meson_pinctrl_probe,
@@ -934,4 +935,5 @@ static struct platform_driver meson_a1_pinctrl_driver = {
},
};
-builtin_platform_driver(meson_a1_pinctrl_driver);
+module_platform_driver(meson_a1_pinctrl_driver);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
index e8931d9cf863..80c43683c789 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
@@ -116,3 +116,6 @@ const struct pinmux_ops meson_axg_pmx_ops = {
.get_function_groups = meson_pmx_get_groups,
.gpio_request_enable = meson_axg_pmx_request_gpio,
};
+EXPORT_SYMBOL_GPL(meson_axg_pmx_ops);
+
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 072765db93d7..7bfecdfba177 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -1080,6 +1080,7 @@ static const struct of_device_id meson_axg_pinctrl_dt_match[] = {
},
{ },
};
+MODULE_DEVICE_TABLE(of, meson_axg_pinctrl_dt_match);
static struct platform_driver meson_axg_pinctrl_driver = {
.probe = meson_pinctrl_probe,
@@ -1089,4 +1090,5 @@ static struct platform_driver meson_axg_pinctrl_driver = {
},
};
-builtin_platform_driver(meson_axg_pinctrl_driver);
+module_platform_driver(meson_axg_pinctrl_driver);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
index 41850e3c0091..cd9656b13836 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
@@ -1410,6 +1410,7 @@ static const struct of_device_id meson_g12a_pinctrl_dt_match[] = {
},
{ },
};
+MODULE_DEVICE_TABLE(of, meson_g12a_pinctrl_dt_match);
static struct platform_driver meson_g12a_pinctrl_driver = {
.probe = meson_pinctrl_probe,
@@ -1419,4 +1420,5 @@ static struct platform_driver meson_g12a_pinctrl_driver = {
},
};
-builtin_platform_driver(meson_g12a_pinctrl_driver);
+module_platform_driver(meson_g12a_pinctrl_driver);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index d130c635f74b..f51fc3939252 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -900,6 +900,7 @@ static const struct of_device_id meson_gxbb_pinctrl_dt_match[] = {
},
{ },
};
+MODULE_DEVICE_TABLE(of, meson_gxbb_pinctrl_dt_match);
static struct platform_driver meson_gxbb_pinctrl_driver = {
.probe = meson_pinctrl_probe,
@@ -908,4 +909,5 @@ static struct platform_driver meson_gxbb_pinctrl_driver = {
.of_match_table = meson_gxbb_pinctrl_dt_match,
},
};
-builtin_platform_driver(meson_gxbb_pinctrl_driver);
+module_platform_driver(meson_gxbb_pinctrl_driver);
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index 32552d795bb2..51408996255b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -861,6 +861,7 @@ static const struct of_device_id meson_gxl_pinctrl_dt_match[] = {
},
{ },
};
+MODULE_DEVICE_TABLE(of, meson_gxl_pinctrl_dt_match);
static struct platform_driver meson_gxl_pinctrl_driver = {
.probe = meson_pinctrl_probe,
@@ -869,4 +870,5 @@ static struct platform_driver meson_gxl_pinctrl_driver = {
.of_match_table = meson_gxl_pinctrl_dt_match,
},
};
-builtin_platform_driver(meson_gxl_pinctrl_driver);
+module_platform_driver(meson_gxl_pinctrl_driver);
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index 20683cd072bb..49851444a6e3 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -152,6 +152,7 @@ int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
return pc->data->num_funcs;
}
+EXPORT_SYMBOL_GPL(meson_pmx_get_funcs_count);
const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
unsigned selector)
@@ -160,6 +161,7 @@ const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
return pc->data->funcs[selector].name;
}
+EXPORT_SYMBOL_GPL(meson_pmx_get_func_name);
int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
const char * const **groups,
@@ -172,6 +174,7 @@ int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
return 0;
}
+EXPORT_SYMBOL_GPL(meson_pmx_get_groups);
static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc,
unsigned int pin,
@@ -723,6 +726,7 @@ int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc)
return 0;
}
+EXPORT_SYMBOL_GPL(meson8_aobus_parse_dt_extra);
int meson_a1_parse_dt_extra(struct meson_pinctrl *pc)
{
@@ -732,6 +736,7 @@ int meson_a1_parse_dt_extra(struct meson_pinctrl *pc)
return 0;
}
+EXPORT_SYMBOL_GPL(meson_a1_parse_dt_extra);
int meson_pinctrl_probe(struct platform_device *pdev)
{
@@ -766,3 +771,6 @@ int meson_pinctrl_probe(struct platform_device *pdev)
return meson_gpiolib_register(pc);
}
+EXPORT_SYMBOL_GPL(meson_pinctrl_probe);
+
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index f8b0ff9d419a..ff5372e0a475 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -10,6 +10,7 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/types.h>
+#include <linux/module.h>
struct meson_pinctrl;
diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c
index 66a908f9f13d..f767b6923f9f 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c
@@ -100,3 +100,5 @@ const struct pinmux_ops meson8_pmx_ops = {
.get_function_groups = meson_pmx_get_groups,
.gpio_request_enable = meson8_pmx_request_gpio,
};
+EXPORT_SYMBOL_GPL(meson8_pmx_ops);
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
index acad3887cc74..0b9b6cbfd10c 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
@@ -421,6 +421,8 @@ static const unsigned lcd_d0_d7_a_1_pins[] = {
/* D8 thru D11 often used as TVOUT lines */
static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4,
DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 };
+static const unsigned lcd_d12_d15_a_1_pins[] = {
+ DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
static const unsigned lcd_d12_d23_a_1_pins[] = {
DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5,
DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6,
@@ -535,6 +537,9 @@ static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
+static const unsigned lcd_d16_d23_b_1_pins[] = {
+ DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
+ DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 };
static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 };
static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13,
@@ -689,6 +694,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
+ DB8500_PIN_GROUP(lcd_d12_d15_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(kpskaskb_a_1, NMK_GPIO_ALT_A),
@@ -741,6 +747,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B),
+ DB8500_PIN_GROUP(lcd_d16_d23_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
@@ -846,7 +853,8 @@ DB8500_FUNC_GROUPS(mc0, "mc0_a_1", "mc0_a_2", "mc0_dat47_a_1", "mc0dat31dir_a_1"
DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
- "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
+ "lcd_d8_d11_a_1", "lcd_d12_d15_a_1", "lcd_d12_d23_a_1", "lcd_b_1",
+ "lcd_d16_d23_b_1");
DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_a_2", "kp_b_1", "kp_b_2", "kp_c_1", "kp_oc1_1");
DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 899c16c17b6d..2d4acf21117c 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -197,10 +197,16 @@ static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
{
u32 pin_reg;
+ u32 db_cntrl;
unsigned long flags;
unsigned int bank, i, pin_num;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+ bool tmr_out_unit;
+ unsigned int time;
+ unsigned int unit;
+ bool tmr_large;
+
char *level_trig;
char *active_level;
char *interrupt_enable;
@@ -214,6 +220,8 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
char *pull_down_enable;
char *output_value;
char *output_enable;
+ char debounce_value[40];
+ char *debounce_enable;
for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
seq_printf(s, "GPIO bank%d\t", bank);
@@ -327,13 +335,44 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
pin_sts = "input is low|";
}
+ db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
+ if (db_cntrl) {
+ tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
+ tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
+ time = pin_reg & DB_TMR_OUT_MASK;
+ if (tmr_large) {
+ if (tmr_out_unit)
+ unit = 62500;
+ else
+ unit = 15625;
+ } else {
+ if (tmr_out_unit)
+ unit = 244;
+ else
+ unit = 61;
+ }
+ if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
+ debounce_enable = "debouncing filter (high and low) enabled|";
+ else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
+ debounce_enable = "debouncing filter (low) enabled|";
+ else
+ debounce_enable = "debouncing filter (high) enabled|";
+
+ snprintf(debounce_value, sizeof(debounce_value),
+ "debouncing timeout is %u (us)|", time * unit);
+ } else {
+ debounce_enable = "debouncing filter disabled|";
+ snprintf(debounce_value, sizeof(debounce_value), " ");
+ }
+
seq_printf(s, "%s %s %s %s %s %s\n"
- " %s %s %s %s %s %s %s 0x%x\n",
+ " %s %s %s %s %s %s %s %s %s 0x%x\n",
level_trig, active_level, interrupt_enable,
interrupt_mask, wake_cntrl0, wake_cntrl1,
wake_cntrl2, pin_sts, pull_up_sel,
pull_up_enable, pull_down_enable,
- output_value, output_enable, pin_reg);
+ output_value, output_enable,
+ debounce_enable, debounce_value, pin_reg);
}
}
}
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index 578b387100d9..36c6078b93b3 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -71,8 +71,15 @@
/* Custom pinconf parameters */
#define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
+/**
+ * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
+ * @nbanks: number of PIO banks
+ * @last_bank_count: number of lines in the last bank (can be less than
+ * the rest of the banks).
+ */
struct atmel_pioctrl_data {
unsigned nbanks;
+ unsigned last_bank_count;
};
struct atmel_group {
@@ -980,11 +987,13 @@ static const struct dev_pm_ops atmel_pctrl_pm_ops = {
* We can have up to 16 banks.
*/
static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
- .nbanks = 4,
+ .nbanks = 4,
+ .last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
};
static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
- .nbanks = 5,
+ .nbanks = 5,
+ .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */
};
static const struct of_device_id atmel_pctrl_of_match[] = {
@@ -1025,6 +1034,11 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
atmel_pioctrl_data = match->data;
atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
+ /* if last bank has limited number of pins, adjust accordingly */
+ if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
+ atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
+ atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
+ }
atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(atmel_pioctrl->reg_base))
@@ -1127,8 +1141,8 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
return -EINVAL;
}
atmel_pioctrl->irqs[i] = res->start;
- irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
- irq_set_handler_data(res->start, atmel_pioctrl);
+ irq_set_chained_handler_and_data(res->start,
+ atmel_gpio_irq_handler, atmel_pioctrl);
dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
}
diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
index 62c02b969327..7521a924dffb 100644
--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
@@ -431,24 +431,28 @@ static int pinctrl_falcon_probe(struct platform_device *pdev)
/* load and remap the pad resources of the different banks */
for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
- struct platform_device *ppdev = of_find_device_by_node(np);
const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
struct resource res;
+ struct platform_device *ppdev;
u32 avail;
int pins;
if (!of_device_is_available(np))
continue;
- if (!ppdev) {
- dev_err(&pdev->dev, "failed to find pad pdev\n");
- continue;
- }
if (!bank || *bank >= PORTS)
continue;
if (of_address_to_resource(np, 0, &res))
continue;
+
+ ppdev = of_find_device_by_node(np);
+ if (!ppdev) {
+ dev_err(&pdev->dev, "failed to find pad pdev\n");
+ continue;
+ }
+
falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
+ put_device(&ppdev->dev);
if (IS_ERR(falcon_info.clk[*bank])) {
dev_err(&ppdev->dev, "failed to get clock\n");
of_node_put(np);
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 621909b01deb..53a6a24bd052 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -134,61 +134,42 @@ static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
-static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, };
-static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, };
-static int jz4740_uart0_data_funcs[] = { 1, 1, };
-static int jz4740_uart0_hwflow_funcs[] = { 1, 1, };
-static int jz4740_uart1_data_funcs[] = { 2, 2, };
-static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4740_lcd_18bit_funcs[] = { 0, 0, };
-static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, };
-static int jz4740_nand_cs1_funcs[] = { 0, };
-static int jz4740_nand_cs2_funcs[] = { 0, };
-static int jz4740_nand_cs3_funcs[] = { 0, };
-static int jz4740_nand_cs4_funcs[] = { 0, };
-static int jz4740_nand_fre_fwe_funcs[] = { 0, 0, };
-static int jz4740_pwm_pwm0_funcs[] = { 0, };
-static int jz4740_pwm_pwm1_funcs[] = { 0, };
-static int jz4740_pwm_pwm2_funcs[] = { 0, };
-static int jz4740_pwm_pwm3_funcs[] = { 0, };
-static int jz4740_pwm_pwm4_funcs[] = { 0, };
-static int jz4740_pwm_pwm5_funcs[] = { 0, };
-static int jz4740_pwm_pwm6_funcs[] = { 0, };
-static int jz4740_pwm_pwm7_funcs[] = { 0, };
-
-#define INGENIC_PIN_GROUP(name, id) \
+
+#define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \
{ \
name, \
id##_pins, \
ARRAY_SIZE(id##_pins), \
- id##_funcs, \
+ funcs, \
}
+#define INGENIC_PIN_GROUP(name, id, func) \
+ INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
+
static const struct group_desc jz4740_groups[] = {
- INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit),
- INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit),
- INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data),
- INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow),
- INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data),
- INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit),
- INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit),
- INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit),
- INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft),
+ INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
+ INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
+ INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
+ INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
+ INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
+ INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
+ INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
+ INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
+ INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft, 0),
{ "lcd-no-pins", },
- INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1),
- INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
- INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
- INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
- INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe),
- INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0),
- INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1),
- INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2),
- INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3),
- INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4),
- INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5),
- INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6),
- INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
+ INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
+ INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
+ INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
+ INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
+ INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
+ INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0),
+ INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0),
+ INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0),
+ INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0),
+ INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0),
+ INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0),
+ INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0),
+ INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0),
};
static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
@@ -268,54 +249,33 @@ static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
static int jz4725b_lcd_generic_pins[] = { 0x75, };
-static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, };
-static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
-static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, };
-static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, };
-static int jz4725b_uart_data_funcs[] = { 1, 1, };
-static int jz4725b_nand_cs1_funcs[] = { 0, };
-static int jz4725b_nand_cs2_funcs[] = { 0, };
-static int jz4725b_nand_cs3_funcs[] = { 0, };
-static int jz4725b_nand_cs4_funcs[] = { 0, };
-static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, };
-static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, };
-static int jz4725b_pwm_pwm0_funcs[] = { 0, };
-static int jz4725b_pwm_pwm1_funcs[] = { 0, };
-static int jz4725b_pwm_pwm2_funcs[] = { 0, };
-static int jz4725b_pwm_pwm3_funcs[] = { 0, };
-static int jz4725b_pwm_pwm4_funcs[] = { 0, };
-static int jz4725b_pwm_pwm5_funcs[] = { 0, };
-static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4725b_lcd_18bit_funcs[] = { 0, 0, };
-static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, };
-static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, };
-static int jz4725b_lcd_generic_funcs[] = { 0, };
+static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
static const struct group_desc jz4725b_groups[] = {
- INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit),
- INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit),
- INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit),
- INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit),
- INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data),
- INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1),
- INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2),
- INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3),
- INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4),
- INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale),
- INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe),
- INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0),
- INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1),
- INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2),
- INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3),
- INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4),
- INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
- INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit),
- INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit),
- INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit),
- INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit),
- INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special),
- INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic),
+ INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
+ INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
+ jz4725b_mmc0_4bit_funcs),
+ INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
+ INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
+ INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
+ INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
+ INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
+ INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
+ INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
+ INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
+ INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
+ INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0),
+ INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0),
+ INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0),
+ INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0),
+ INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0),
+ INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0),
+ INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
+ INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
+ INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
+ INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
+ INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
+ INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
};
static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
@@ -431,110 +391,61 @@ static int jz4760_pwm_pwm5_pins[] = { 0x85, };
static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
-static int jz4760_uart0_data_funcs[] = { 0, 0, };
-static int jz4760_uart0_hwflow_funcs[] = { 0, 0, };
-static int jz4760_uart1_data_funcs[] = { 0, 0, };
-static int jz4760_uart1_hwflow_funcs[] = { 0, 0, };
-static int jz4760_uart2_data_funcs[] = { 0, 0, };
-static int jz4760_uart2_hwflow_funcs[] = { 0, 0, };
-static int jz4760_uart3_data_funcs[] = { 0, 1, };
-static int jz4760_uart3_hwflow_funcs[] = { 0, 0, };
-static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
-static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
-static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
-static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
-static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
-static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
-static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
-static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
-static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
-static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
-static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
-static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
-static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
-static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
-static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
-static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, };
-static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, };
-static int jz4760_nemc_rd_we_funcs[] = { 0, 0, };
-static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, };
-static int jz4760_nemc_wait_funcs[] = { 0, };
-static int jz4760_nemc_cs1_funcs[] = { 0, };
-static int jz4760_nemc_cs2_funcs[] = { 0, };
-static int jz4760_nemc_cs3_funcs[] = { 0, };
-static int jz4760_nemc_cs4_funcs[] = { 0, };
-static int jz4760_nemc_cs5_funcs[] = { 0, };
-static int jz4760_nemc_cs6_funcs[] = { 0, };
-static int jz4760_i2c0_funcs[] = { 0, 0, };
-static int jz4760_i2c1_funcs[] = { 0, 0, };
-static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4760_lcd_24bit_funcs[] = {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
-};
-static int jz4760_pwm_pwm0_funcs[] = { 0, };
-static int jz4760_pwm_pwm1_funcs[] = { 0, };
-static int jz4760_pwm_pwm2_funcs[] = { 0, };
-static int jz4760_pwm_pwm3_funcs[] = { 0, };
-static int jz4760_pwm_pwm4_funcs[] = { 0, };
-static int jz4760_pwm_pwm5_funcs[] = { 0, };
-static int jz4760_pwm_pwm6_funcs[] = { 0, };
-static int jz4760_pwm_pwm7_funcs[] = { 0, };
+static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
+static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
static const struct group_desc jz4760_groups[] = {
- INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data),
- INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow),
- INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data),
- INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow),
- INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data),
- INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow),
- INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data),
- INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow),
- INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a),
- INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a),
- INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e),
- INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e),
- INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e),
- INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d),
- INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d),
- INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e),
- INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e),
- INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e),
- INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b),
- INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b),
- INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e),
- INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e),
- INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e),
- INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data),
- INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data),
- INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale),
- INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr),
- INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we),
- INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe),
- INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait),
- INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1),
- INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2),
- INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3),
- INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4),
- INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5),
- INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6),
- INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0),
- INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1),
- INGENIC_PIN_GROUP("cim-data", jz4760_cim),
- INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit),
+ INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
+ INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
+ INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
+ INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
+ INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
+ INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
+ INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
+ jz4760_uart3_data_funcs),
+ INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
+ INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
+ jz4760_mmc0_1bit_a_funcs),
+ INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
+ INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
+ INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
+ INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
+ INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
+ INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
+ INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
+ INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
+ INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
+ INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
+ INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
+ INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
+ INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
+ INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
+ INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
+ INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
+ INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
+ INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
+ INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
+ INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
+ INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
+ INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
+ INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
+ INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
+ INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
+ INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
+ INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
+ INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
+ INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
+ INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
+ INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
{ "lcd-no-pins", },
- INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0),
- INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1),
- INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2),
- INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3),
- INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4),
- INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5),
- INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6),
- INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7),
+ INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
+ INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
+ INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
+ INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0),
+ INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0),
+ INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
+ INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
+ INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
};
static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -715,6 +626,10 @@ static int jz4770_cim_8bit_pins[] = {
static int jz4770_cim_12bit_pins[] = {
0x32, 0x33, 0xb0, 0xb1,
};
+static int jz4770_lcd_8bit_pins[] = {
+ 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
+ 0x48, 0x49, 0x52, 0x53,
+};
static int jz4770_lcd_24bit_pins[] = {
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
@@ -735,200 +650,104 @@ static int jz4770_mac_rmii_pins[] = {
static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
static int jz4770_otg_pins[] = { 0x8a, };
-static int jz4770_uart0_data_funcs[] = { 0, 0, };
-static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
-static int jz4770_uart1_data_funcs[] = { 0, 0, };
-static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
-static int jz4770_uart2_data_funcs[] = { 0, 0, };
-static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
-static int jz4770_uart3_data_funcs[] = { 0, 1, };
-static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
-static int jz4770_ssi0_dt_a_funcs[] = { 2, };
-static int jz4770_ssi0_dt_b_funcs[] = { 1, };
-static int jz4770_ssi0_dt_d_funcs[] = { 1, };
-static int jz4770_ssi0_dt_e_funcs[] = { 0, };
-static int jz4770_ssi0_dr_a_funcs[] = { 1, };
-static int jz4770_ssi0_dr_b_funcs[] = { 1, };
-static int jz4770_ssi0_dr_d_funcs[] = { 1, };
-static int jz4770_ssi0_dr_e_funcs[] = { 0, };
-static int jz4770_ssi0_clk_a_funcs[] = { 2, };
-static int jz4770_ssi0_clk_b_funcs[] = { 1, };
-static int jz4770_ssi0_clk_d_funcs[] = { 1, };
-static int jz4770_ssi0_clk_e_funcs[] = { 0, };
-static int jz4770_ssi0_gpc_b_funcs[] = { 1, };
-static int jz4770_ssi0_gpc_d_funcs[] = { 1, };
-static int jz4770_ssi0_gpc_e_funcs[] = { 0, };
-static int jz4770_ssi0_ce0_a_funcs[] = { 2, };
-static int jz4770_ssi0_ce0_b_funcs[] = { 1, };
-static int jz4770_ssi0_ce0_d_funcs[] = { 1, };
-static int jz4770_ssi0_ce0_e_funcs[] = { 0, };
-static int jz4770_ssi0_ce1_b_funcs[] = { 1, };
-static int jz4770_ssi0_ce1_d_funcs[] = { 1, };
-static int jz4770_ssi0_ce1_e_funcs[] = { 0, };
-static int jz4770_ssi1_dt_b_funcs[] = { 2, };
-static int jz4770_ssi1_dt_d_funcs[] = { 2, };
-static int jz4770_ssi1_dt_e_funcs[] = { 1, };
-static int jz4770_ssi1_dr_b_funcs[] = { 2, };
-static int jz4770_ssi1_dr_d_funcs[] = { 2, };
-static int jz4770_ssi1_dr_e_funcs[] = { 1, };
-static int jz4770_ssi1_clk_b_funcs[] = { 2, };
-static int jz4770_ssi1_clk_d_funcs[] = { 2, };
-static int jz4770_ssi1_clk_e_funcs[] = { 1, };
-static int jz4770_ssi1_gpc_b_funcs[] = { 2, };
-static int jz4770_ssi1_gpc_d_funcs[] = { 2, };
-static int jz4770_ssi1_gpc_e_funcs[] = { 1, };
-static int jz4770_ssi1_ce0_b_funcs[] = { 2, };
-static int jz4770_ssi1_ce0_d_funcs[] = { 2, };
-static int jz4770_ssi1_ce0_e_funcs[] = { 1, };
-static int jz4770_ssi1_ce1_b_funcs[] = { 2, };
-static int jz4770_ssi1_ce1_d_funcs[] = { 2, };
-static int jz4770_ssi1_ce1_e_funcs[] = { 1, };
-static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
-static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
-static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
-static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
-static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
-static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
-static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
-static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
-static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
-static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
-static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
-static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
-static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
-static int jz4770_nemc_wait_funcs[] = { 0, };
-static int jz4770_nemc_cs1_funcs[] = { 0, };
-static int jz4770_nemc_cs2_funcs[] = { 0, };
-static int jz4770_nemc_cs3_funcs[] = { 0, };
-static int jz4770_nemc_cs4_funcs[] = { 0, };
-static int jz4770_nemc_cs5_funcs[] = { 0, };
-static int jz4770_nemc_cs6_funcs[] = { 0, };
-static int jz4770_i2c0_funcs[] = { 0, 0, };
-static int jz4770_i2c1_funcs[] = { 0, 0, };
-static int jz4770_i2c2_funcs[] = { 2, 2, };
-static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
-static int jz4770_lcd_24bit_funcs[] = {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
-};
-static int jz4770_pwm_pwm0_funcs[] = { 0, };
-static int jz4770_pwm_pwm1_funcs[] = { 0, };
-static int jz4770_pwm_pwm2_funcs[] = { 0, };
-static int jz4770_pwm_pwm3_funcs[] = { 0, };
-static int jz4770_pwm_pwm4_funcs[] = { 0, };
-static int jz4770_pwm_pwm5_funcs[] = { 0, };
-static int jz4770_pwm_pwm6_funcs[] = { 0, };
-static int jz4770_pwm_pwm7_funcs[] = { 0, };
-static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4770_mac_mii_funcs[] = { 0, 0, };
-static int jz4770_otg_funcs[] = { 0, };
-
static const struct group_desc jz4770_groups[] = {
- INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
- INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
- INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
- INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
- INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data),
- INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
- INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
- INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
- INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a),
- INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b),
- INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d),
- INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
- INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a),
- INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b),
- INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d),
- INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
- INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a),
- INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b),
- INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d),
- INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e),
- INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b),
- INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d),
- INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e),
- INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a),
- INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b),
- INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d),
- INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
- INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b),
- INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d),
- INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e),
- INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b),
- INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d),
- INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e),
- INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b),
- INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d),
- INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e),
- INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b),
- INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d),
- INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e),
- INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b),
- INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d),
- INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e),
- INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b),
- INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d),
- INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
- INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b),
- INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d),
- INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e),
- INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
- INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
- INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
- INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
- INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
- INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
- INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
- INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
- INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
- INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
- INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
- INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
- INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
- INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
- INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
- INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
- INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
- INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
- INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
- INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
- INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
- INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
- INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
- INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
- INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
- INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
- INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
- INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
- INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
- INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
- INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
- INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
- INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
- INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
+ INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
+ INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
+ INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
+ INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
+ INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
+ INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
+ INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
+ jz4760_uart3_data_funcs),
+ INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
+ INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
+ INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
+ INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
+ INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
+ INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
+ INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
+ INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
+ INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
+ INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
+ INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
+ INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
+ INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
+ INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
+ INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
+ INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
+ INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
+ INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
+ INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
+ INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
+ INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
+ INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
+ INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
+ INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
+ INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
+ INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
+ INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
+ INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
+ INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
+ INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
+ INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
+ INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
+ INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
+ INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
+ INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
+ INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
+ INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
+ INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
+ INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
+ INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
+ INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
+ INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
+ jz4760_mmc0_1bit_a_funcs),
+ INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
+ INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
+ INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
+ INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
+ INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
+ INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
+ INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
+ INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
+ INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
+ INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
+ INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
+ INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
+ INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
+ INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
+ INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
+ INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
+ INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
+ INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
+ INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
+ INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
+ INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
+ INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
+ INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
+ INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
+ INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
+ INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
+ INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
+ INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
+ INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
+ INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
+ INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
+ INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
+ INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
+ INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
{ "lcd-no-pins", },
- INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
- INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
- INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
- INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
- INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
- INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
- INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
- INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
- INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
- INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
- INGENIC_PIN_GROUP("otg-vbus", jz4770_otg),
+ INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
+ INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
+ INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
+ INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
+ INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
+ INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
+ INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
+ INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
+ INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
+ INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
+ INGENIC_PIN_GROUP("otg-vbus", jz4770_otg, 0),
};
static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -977,7 +796,9 @@ static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
-static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
+static const char *jz4770_lcd_groups[] = {
+ "lcd-8bit", "lcd-24bit", "lcd-no-pins",
+};
static const char *jz4770_pwm0_groups[] = { "pwm0", };
static const char *jz4770_pwm1_groups[] = { "pwm1", };
static const char *jz4770_pwm2_groups[] = { "pwm2", };
@@ -1090,156 +911,115 @@ static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
static int jz4780_i2s_sysclk_pins[] = { 0x85, };
static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
-static int jz4780_uart2_data_funcs[] = { 1, 1, };
-static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
-static int jz4780_uart4_data_funcs[] = { 2, 2, };
-static int jz4780_ssi0_dt_a_19_funcs[] = { 2, };
-static int jz4780_ssi0_dt_a_21_funcs[] = { 2, };
-static int jz4780_ssi0_dt_a_28_funcs[] = { 2, };
-static int jz4780_ssi0_dt_b_funcs[] = { 1, };
-static int jz4780_ssi0_dt_d_funcs[] = { 1, };
-static int jz4780_ssi0_dr_a_20_funcs[] = { 2, };
-static int jz4780_ssi0_dr_a_27_funcs[] = { 2, };
-static int jz4780_ssi0_dr_b_funcs[] = { 1, };
-static int jz4780_ssi0_dr_d_funcs[] = { 1, };
-static int jz4780_ssi0_clk_a_funcs[] = { 2, };
-static int jz4780_ssi0_clk_b_5_funcs[] = { 1, };
-static int jz4780_ssi0_clk_b_28_funcs[] = { 1, };
-static int jz4780_ssi0_clk_d_funcs[] = { 1, };
-static int jz4780_ssi0_gpc_b_funcs[] = { 1, };
-static int jz4780_ssi0_gpc_d_funcs[] = { 1, };
-static int jz4780_ssi0_ce0_a_23_funcs[] = { 2, };
-static int jz4780_ssi0_ce0_a_25_funcs[] = { 2, };
-static int jz4780_ssi0_ce0_b_funcs[] = { 1, };
-static int jz4780_ssi0_ce0_d_funcs[] = { 1, };
-static int jz4780_ssi0_ce1_b_funcs[] = { 1, };
-static int jz4780_ssi0_ce1_d_funcs[] = { 1, };
-static int jz4780_ssi1_dt_b_funcs[] = { 2, };
-static int jz4780_ssi1_dt_d_funcs[] = { 2, };
-static int jz4780_ssi1_dr_b_funcs[] = { 2, };
-static int jz4780_ssi1_dr_d_funcs[] = { 2, };
-static int jz4780_ssi1_clk_b_funcs[] = { 2, };
-static int jz4780_ssi1_clk_d_funcs[] = { 2, };
-static int jz4780_ssi1_gpc_b_funcs[] = { 2, };
-static int jz4780_ssi1_gpc_d_funcs[] = { 2, };
-static int jz4780_ssi1_ce0_b_funcs[] = { 2, };
-static int jz4780_ssi1_ce0_d_funcs[] = { 2, };
-static int jz4780_ssi1_ce1_b_funcs[] = { 2, };
-static int jz4780_ssi1_ce1_d_funcs[] = { 2, };
-static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
-static int jz4780_i2c3_funcs[] = { 1, 1, };
-static int jz4780_i2c4_e_funcs[] = { 1, 1, };
-static int jz4780_i2c4_f_funcs[] = { 1, 1, };
-static int jz4780_i2s_data_tx_funcs[] = { 0, };
-static int jz4780_i2s_data_rx_funcs[] = { 0, };
-static int jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
-static int jz4780_i2s_clk_rx_funcs[] = { 1, 1, };
-static int jz4780_i2s_sysclk_funcs[] = { 2, };
-static int jz4780_hdmi_ddc_funcs[] = { 0, 0, };
+static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
static const struct group_desc jz4780_groups[] = {
- INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
- INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
- INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
- INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
- INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
- INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
- INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
- INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
- INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
- INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19),
- INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21),
- INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28),
- INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b),
- INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d),
- INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
- INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20),
- INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27),
- INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b),
- INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d),
- INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
- INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a),
- INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5),
- INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28),
- INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d),
- INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e),
- INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b),
- INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d),
- INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e),
- INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23),
- INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25),
- INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b),
- INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d),
- INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
- INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b),
- INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d),
- INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e),
- INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b),
- INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d),
- INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e),
- INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b),
- INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d),
- INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e),
- INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b),
- INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d),
- INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e),
- INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b),
- INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d),
- INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e),
- INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b),
- INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d),
- INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
- INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b),
- INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d),
- INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e),
- INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
- INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
- INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
- INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
- INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
- INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
- INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
- INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
- INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
- INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
- INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
- INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
- INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
- INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
- INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
- INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
- INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
- INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
- INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
- INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
- INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
- INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
- INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
- INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
- INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
- INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
- INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
- INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
- INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
- INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
- INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
- INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx),
- INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx),
- INGENIC_PIN_GROUP("i2s-clk-txrx", jz4780_i2s_clk_txrx),
- INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx),
- INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk),
- INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc),
- INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
- INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
+ INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
+ INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
+ INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
+ INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
+ INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
+ INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
+ INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
+ jz4760_uart3_data_funcs),
+ INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
+ INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
+ INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
+ INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
+ INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
+ INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
+ INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
+ INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
+ INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
+ INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
+ INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
+ INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
+ INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
+ INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
+ INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
+ INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
+ INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
+ INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
+ INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
+ INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
+ INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
+ INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
+ INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
+ INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
+ INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
+ INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
+ INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
+ INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
+ INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
+ INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
+ INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
+ INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
+ INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
+ INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
+ INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
+ INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
+ INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
+ INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
+ INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
+ INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
+ INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
+ INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
+ INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
+ INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
+ INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
+ INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
+ INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
+ INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
+ jz4760_mmc0_1bit_a_funcs),
+ INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
+ INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
+ INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
+ INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
+ INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
+ INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
+ INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
+ INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
+ INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
+ INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
+ INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
+ INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
+ INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
+ INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
+ INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
+ INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
+ INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
+ INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
+ INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
+ INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
+ INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
+ INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
+ INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
+ INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
+ INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
+ INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
+ INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
+ INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
+ INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
+ INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
+ INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
+ INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
+ INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
+ jz4780_i2s_clk_txrx_funcs),
+ INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
+ INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
+ INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
+ INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
+ INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
+ INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
{ "lcd-no-pins", },
- INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
- INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
- INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
- INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
- INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
- INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
- INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
- INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
+ INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
+ INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
+ INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
+ INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
+ INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
+ INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
+ INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
+ INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
};
static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
@@ -1411,119 +1191,61 @@ static int x1000_mac_pins[] = {
0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
};
-static int x1000_uart0_data_funcs[] = { 0, 0, };
-static int x1000_uart0_hwflow_funcs[] = { 0, 0, };
-static int x1000_uart1_data_a_funcs[] = { 2, 2, };
-static int x1000_uart1_data_d_funcs[] = { 1, 1, };
-static int x1000_uart1_hwflow_funcs[] = { 1, 1, };
-static int x1000_uart2_data_a_funcs[] = { 2, 2, };
-static int x1000_uart2_data_d_funcs[] = { 0, 0, };
-static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
-static int x1000_ssi_dt_a_22_funcs[] = { 2, };
-static int x1000_ssi_dt_a_29_funcs[] = { 2, };
-static int x1000_ssi_dt_d_funcs[] = { 0, };
-static int x1000_ssi_dr_a_23_funcs[] = { 2, };
-static int x1000_ssi_dr_a_28_funcs[] = { 2, };
-static int x1000_ssi_dr_d_funcs[] = { 0, };
-static int x1000_ssi_clk_a_24_funcs[] = { 2, };
-static int x1000_ssi_clk_a_26_funcs[] = { 2, };
-static int x1000_ssi_clk_d_funcs[] = { 0, };
-static int x1000_ssi_gpc_a_20_funcs[] = { 2, };
-static int x1000_ssi_gpc_a_31_funcs[] = { 2, };
-static int x1000_ssi_ce0_a_25_funcs[] = { 2, };
-static int x1000_ssi_ce0_a_27_funcs[] = { 2, };
-static int x1000_ssi_ce0_d_funcs[] = { 0, };
-static int x1000_ssi_ce1_a_21_funcs[] = { 2, };
-static int x1000_ssi_ce1_a_30_funcs[] = { 2, };
-static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };
-static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };
-static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };
-static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };
-static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };
-static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-static int x1000_emc_addr_funcs[] = {
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-};
-static int x1000_emc_rd_we_funcs[] = { 0, 0, };
-static int x1000_emc_wait_funcs[] = { 0, };
-static int x1000_emc_cs1_funcs[] = { 0, };
-static int x1000_emc_cs2_funcs[] = { 0, };
-static int x1000_i2c0_funcs[] = { 0, 0, };
-static int x1000_i2c1_a_funcs[] = { 2, 2, };
-static int x1000_i2c1_c_funcs[] = { 0, 0, };
-static int x1000_i2c2_funcs[] = { 1, 1, };
-static int x1000_i2s_data_tx_funcs[] = { 1, };
-static int x1000_i2s_data_rx_funcs[] = { 1, };
-static int x1000_i2s_clk_txrx_funcs[] = { 1, 1, };
-static int x1000_i2s_sysclk_funcs[] = { 1, };
-static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-static int x1000_lcd_8bit_funcs[] = {
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-};
-static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
-static int x1000_pwm_pwm0_funcs[] = { 0, };
-static int x1000_pwm_pwm1_funcs[] = { 1, };
-static int x1000_pwm_pwm2_funcs[] = { 1, };
-static int x1000_pwm_pwm3_funcs[] = { 2, };
-static int x1000_pwm_pwm4_funcs[] = { 0, };
-static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
static const struct group_desc x1000_groups[] = {
- INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data),
- INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
- INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
- INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
- INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow),
- INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
- INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
- INGENIC_PIN_GROUP("sfc", x1000_sfc),
- INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22),
- INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29),
- INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d),
- INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23),
- INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28),
- INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d),
- INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24),
- INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26),
- INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d),
- INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20),
- INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31),
- INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25),
- INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27),
- INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d),
- INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21),
- INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30),
- INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
- INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
- INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
- INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
- INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
- INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data),
- INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data),
- INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr),
- INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we),
- INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait),
- INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1),
- INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2),
- INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
- INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
- INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
- INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
- INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx),
- INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx),
- INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx),
- INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk),
- INGENIC_PIN_GROUP("cim-data", x1000_cim),
- INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
- INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
+ INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
+ INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
+ INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
+ INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
+ INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
+ INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
+ INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
+ INGENIC_PIN_GROUP("sfc", x1000_sfc, 1),
+ INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
+ INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
+ INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
+ INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
+ INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
+ INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
+ INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
+ INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
+ INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
+ INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
+ INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
+ INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
+ INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
+ INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
+ INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
+ INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
+ INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
+ INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
+ INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
+ INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
+ INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
+ INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
+ INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
+ INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
+ INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
+ INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
+ INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
+ INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
+ INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
+ INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
+ INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
+ INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
+ INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
+ INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
+ INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
+ INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
+ INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
+ INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
+ INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
{ "lcd-no-pins", },
- INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0),
- INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1),
- INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2),
- INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3),
- INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4),
- INGENIC_PIN_GROUP("mac", x1000_mac),
+ INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0),
+ INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1),
+ INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1),
+ INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),
+ INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0),
+ INGENIC_PIN_GROUP("mac", x1000_mac, 1),
};
static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -1633,56 +1355,32 @@ static int x1500_pwm_pwm2_pins[] = { 0x5b, };
static int x1500_pwm_pwm3_pins[] = { 0x26, };
static int x1500_pwm_pwm4_pins[] = { 0x58, };
-static int x1500_uart0_data_funcs[] = { 0, 0, };
-static int x1500_uart0_hwflow_funcs[] = { 0, 0, };
-static int x1500_uart1_data_a_funcs[] = { 2, 2, };
-static int x1500_uart1_data_d_funcs[] = { 1, 1, };
-static int x1500_uart1_hwflow_funcs[] = { 1, 1, };
-static int x1500_uart2_data_a_funcs[] = { 2, 2, };
-static int x1500_uart2_data_d_funcs[] = { 0, 0, };
-static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, };
-static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, };
-static int x1500_i2c0_funcs[] = { 0, 0, };
-static int x1500_i2c1_a_funcs[] = { 2, 2, };
-static int x1500_i2c1_c_funcs[] = { 0, 0, };
-static int x1500_i2c2_funcs[] = { 1, 1, };
-static int x1500_i2s_data_tx_funcs[] = { 1, };
-static int x1500_i2s_data_rx_funcs[] = { 1, };
-static int x1500_i2s_clk_txrx_funcs[] = { 1, 1, };
-static int x1500_i2s_sysclk_funcs[] = { 1, };
-static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-static int x1500_pwm_pwm0_funcs[] = { 0, };
-static int x1500_pwm_pwm1_funcs[] = { 1, };
-static int x1500_pwm_pwm2_funcs[] = { 1, };
-static int x1500_pwm_pwm3_funcs[] = { 2, };
-static int x1500_pwm_pwm4_funcs[] = { 0, };
-
static const struct group_desc x1500_groups[] = {
- INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data),
- INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),
- INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),
- INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),
- INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow),
- INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),
- INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),
- INGENIC_PIN_GROUP("sfc", x1000_sfc),
- INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit),
- INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit),
- INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),
- INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
- INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
- INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2),
- INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx),
- INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx),
- INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx),
- INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk),
- INGENIC_PIN_GROUP("cim-data", x1500_cim),
+ INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
+ INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
+ INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
+ INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
+ INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
+ INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
+ INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
+ INGENIC_PIN_GROUP("sfc", x1000_sfc, 1),
+ INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
+ INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
+ INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
+ INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
+ INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
+ INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
+ INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
+ INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
+ INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
+ INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
+ INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
{ "lcd-no-pins", },
- INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0),
- INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1),
- INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2),
- INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3),
- INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4),
+ INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),
+ INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),
+ INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1),
+ INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),
+ INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0),
};
static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -1811,124 +1509,62 @@ static int x1830_mac_pins[] = {
0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
};
-static int x1830_uart0_data_funcs[] = { 0, 0, };
-static int x1830_uart0_hwflow_funcs[] = { 0, 0, };
-static int x1830_uart1_data_funcs[] = { 0, 0, };
-static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
-static int x1830_ssi0_dt_funcs[] = { 0, };
-static int x1830_ssi0_dr_funcs[] = { 0, };
-static int x1830_ssi0_clk_funcs[] = { 0, };
-static int x1830_ssi0_gpc_funcs[] = { 0, };
-static int x1830_ssi0_ce0_funcs[] = { 0, };
-static int x1830_ssi0_ce1_funcs[] = { 0, };
-static int x1830_ssi1_dt_c_funcs[] = { 1, };
-static int x1830_ssi1_dr_c_funcs[] = { 1, };
-static int x1830_ssi1_clk_c_funcs[] = { 1, };
-static int x1830_ssi1_gpc_c_funcs[] = { 1, };
-static int x1830_ssi1_ce0_c_funcs[] = { 1, };
-static int x1830_ssi1_ce1_c_funcs[] = { 1, };
-static int x1830_ssi1_dt_d_funcs[] = { 2, };
-static int x1830_ssi1_dr_d_funcs[] = { 2, };
-static int x1830_ssi1_clk_d_funcs[] = { 2, };
-static int x1830_ssi1_gpc_d_funcs[] = { 2, };
-static int x1830_ssi1_ce0_d_funcs[] = { 2, };
-static int x1830_ssi1_ce1_d_funcs[] = { 2, };
-static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, };
-static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, };
-static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, };
-static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, };
-static int x1830_i2c0_funcs[] = { 1, 1, };
-static int x1830_i2c1_funcs[] = { 0, 0, };
-static int x1830_i2c2_funcs[] = { 1, 1, };
-static int x1830_i2s_data_tx_funcs[] = { 0, };
-static int x1830_i2s_data_rx_funcs[] = { 0, };
-static int x1830_i2s_clk_txrx_funcs[] = { 0, 0, };
-static int x1830_i2s_clk_rx_funcs[] = { 0, 0, };
-static int x1830_i2s_sysclk_funcs[] = { 0, };
-static int x1830_lcd_rgb_18bit_funcs[] = {
- 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
-};
-static int x1830_lcd_slcd_8bit_funcs[] = {
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-};
-static int x1830_lcd_slcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
-static int x1830_pwm_pwm0_b_funcs[] = { 0, };
-static int x1830_pwm_pwm0_c_funcs[] = { 1, };
-static int x1830_pwm_pwm1_b_funcs[] = { 0, };
-static int x1830_pwm_pwm1_c_funcs[] = { 1, };
-static int x1830_pwm_pwm2_c_8_funcs[] = { 0, };
-static int x1830_pwm_pwm2_c_13_funcs[] = { 1, };
-static int x1830_pwm_pwm3_c_9_funcs[] = { 0, };
-static int x1830_pwm_pwm3_c_14_funcs[] = { 1, };
-static int x1830_pwm_pwm4_c_15_funcs[] = { 1, };
-static int x1830_pwm_pwm4_c_25_funcs[] = { 0, };
-static int x1830_pwm_pwm5_c_16_funcs[] = { 1, };
-static int x1830_pwm_pwm5_c_26_funcs[] = { 0, };
-static int x1830_pwm_pwm6_c_17_funcs[] = { 1, };
-static int x1830_pwm_pwm6_c_27_funcs[] = { 0, };
-static int x1830_pwm_pwm7_c_18_funcs[] = { 1, };
-static int x1830_pwm_pwm7_c_28_funcs[] = { 0, };
-static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-
static const struct group_desc x1830_groups[] = {
- INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data),
- INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow),
- INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data),
- INGENIC_PIN_GROUP("sfc", x1830_sfc),
- INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt),
- INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr),
- INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk),
- INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc),
- INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0),
- INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1),
- INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c),
- INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c),
- INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c),
- INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c),
- INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c),
- INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c),
- INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d),
- INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d),
- INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d),
- INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d),
- INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d),
- INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d),
- INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit),
- INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit),
- INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit),
- INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit),
- INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0),
- INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1),
- INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2),
- INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx),
- INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx),
- INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx),
- INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx),
- INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk),
- INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit),
- INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit),
- INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit),
+ INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
+ INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
+ INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
+ INGENIC_PIN_GROUP("sfc", x1830_sfc, 1),
+ INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
+ INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
+ INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
+ INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
+ INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
+ INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
+ INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
+ INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
+ INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
+ INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
+ INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
+ INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
+ INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
+ INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
+ INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
+ INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
+ INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
+ INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
+ INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
+ INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
+ INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
+ INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
+ INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
+ INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
+ INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
+ INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
+ INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
+ INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
+ INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
+ INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
+ INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit, 0),
+ INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
+ INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
{ "lcd-no-pins", },
- INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b),
- INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c),
- INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b),
- INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c),
- INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8),
- INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13),
- INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9),
- INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14),
- INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15),
- INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25),
- INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16),
- INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26),
- INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17),
- INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27),
- INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18),
- INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28),
- INGENIC_PIN_GROUP("mac", x1830_mac),
+ INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
+ INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
+ INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
+ INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
+ INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
+ INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
+ INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
+ INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
+ INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
+ INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
+ INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
+ INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
+ INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
+ INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
+ INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
+ INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
+ INGENIC_PIN_GROUP("mac", x1830_mac, 0),
};
static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -2381,6 +2017,8 @@ static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
struct function_desc *func;
struct group_desc *grp;
unsigned int i;
+ uintptr_t mode;
+ u8 *pin_modes;
func = pinmux_generic_get_function(pctldev, selector);
if (!func)
@@ -2393,10 +2031,15 @@ static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
dev_dbg(pctldev->dev, "enable function %s group %s\n",
func->name, grp->name);
- for (i = 0; i < grp->num_pins; i++) {
- int *pin_modes = grp->data;
+ mode = (uintptr_t)grp->data;
+ if (mode <= 3) {
+ for (i = 0; i < grp->num_pins; i++)
+ ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode);
+ } else {
+ pin_modes = grp->data;
- ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
+ for (i = 0; i < grp->num_pins; i++)
+ ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
}
return 0;
diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c
new file mode 100644
index 000000000000..f35edb0eac40
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c
@@ -0,0 +1,892 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Microsemi/Microchip SoCs serial gpio driver
+ *
+ * Author: Lars Povlsen <lars.povlsen@microchip.com>
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+
+#include "core.h"
+#include "pinconf.h"
+
+#define SGPIO_BITS_PER_WORD 32
+#define SGPIO_MAX_BITS 4
+#define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */
+
+enum {
+ REG_INPUT_DATA,
+ REG_PORT_CONFIG,
+ REG_PORT_ENABLE,
+ REG_SIO_CONFIG,
+ REG_SIO_CLOCK,
+ REG_INT_POLARITY,
+ REG_INT_TRIGGER,
+ REG_INT_ACK,
+ REG_INT_ENABLE,
+ REG_INT_IDENT,
+ MAXREG
+};
+
+enum {
+ SGPIO_ARCH_LUTON,
+ SGPIO_ARCH_OCELOT,
+ SGPIO_ARCH_SPARX5,
+};
+
+enum {
+ SGPIO_FLAGS_HAS_IRQ = BIT(0),
+};
+
+struct sgpio_properties {
+ int arch;
+ int flags;
+ u8 regoff[MAXREG];
+};
+
+#define SGPIO_LUTON_AUTO_REPEAT BIT(5)
+#define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)
+#define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)
+#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
+
+#define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
+#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
+#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
+#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
+
+#define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
+#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
+#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
+#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
+
+#define SGPIO_MASTER_INTR_ENA BIT(0)
+
+#define SGPIO_INT_TRG_LEVEL 0
+#define SGPIO_INT_TRG_EDGE 1
+#define SGPIO_INT_TRG_EDGE_FALL 2
+#define SGPIO_INT_TRG_EDGE_RISE 3
+
+#define SGPIO_TRG_LEVEL_HIGH 0
+#define SGPIO_TRG_LEVEL_LOW 1
+
+static const struct sgpio_properties properties_luton = {
+ .arch = SGPIO_ARCH_LUTON,
+ .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
+};
+
+static const struct sgpio_properties properties_ocelot = {
+ .arch = SGPIO_ARCH_OCELOT,
+ .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
+};
+
+static const struct sgpio_properties properties_sparx5 = {
+ .arch = SGPIO_ARCH_SPARX5,
+ .flags = SGPIO_FLAGS_HAS_IRQ,
+ .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 },
+};
+
+static const char * const functions[] = { "gpio" };
+
+struct sgpio_bank {
+ struct sgpio_priv *priv;
+ bool is_input;
+ struct gpio_chip gpio;
+ struct pinctrl_desc pctl_desc;
+};
+
+struct sgpio_priv {
+ struct device *dev;
+ struct sgpio_bank in;
+ struct sgpio_bank out;
+ u32 bitcount;
+ u32 ports;
+ u32 clock;
+ u32 __iomem *regs;
+ const struct sgpio_properties *properties;
+};
+
+struct sgpio_port_addr {
+ u8 port;
+ u8 bit;
+};
+
+static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
+ struct sgpio_port_addr *addr)
+{
+ addr->port = pin / priv->bitcount;
+ addr->bit = pin % priv->bitcount;
+}
+
+static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
+{
+ return bit + port * priv->bitcount;
+}
+
+static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
+{
+ u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off];
+
+ return readl(reg);
+}
+
+static inline void sgpio_writel(struct sgpio_priv *priv,
+ u32 val, u32 rno, u32 off)
+{
+ u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off];
+
+ writel(val, reg);
+}
+
+static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
+ u32 rno, u32 off, u32 clear, u32 set)
+{
+ u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off];
+ u32 val = readl(reg);
+
+ val &= ~clear;
+ val |= set;
+
+ writel(val, reg);
+}
+
+static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
+{
+ int width = priv->bitcount - 1;
+ u32 clr, set;
+
+ switch (priv->properties->arch) {
+ case SGPIO_ARCH_LUTON:
+ clr = SGPIO_LUTON_PORT_WIDTH;
+ set = SGPIO_LUTON_AUTO_REPEAT |
+ FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width);
+ break;
+ case SGPIO_ARCH_OCELOT:
+ clr = SGPIO_OCELOT_PORT_WIDTH;
+ set = SGPIO_OCELOT_AUTO_REPEAT |
+ FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width);
+ break;
+ case SGPIO_ARCH_SPARX5:
+ clr = SGPIO_SPARX5_PORT_WIDTH;
+ set = SGPIO_SPARX5_AUTO_REPEAT |
+ FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width);
+ break;
+ default:
+ return;
+ }
+ sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set);
+}
+
+static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq)
+{
+ u32 clr, set;
+
+ switch (priv->properties->arch) {
+ case SGPIO_ARCH_LUTON:
+ clr = SGPIO_LUTON_CLK_FREQ;
+ set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq);
+ break;
+ case SGPIO_ARCH_OCELOT:
+ clr = SGPIO_OCELOT_CLK_FREQ;
+ set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq);
+ break;
+ case SGPIO_ARCH_SPARX5:
+ clr = SGPIO_SPARX5_CLK_FREQ;
+ set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq);
+ break;
+ default:
+ return;
+ }
+ sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
+}
+
+static void sgpio_output_set(struct sgpio_priv *priv,
+ struct sgpio_port_addr *addr,
+ int value)
+{
+ unsigned int bit = SGPIO_SRC_BITS * addr->bit;
+ u32 clr, set;
+
+ switch (priv->properties->arch) {
+ case SGPIO_ARCH_LUTON:
+ clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit));
+ set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit);
+ break;
+ case SGPIO_ARCH_OCELOT:
+ clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit));
+ set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit);
+ break;
+ case SGPIO_ARCH_SPARX5:
+ clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit));
+ set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
+ break;
+ default:
+ return;
+ }
+ sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set);
+}
+
+static int sgpio_output_get(struct sgpio_priv *priv,
+ struct sgpio_port_addr *addr)
+{
+ u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port);
+ unsigned int bit = SGPIO_SRC_BITS * addr->bit;
+
+ switch (priv->properties->arch) {
+ case SGPIO_ARCH_LUTON:
+ val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval);
+ break;
+ case SGPIO_ARCH_OCELOT:
+ val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval);
+ break;
+ case SGPIO_ARCH_SPARX5:
+ val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval);
+ break;
+ default:
+ val = 0;
+ break;
+ }
+ return !!(val & BIT(bit));
+}
+
+static int sgpio_input_get(struct sgpio_priv *priv,
+ struct sgpio_port_addr *addr)
+{
+ return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port));
+}
+
+static int sgpio_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
+ u32 param = pinconf_to_config_param(*config);
+ struct sgpio_priv *priv = bank->priv;
+ struct sgpio_port_addr addr;
+ int val;
+
+ sgpio_pin_to_addr(priv, pin, &addr);
+
+ switch (param) {
+ case PIN_CONFIG_INPUT_ENABLE:
+ val = bank->is_input;
+ break;
+
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ val = !bank->is_input;
+ break;
+
+ case PIN_CONFIG_OUTPUT:
+ if (bank->is_input)
+ return -EINVAL;
+ val = sgpio_output_get(priv, &addr);
+ break;
+
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, val);
+
+ return 0;
+}
+
+static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
+ struct sgpio_priv *priv = bank->priv;
+ struct sgpio_port_addr addr;
+ int cfg, err = 0;
+ u32 param, arg;
+
+ sgpio_pin_to_addr(priv, pin, &addr);
+
+ for (cfg = 0; cfg < num_configs; cfg++) {
+ param = pinconf_to_config_param(configs[cfg]);
+ arg = pinconf_to_config_argument(configs[cfg]);
+
+ switch (param) {
+ case PIN_CONFIG_OUTPUT:
+ if (bank->is_input)
+ return -EINVAL;
+ sgpio_output_set(priv, &addr, arg);
+ break;
+
+ default:
+ err = -ENOTSUPP;
+ }
+ }
+
+ return err;
+}
+
+static const struct pinconf_ops sgpio_confops = {
+ .is_generic = true,
+ .pin_config_get = sgpio_pinconf_get,
+ .pin_config_set = sgpio_pinconf_set,
+ .pin_config_config_dbg_show = pinconf_generic_dump_config,
+};
+
+static int sgpio_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ return 1;
+}
+
+static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev,
+ unsigned int function)
+{
+ return functions[0];
+}
+
+static int sgpio_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char *const **groups,
+ unsigned *const num_groups)
+{
+ *groups = functions;
+ *num_groups = ARRAY_SIZE(functions);
+
+ return 0;
+}
+
+static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int selector, unsigned int group)
+{
+ return 0;
+}
+
+static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin, bool input)
+{
+ struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
+
+ return (input == bank->is_input) ? 0 : -EINVAL;
+}
+
+static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
+ struct sgpio_priv *priv = bank->priv;
+ struct sgpio_port_addr addr;
+
+ sgpio_pin_to_addr(priv, offset, &addr);
+
+ if ((priv->ports & BIT(addr.port)) == 0) {
+ dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n",
+ addr.port, addr.bit);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct pinmux_ops sgpio_pmx_ops = {
+ .get_functions_count = sgpio_get_functions_count,
+ .get_function_name = sgpio_get_function_name,
+ .get_function_groups = sgpio_get_function_groups,
+ .set_mux = sgpio_pinmux_set_mux,
+ .gpio_set_direction = sgpio_gpio_set_direction,
+ .gpio_request_enable = sgpio_gpio_request_enable,
+};
+
+static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
+
+ return bank->pctl_desc.npins;
+}
+
+static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int group)
+{
+ struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
+
+ return bank->pctl_desc.pins[group].name;
+}
+
+static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int group,
+ const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = &bank->pctl_desc.pins[group].number;
+ *num_pins = 1;
+
+ return 0;
+}
+
+static const struct pinctrl_ops sgpio_pctl_ops = {
+ .get_groups_count = sgpio_pctl_get_groups_count,
+ .get_group_name = sgpio_pctl_get_group_name,
+ .get_group_pins = sgpio_pctl_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct sgpio_bank *bank = gpiochip_get_data(gc);
+
+ /* Fixed-position function */
+ return bank->is_input ? 0 : -EINVAL;
+}
+
+static int microchip_sgpio_direction_output(struct gpio_chip *gc,
+ unsigned int gpio, int value)
+{
+ struct sgpio_bank *bank = gpiochip_get_data(gc);
+ struct sgpio_priv *priv = bank->priv;
+ struct sgpio_port_addr addr;
+
+ /* Fixed-position function */
+ if (bank->is_input)
+ return -EINVAL;
+
+ sgpio_pin_to_addr(priv, gpio, &addr);
+
+ sgpio_output_set(priv, &addr, value);
+
+ return 0;
+}
+
+static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct sgpio_bank *bank = gpiochip_get_data(gc);
+
+ return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
+}
+
+static void microchip_sgpio_set_value(struct gpio_chip *gc,
+ unsigned int gpio, int value)
+{
+ microchip_sgpio_direction_output(gc, gpio, value);
+}
+
+static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct sgpio_bank *bank = gpiochip_get_data(gc);
+ struct sgpio_priv *priv = bank->priv;
+ struct sgpio_port_addr addr;
+
+ sgpio_pin_to_addr(priv, gpio, &addr);
+
+ return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr);
+}
+
+static int microchip_sgpio_of_xlate(struct gpio_chip *gc,
+ const struct of_phandle_args *gpiospec,
+ u32 *flags)
+{
+ struct sgpio_bank *bank = gpiochip_get_data(gc);
+ struct sgpio_priv *priv = bank->priv;
+ int pin;
+
+ /*
+ * Note that the SGIO pin is defined by *2* numbers, a port
+ * number between 0 and 31, and a bit index, 0 to 3.
+ */
+ if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
+ gpiospec->args[1] > priv->bitcount)
+ return -EINVAL;
+
+ pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]);
+
+ if (pin > gc->ngpio)
+ return -EINVAL;
+
+ if (flags)
+ *flags = gpiospec->args[2];
+
+ return pin;
+}
+
+static int microchip_sgpio_get_ports(struct sgpio_priv *priv)
+{
+ const char *range_property_name = "microchip,sgpio-port-ranges";
+ struct device *dev = priv->dev;
+ u32 range_params[64];
+ int i, nranges, ret;
+
+ /* Calculate port mask */
+ nranges = device_property_count_u32(dev, range_property_name);
+ if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) {
+ dev_err(dev, "%s port range: '%s' property\n",
+ nranges == -EINVAL ? "Missing" : "Invalid",
+ range_property_name);
+ return -EINVAL;
+ }
+
+ ret = device_property_read_u32_array(dev, range_property_name,
+ range_params, nranges);
+ if (ret) {
+ dev_err(dev, "failed to parse '%s' property: %d\n",
+ range_property_name, ret);
+ return ret;
+ }
+ for (i = 0; i < nranges; i += 2) {
+ int start, end;
+
+ start = range_params[i];
+ end = range_params[i + 1];
+ if (start > end || end >= SGPIO_BITS_PER_WORD) {
+ dev_err(dev, "Ill-formed port-range [%d:%d]\n",
+ start, end);
+ }
+ priv->ports |= GENMASK(end, start);
+ }
+
+ return 0;
+}
+
+static void microchip_sgpio_irq_settype(struct irq_data *data,
+ int type,
+ int polarity)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
+ struct sgpio_bank *bank = gpiochip_get_data(chip);
+ unsigned int gpio = irqd_to_hwirq(data);
+ struct sgpio_port_addr addr;
+ u32 ena;
+
+ sgpio_pin_to_addr(bank->priv, gpio, &addr);
+
+ /* Disable interrupt while changing type */
+ ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
+ sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
+
+ /* Type value spread over 2 registers sets: low, high bit */
+ sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
+ BIT(addr.port), (!!(type & 0x1)) << addr.port);
+ sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER + SGPIO_MAX_BITS, addr.bit,
+ BIT(addr.port), (!!(type & 0x2)) << addr.port);
+
+ if (type == SGPIO_INT_TRG_LEVEL)
+ sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,
+ BIT(addr.port), polarity << addr.port);
+
+ /* Possibly re-enable interrupts */
+ sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
+}
+
+static void microchip_sgpio_irq_setreg(struct irq_data *data,
+ int reg,
+ bool clear)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
+ struct sgpio_bank *bank = gpiochip_get_data(chip);
+ unsigned int gpio = irqd_to_hwirq(data);
+ struct sgpio_port_addr addr;
+
+ sgpio_pin_to_addr(bank->priv, gpio, &addr);
+
+ if (clear)
+ sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
+ else
+ sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
+}
+
+static void microchip_sgpio_irq_mask(struct irq_data *data)
+{
+ microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
+}
+
+static void microchip_sgpio_irq_unmask(struct irq_data *data)
+{
+ microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
+}
+
+static void microchip_sgpio_irq_ack(struct irq_data *data)
+{
+ microchip_sgpio_irq_setreg(data, REG_INT_ACK, false);
+}
+
+static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ type &= IRQ_TYPE_SENSE_MASK;
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_BOTH:
+ irq_set_handler_locked(data, handle_edge_irq);
+ microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ irq_set_handler_locked(data, handle_edge_irq);
+ microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ irq_set_handler_locked(data, handle_edge_irq);
+ microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0);
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ irq_set_handler_locked(data, handle_level_irq);
+ microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ irq_set_handler_locked(data, handle_level_irq);
+ microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct irq_chip microchip_sgpio_irqchip = {
+ .name = "gpio",
+ .irq_mask = microchip_sgpio_irq_mask,
+ .irq_ack = microchip_sgpio_irq_ack,
+ .irq_unmask = microchip_sgpio_irq_unmask,
+ .irq_set_type = microchip_sgpio_irq_set_type,
+};
+
+static void sgpio_irq_handler(struct irq_desc *desc)
+{
+ struct irq_chip *parent_chip = irq_desc_get_chip(desc);
+ struct gpio_chip *chip = irq_desc_get_handler_data(desc);
+ struct sgpio_bank *bank = gpiochip_get_data(chip);
+ struct sgpio_priv *priv = bank->priv;
+ int bit, port, gpio;
+ long val;
+
+ for (bit = 0; bit < priv->bitcount; bit++) {
+ val = sgpio_readl(priv, REG_INT_IDENT, bit);
+ if (!val)
+ continue;
+
+ chained_irq_enter(parent_chip, desc);
+
+ for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
+ gpio = sgpio_addr_to_pin(priv, port, bit);
+ generic_handle_irq(irq_linear_revmap(chip->irq.domain, gpio));
+ }
+
+ chained_irq_exit(parent_chip, desc);
+ }
+}
+
+static int microchip_sgpio_register_bank(struct device *dev,
+ struct sgpio_priv *priv,
+ struct fwnode_handle *fwnode,
+ int bankno)
+{
+ struct pinctrl_pin_desc *pins;
+ struct pinctrl_desc *pctl_desc;
+ struct pinctrl_dev *pctldev;
+ struct sgpio_bank *bank;
+ struct gpio_chip *gc;
+ u32 ngpios;
+ int i, ret;
+
+ /* Get overall bank struct */
+ bank = (bankno == 0) ? &priv->in : &priv->out;
+ bank->priv = priv;
+
+ if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) {
+ dev_info(dev, "failed to get number of gpios for bank%d\n",
+ bankno);
+ ngpios = 64;
+ }
+
+ priv->bitcount = ngpios / SGPIO_BITS_PER_WORD;
+ if (priv->bitcount > SGPIO_MAX_BITS) {
+ dev_err(dev, "Bit width exceeds maximum (%d)\n",
+ SGPIO_MAX_BITS);
+ return -EINVAL;
+ }
+
+ pctl_desc = &bank->pctl_desc;
+ pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput",
+ dev_name(dev),
+ bank->is_input ? "in" : "out");
+ pctl_desc->pctlops = &sgpio_pctl_ops;
+ pctl_desc->pmxops = &sgpio_pmx_ops;
+ pctl_desc->confops = &sgpio_confops;
+ pctl_desc->owner = THIS_MODULE;
+
+ pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ pctl_desc->npins = ngpios;
+ pctl_desc->pins = pins;
+
+ for (i = 0; i < ngpios; i++) {
+ struct sgpio_port_addr addr;
+
+ sgpio_pin_to_addr(priv, i, &addr);
+
+ pins[i].number = i;
+ pins[i].name = devm_kasprintf(dev, GFP_KERNEL,
+ "SGPIO_%c_p%db%d",
+ bank->is_input ? 'I' : 'O',
+ addr.port, addr.bit);
+ if (!pins[i].name)
+ return -ENOMEM;
+ }
+
+ pctldev = devm_pinctrl_register(dev, pctl_desc, bank);
+ if (IS_ERR(pctldev))
+ return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n");
+
+ gc = &bank->gpio;
+ gc->label = pctl_desc->name;
+ gc->parent = dev;
+ gc->of_node = to_of_node(fwnode);
+ gc->owner = THIS_MODULE;
+ gc->get_direction = microchip_sgpio_get_direction;
+ gc->direction_input = microchip_sgpio_direction_input;
+ gc->direction_output = microchip_sgpio_direction_output;
+ gc->get = microchip_sgpio_get_value;
+ gc->set = microchip_sgpio_set_value;
+ gc->request = gpiochip_generic_request;
+ gc->free = gpiochip_generic_free;
+ gc->of_xlate = microchip_sgpio_of_xlate;
+ gc->of_gpio_n_cells = 3;
+ gc->base = -1;
+ gc->ngpio = ngpios;
+
+ if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
+ int irq = fwnode_irq_get(fwnode, 0);
+
+ if (irq) {
+ struct gpio_irq_chip *girq = &gc->irq;
+
+ girq->chip = devm_kmemdup(dev, &microchip_sgpio_irqchip,
+ sizeof(microchip_sgpio_irqchip),
+ GFP_KERNEL);
+ if (!girq->chip)
+ return -ENOMEM;
+ girq->parent_handler = sgpio_irq_handler;
+ girq->num_parents = 1;
+ girq->parents = devm_kcalloc(dev, 1,
+ sizeof(*girq->parents),
+ GFP_KERNEL);
+ if (!girq->parents)
+ return -ENOMEM;
+ girq->parents[0] = irq;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+
+ /* Disable all individual pins */
+ for (i = 0; i < SGPIO_MAX_BITS; i++)
+ sgpio_writel(priv, 0, REG_INT_ENABLE, i);
+ /* Master enable */
+ sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA);
+ }
+ }
+
+ ret = devm_gpiochip_add_data(dev, gc, bank);
+ if (ret)
+ dev_err(dev, "Failed to register: ret %d\n", ret);
+
+ return ret;
+}
+
+static int microchip_sgpio_probe(struct platform_device *pdev)
+{
+ int div_clock = 0, ret, port, i, nbanks;
+ struct device *dev = &pdev->dev;
+ struct fwnode_handle *fwnode;
+ struct sgpio_priv *priv;
+ struct clk *clk;
+ u32 val;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+
+ clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
+
+ div_clock = clk_get_rate(clk);
+ if (device_property_read_u32(dev, "bus-frequency", &priv->clock))
+ priv->clock = 12500000;
+ if (priv->clock == 0 || priv->clock > (div_clock / 2)) {
+ dev_err(dev, "Invalid frequency %d\n", priv->clock);
+ return -EINVAL;
+ }
+
+ priv->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->regs))
+ return PTR_ERR(priv->regs);
+ priv->properties = device_get_match_data(dev);
+ priv->in.is_input = true;
+
+ /* Get rest of device properties */
+ ret = microchip_sgpio_get_ports(priv);
+ if (ret)
+ return ret;
+
+ nbanks = device_get_child_node_count(dev);
+ if (nbanks != 2) {
+ dev_err(dev, "Must have 2 banks (have %d)\n", nbanks);
+ return -EINVAL;
+ }
+
+ i = 0;
+ device_for_each_child_node(dev, fwnode) {
+ ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++);
+ if (ret)
+ return ret;
+ }
+
+ if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
+ dev_err(dev, "Banks must have same GPIO count\n");
+ return -ERANGE;
+ }
+
+ sgpio_configure_bitstream(priv);
+
+ val = max(2U, div_clock / priv->clock);
+ sgpio_configure_clock(priv, val);
+
+ for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
+ sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
+ sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
+
+ return 0;
+}
+
+static const struct of_device_id microchip_sgpio_gpio_of_match[] = {
+ {
+ .compatible = "microchip,sparx5-sgpio",
+ .data = &properties_sparx5,
+ }, {
+ .compatible = "mscc,luton-sgpio",
+ .data = &properties_luton,
+ }, {
+ .compatible = "mscc,ocelot-sgpio",
+ .data = &properties_ocelot,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver microchip_sgpio_pinctrl_driver = {
+ .driver = {
+ .name = "pinctrl-microchip-sgpio",
+ .of_match_table = microchip_sgpio_gpio_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = microchip_sgpio_probe,
+};
+builtin_platform_driver(microchip_sgpio_pinctrl_driver);
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
index a4a1b00f7f0d..2fd18e356d0c 100644
--- a/drivers/pinctrl/pinctrl-ocelot.c
+++ b/drivers/pinctrl/pinctrl-ocelot.c
@@ -158,6 +158,170 @@ struct ocelot_pinctrl {
u8 stride;
};
+#define LUTON_P(p, f0, f1) \
+static struct ocelot_pin_caps luton_pin_##p = { \
+ .pin = p, \
+ .functions = { \
+ FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \
+ }, \
+}
+
+LUTON_P(0, SG0, NONE);
+LUTON_P(1, SG0, NONE);
+LUTON_P(2, SG0, NONE);
+LUTON_P(3, SG0, NONE);
+LUTON_P(4, TACHO, NONE);
+LUTON_P(5, TWI, PHY_LED);
+LUTON_P(6, TWI, PHY_LED);
+LUTON_P(7, NONE, PHY_LED);
+LUTON_P(8, EXT_IRQ, PHY_LED);
+LUTON_P(9, EXT_IRQ, PHY_LED);
+LUTON_P(10, SFP, PHY_LED);
+LUTON_P(11, SFP, PHY_LED);
+LUTON_P(12, SFP, PHY_LED);
+LUTON_P(13, SFP, PHY_LED);
+LUTON_P(14, SI, PHY_LED);
+LUTON_P(15, SI, PHY_LED);
+LUTON_P(16, SI, PHY_LED);
+LUTON_P(17, SFP, PHY_LED);
+LUTON_P(18, SFP, PHY_LED);
+LUTON_P(19, SFP, PHY_LED);
+LUTON_P(20, SFP, PHY_LED);
+LUTON_P(21, SFP, PHY_LED);
+LUTON_P(22, SFP, PHY_LED);
+LUTON_P(23, SFP, PHY_LED);
+LUTON_P(24, SFP, PHY_LED);
+LUTON_P(25, SFP, PHY_LED);
+LUTON_P(26, SFP, PHY_LED);
+LUTON_P(27, SFP, PHY_LED);
+LUTON_P(28, SFP, PHY_LED);
+LUTON_P(29, PWM, NONE);
+LUTON_P(30, UART, NONE);
+LUTON_P(31, UART, NONE);
+
+#define LUTON_PIN(n) { \
+ .number = n, \
+ .name = "GPIO_"#n, \
+ .drv_data = &luton_pin_##n \
+}
+
+static const struct pinctrl_pin_desc luton_pins[] = {
+ LUTON_PIN(0),
+ LUTON_PIN(1),
+ LUTON_PIN(2),
+ LUTON_PIN(3),
+ LUTON_PIN(4),
+ LUTON_PIN(5),
+ LUTON_PIN(6),
+ LUTON_PIN(7),
+ LUTON_PIN(8),
+ LUTON_PIN(9),
+ LUTON_PIN(10),
+ LUTON_PIN(11),
+ LUTON_PIN(12),
+ LUTON_PIN(13),
+ LUTON_PIN(14),
+ LUTON_PIN(15),
+ LUTON_PIN(16),
+ LUTON_PIN(17),
+ LUTON_PIN(18),
+ LUTON_PIN(19),
+ LUTON_PIN(20),
+ LUTON_PIN(21),
+ LUTON_PIN(22),
+ LUTON_PIN(23),
+ LUTON_PIN(24),
+ LUTON_PIN(25),
+ LUTON_PIN(26),
+ LUTON_PIN(27),
+ LUTON_PIN(28),
+ LUTON_PIN(29),
+ LUTON_PIN(30),
+ LUTON_PIN(31),
+};
+
+#define SERVAL_P(p, f0, f1, f2) \
+static struct ocelot_pin_caps serval_pin_##p = { \
+ .pin = p, \
+ .functions = { \
+ FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
+ }, \
+}
+
+SERVAL_P(0, SG0, NONE, NONE);
+SERVAL_P(1, SG0, NONE, NONE);
+SERVAL_P(2, SG0, NONE, NONE);
+SERVAL_P(3, SG0, NONE, NONE);
+SERVAL_P(4, TACHO, NONE, NONE);
+SERVAL_P(5, PWM, NONE, NONE);
+SERVAL_P(6, TWI, NONE, NONE);
+SERVAL_P(7, TWI, NONE, NONE);
+SERVAL_P(8, SI, NONE, NONE);
+SERVAL_P(9, SI, MD, NONE);
+SERVAL_P(10, SI, MD, NONE);
+SERVAL_P(11, SFP, MD, TWI_SCL_M);
+SERVAL_P(12, SFP, MD, TWI_SCL_M);
+SERVAL_P(13, SFP, UART2, TWI_SCL_M);
+SERVAL_P(14, SFP, UART2, TWI_SCL_M);
+SERVAL_P(15, SFP, PTP0, TWI_SCL_M);
+SERVAL_P(16, SFP, PTP0, TWI_SCL_M);
+SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M);
+SERVAL_P(18, SFP, NONE, TWI_SCL_M);
+SERVAL_P(19, SFP, NONE, TWI_SCL_M);
+SERVAL_P(20, SFP, NONE, TWI_SCL_M);
+SERVAL_P(21, SFP, NONE, TWI_SCL_M);
+SERVAL_P(22, NONE, NONE, NONE);
+SERVAL_P(23, NONE, NONE, NONE);
+SERVAL_P(24, NONE, NONE, NONE);
+SERVAL_P(25, NONE, NONE, NONE);
+SERVAL_P(26, UART, NONE, NONE);
+SERVAL_P(27, UART, NONE, NONE);
+SERVAL_P(28, IRQ0, NONE, NONE);
+SERVAL_P(29, IRQ1, NONE, NONE);
+SERVAL_P(30, PTP0, NONE, NONE);
+SERVAL_P(31, PTP0, NONE, NONE);
+
+#define SERVAL_PIN(n) { \
+ .number = n, \
+ .name = "GPIO_"#n, \
+ .drv_data = &serval_pin_##n \
+}
+
+static const struct pinctrl_pin_desc serval_pins[] = {
+ SERVAL_PIN(0),
+ SERVAL_PIN(1),
+ SERVAL_PIN(2),
+ SERVAL_PIN(3),
+ SERVAL_PIN(4),
+ SERVAL_PIN(5),
+ SERVAL_PIN(6),
+ SERVAL_PIN(7),
+ SERVAL_PIN(8),
+ SERVAL_PIN(9),
+ SERVAL_PIN(10),
+ SERVAL_PIN(11),
+ SERVAL_PIN(12),
+ SERVAL_PIN(13),
+ SERVAL_PIN(14),
+ SERVAL_PIN(15),
+ SERVAL_PIN(16),
+ SERVAL_PIN(17),
+ SERVAL_PIN(18),
+ SERVAL_PIN(19),
+ SERVAL_PIN(20),
+ SERVAL_PIN(21),
+ SERVAL_PIN(22),
+ SERVAL_PIN(23),
+ SERVAL_PIN(24),
+ SERVAL_PIN(25),
+ SERVAL_PIN(26),
+ SERVAL_PIN(27),
+ SERVAL_PIN(28),
+ SERVAL_PIN(29),
+ SERVAL_PIN(30),
+ SERVAL_PIN(31),
+};
+
#define OCELOT_P(p, f0, f1, f2) \
static struct ocelot_pin_caps ocelot_pin_##p = { \
.pin = p, \
@@ -729,7 +893,7 @@ static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
if (err)
return err;
if (param == PIN_CONFIG_BIAS_DISABLE)
- val = (val == 0 ? true : false);
+ val = (val == 0);
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
val = (val & BIAS_PD_BIT ? true : false);
else /* PIN_CONFIG_BIAS_PULL_UP */
@@ -868,6 +1032,24 @@ static const struct pinctrl_ops ocelot_pctl_ops = {
.dt_free_map = pinconf_generic_dt_free_map,
};
+static struct pinctrl_desc luton_desc = {
+ .name = "luton-pinctrl",
+ .pins = luton_pins,
+ .npins = ARRAY_SIZE(luton_pins),
+ .pctlops = &ocelot_pctl_ops,
+ .pmxops = &ocelot_pmx_ops,
+ .owner = THIS_MODULE,
+};
+
+static struct pinctrl_desc serval_desc = {
+ .name = "serval-pinctrl",
+ .pins = serval_pins,
+ .npins = ARRAY_SIZE(serval_pins),
+ .pctlops = &ocelot_pctl_ops,
+ .pmxops = &ocelot_pmx_ops,
+ .owner = THIS_MODULE,
+};
+
static struct pinctrl_desc ocelot_desc = {
.name = "ocelot-pinctrl",
.pins = ocelot_pins,
@@ -1151,6 +1333,8 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
}
static const struct of_device_id ocelot_pinctrl_of_match[] = {
+ { .compatible = "mscc,luton-pinctrl", .data = &luton_desc },
+ { .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
{ .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..a003776506d0 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -2,7 +2,8 @@
if (ARCH_QCOM || COMPILE_TEST)
config PINCTRL_MSM
- bool
+ tristate "Qualcomm core pin controller driver"
+ depends on QCOM_SCM || !QCOM_SCM #if QCOM_SCM=m this can't be =y
select PINMUX
select PINCONF
select GENERIC_PINCONF
@@ -13,7 +14,7 @@ config PINCTRL_MSM
config PINCTRL_APQ8064
tristate "Qualcomm APQ8064 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
@@ -21,7 +22,7 @@ config PINCTRL_APQ8064
config PINCTRL_APQ8084
tristate "Qualcomm APQ8084 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
@@ -29,7 +30,7 @@ config PINCTRL_APQ8084
config PINCTRL_IPQ4019
tristate "Qualcomm IPQ4019 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
@@ -37,7 +38,7 @@ config PINCTRL_IPQ4019
config PINCTRL_IPQ8064
tristate "Qualcomm IPQ8064 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
@@ -45,7 +46,7 @@ config PINCTRL_IPQ8064
config PINCTRL_IPQ8074
tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
the Qualcomm Technologies Inc. TLMM block found on the
@@ -55,7 +56,7 @@ config PINCTRL_IPQ8074
config PINCTRL_IPQ6018
tristate "Qualcomm Technologies, Inc. IPQ6018 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
the Qualcomm Technologies Inc. TLMM block found on the
@@ -65,7 +66,7 @@ config PINCTRL_IPQ6018
config PINCTRL_MSM8226
tristate "Qualcomm 8226 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
@@ -74,7 +75,7 @@ config PINCTRL_MSM8226
config PINCTRL_MSM8660
tristate "Qualcomm 8660 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8660 platform.
@@ -82,7 +83,7 @@ config PINCTRL_MSM8660
config PINCTRL_MSM8960
tristate "Qualcomm 8960 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8960 platform.
@@ -90,7 +91,7 @@ config PINCTRL_MSM8960
config PINCTRL_MDM9615
tristate "Qualcomm 9615 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 9615 platform.
@@ -98,7 +99,7 @@ config PINCTRL_MDM9615
config PINCTRL_MSM8X74
tristate "Qualcomm 8x74 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8974 platform.
@@ -106,15 +107,25 @@ config PINCTRL_MSM8X74
config PINCTRL_MSM8916
tristate "Qualcomm 8916 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm 8916 platform.
+config PINCTRL_MSM8953
+ tristate "Qualcomm 8953 pin controller driver"
+ depends on GPIOLIB && OF
+ depends on PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm TLMM block found on the Qualcomm MSM8953 platform.
+ The Qualcomm APQ8053, SDM450, SDM632 platforms are also
+ supported by this driver.
+
config PINCTRL_MSM8976
tristate "Qualcomm 8976 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8976 platform.
@@ -124,7 +135,7 @@ config PINCTRL_MSM8976
config PINCTRL_MSM8994
tristate "Qualcomm 8994 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8994 platform. The
@@ -133,7 +144,7 @@ config PINCTRL_MSM8994
config PINCTRL_MSM8996
tristate "Qualcomm MSM8996 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm MSM8996 platform.
@@ -141,7 +152,7 @@ config PINCTRL_MSM8996
config PINCTRL_MSM8998
tristate "Qualcomm MSM8998 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm MSM8998 platform.
@@ -149,7 +160,7 @@ config PINCTRL_MSM8998
config PINCTRL_QCS404
tristate "Qualcomm QCS404 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
TLMM block found in the Qualcomm QCS404 platform.
@@ -157,7 +168,7 @@ config PINCTRL_QCS404
config PINCTRL_QDF2XXX
tristate "Qualcomm Technologies QDF2xxx pin controller driver"
depends on GPIOLIB && ACPI
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the GPIO driver for the TLMM block found on the
Qualcomm Technologies QDF2xxx SOCs.
@@ -194,16 +205,25 @@ config PINCTRL_QCOM_SSBI_PMIC
config PINCTRL_SC7180
tristate "Qualcomm Technologies Inc SC7180 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7180 platform.
+config PINCTRL_SC7280
+ tristate "Qualcomm Technologies Inc SC7280 pin controller driver"
+ depends on GPIOLIB && OF
+ depends on PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SC7280 platform.
+
config PINCTRL_SDM660
tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
@@ -212,16 +232,25 @@ config PINCTRL_SDM660
config PINCTRL_SDM845
tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
depends on GPIOLIB && (OF || ACPI)
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDM845 platform.
+config PINCTRL_SDX55
+ tristate "Qualcomm Technologies Inc SDX55 pin controller driver"
+ depends on GPIOLIB && OF
+ depends on PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SDX55 platform.
+
config PINCTRL_SM8150
tristate "Qualcomm Technologies Inc SM8150 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
@@ -230,10 +259,21 @@ config PINCTRL_SM8150
config PINCTRL_SM8250
tristate "Qualcomm Technologies Inc SM8250 pin controller driver"
depends on GPIOLIB && OF
- select PINCTRL_MSM
+ depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ depends on GPIOLIB
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..91875a3f5ac4 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
+obj-$(CONFIG_PINCTRL_MSM8953) += pinctrl-msm8953.o
obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o
obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o
obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o
@@ -24,7 +25,10 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
+obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
+obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index 000000000000..369ee20a7ea9
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,695 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_TLMM_REG_OFFSET 0x1000
+#define LPI_SLEW_RATE_MAX 0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
+#define LPI_GPIO_CFG_REG 0x00
+#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_OE_MASK BIT(9)
+#define LPI_GPIO_VALUE_REG 0x04
+#define LPI_GPIO_VALUE_IN_MASK BIT(0)
+#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
+
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER 0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
+#define NO_SLEW -1
+
+#define LPI_FUNCTION(fname) \
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .pin = id, \
+ .slew_offset = soff, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5, \
+ }
+
+struct lpi_pingroup {
+ const char *name;
+ const unsigned int *pins;
+ unsigned int npins;
+ unsigned int pin;
+ /* Bit offset in slew register for SoundWire pins only */
+ int slew_offset;
+ unsigned int *funcs;
+ unsigned int nfuncs;
+};
+
+struct lpi_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int ngroups;
+};
+
+struct lpi_pinctrl_variant_data {
+ const struct pinctrl_pin_desc *pins;
+ int npins;
+ const struct lpi_pingroup *groups;
+ int ngroups;
+ const struct lpi_function *functions;
+ int nfunctions;
+};
+
+#define MAX_LPI_NUM_CLKS 2
+
+struct lpi_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *ctrl;
+ struct gpio_chip chip;
+ struct pinctrl_desc desc;
+ char __iomem *tlmm_base;
+ char __iomem *slew_base;
+ struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
+ struct mutex slew_access_lock;
+ const struct lpi_pinctrl_variant_data *data;
+};
+
+/* sm8250 variant specific data */
+static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+};
+
+enum sm8250_lpi_functions {
+ LPI_MUX_dmic1_clk,
+ LPI_MUX_dmic1_data,
+ LPI_MUX_dmic2_clk,
+ LPI_MUX_dmic2_data,
+ LPI_MUX_dmic3_clk,
+ LPI_MUX_dmic3_data,
+ LPI_MUX_i2s1_clk,
+ LPI_MUX_i2s1_data,
+ LPI_MUX_i2s1_ws,
+ LPI_MUX_i2s2_clk,
+ LPI_MUX_i2s2_data,
+ LPI_MUX_i2s2_ws,
+ LPI_MUX_qua_mi2s_data,
+ LPI_MUX_qua_mi2s_sclk,
+ LPI_MUX_qua_mi2s_ws,
+ LPI_MUX_swr_rx_clk,
+ LPI_MUX_swr_rx_data,
+ LPI_MUX_swr_tx_clk,
+ LPI_MUX_swr_tx_data,
+ LPI_MUX_wsa_swr_clk,
+ LPI_MUX_wsa_swr_data,
+ LPI_MUX_gpio,
+ LPI_MUX__,
+};
+
+static const unsigned int gpio0_pins[] = { 0 };
+static const unsigned int gpio1_pins[] = { 1 };
+static const unsigned int gpio2_pins[] = { 2 };
+static const unsigned int gpio3_pins[] = { 3 };
+static const unsigned int gpio4_pins[] = { 4 };
+static const unsigned int gpio5_pins[] = { 5 };
+static const unsigned int gpio6_pins[] = { 6 };
+static const unsigned int gpio7_pins[] = { 7 };
+static const unsigned int gpio8_pins[] = { 8 };
+static const unsigned int gpio9_pins[] = { 9 };
+static const unsigned int gpio10_pins[] = { 10 };
+static const unsigned int gpio11_pins[] = { 11 };
+static const unsigned int gpio12_pins[] = { 12 };
+static const unsigned int gpio13_pins[] = { 13 };
+static const char * const swr_tx_clk_groups[] = { "gpio0" };
+static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
+static const char * const swr_rx_clk_groups[] = { "gpio3" };
+static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
+static const char * const dmic1_clk_groups[] = { "gpio6" };
+static const char * const dmic1_data_groups[] = { "gpio7" };
+static const char * const dmic2_clk_groups[] = { "gpio8" };
+static const char * const dmic2_data_groups[] = { "gpio9" };
+static const char * const i2s2_clk_groups[] = { "gpio10" };
+static const char * const i2s2_ws_groups[] = { "gpio11" };
+static const char * const dmic3_clk_groups[] = { "gpio12" };
+static const char * const dmic3_data_groups[] = { "gpio13" };
+static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
+static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
+static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
+static const char * const i2s1_clk_groups[] = { "gpio6" };
+static const char * const i2s1_ws_groups[] = { "gpio7" };
+static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
+static const char * const wsa_swr_clk_groups[] = { "gpio10" };
+static const char * const wsa_swr_data_groups[] = { "gpio11" };
+static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
+
+static const struct lpi_pingroup sm8250_groups[] = {
+ LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
+ LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
+ LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
+ LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
+ LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
+ LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
+ LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
+ LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
+ LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
+ LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
+ LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
+ LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
+};
+
+static const struct lpi_function sm8250_functions[] = {
+ LPI_FUNCTION(dmic1_clk),
+ LPI_FUNCTION(dmic1_data),
+ LPI_FUNCTION(dmic2_clk),
+ LPI_FUNCTION(dmic2_data),
+ LPI_FUNCTION(dmic3_clk),
+ LPI_FUNCTION(dmic3_data),
+ LPI_FUNCTION(i2s1_clk),
+ LPI_FUNCTION(i2s1_data),
+ LPI_FUNCTION(i2s1_ws),
+ LPI_FUNCTION(i2s2_clk),
+ LPI_FUNCTION(i2s2_data),
+ LPI_FUNCTION(i2s2_ws),
+ LPI_FUNCTION(qua_mi2s_data),
+ LPI_FUNCTION(qua_mi2s_sclk),
+ LPI_FUNCTION(qua_mi2s_ws),
+ LPI_FUNCTION(swr_rx_clk),
+ LPI_FUNCTION(swr_rx_data),
+ LPI_FUNCTION(swr_tx_clk),
+ LPI_FUNCTION(swr_tx_data),
+ LPI_FUNCTION(wsa_swr_clk),
+ LPI_FUNCTION(wsa_swr_data),
+};
+
+static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
+ .pins = sm8250_lpi_pins,
+ .npins = ARRAY_SIZE(sm8250_lpi_pins),
+ .groups = sm8250_groups,
+ .ngroups = ARRAY_SIZE(sm8250_groups),
+ .functions = sm8250_functions,
+ .nfunctions = ARRAY_SIZE(sm8250_functions),
+};
+
+static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
+ unsigned int addr)
+{
+ return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
+}
+
+static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
+ unsigned int addr, unsigned int val)
+{
+ iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
+
+ return 0;
+}
+
+static int lpi_gpio_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctrl->data->ngroups;
+}
+
+static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int group)
+{
+ struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctrl->data->groups[group].name;
+}
+
+static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int group,
+ const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = pctrl->data->groups[group].pins;
+ *num_pins = pctrl->data->groups[group].npins;
+
+ return 0;
+}
+
+static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
+ .get_groups_count = lpi_gpio_get_groups_count,
+ .get_group_name = lpi_gpio_get_group_name,
+ .get_group_pins = lpi_gpio_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctrl->data->nfunctions;
+}
+
+static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
+ unsigned int function)
+{
+ struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctrl->data->functions[function].name;
+}
+
+static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char *const **groups,
+ unsigned *const num_qgroups)
+{
+ struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pctrl->data->functions[function].groups;
+ *num_qgroups = pctrl->data->functions[function].ngroups;
+
+ return 0;
+}
+
+static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
+ unsigned int group_num)
+{
+ struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+ const struct lpi_pingroup *g = &pctrl->data->groups[group_num];
+ u32 val;
+ int i, pin = g->pin;
+
+ for (i = 0; i < g->nfuncs; i++) {
+ if (g->funcs[i] == function)
+ break;
+ }
+
+ if (WARN_ON(i == g->nfuncs))
+ return -EINVAL;
+
+ val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
+ u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
+ lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
+
+ return 0;
+}
+
+static const struct pinmux_ops lpi_gpio_pinmux_ops = {
+ .get_functions_count = lpi_gpio_get_functions_count,
+ .get_function_name = lpi_gpio_get_function_name,
+ .get_function_groups = lpi_gpio_get_function_groups,
+ .set_mux = lpi_gpio_set_mux,
+};
+
+static int lpi_config_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ unsigned int param = pinconf_to_config_param(*config);
+ struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
+ unsigned int arg = 0;
+ int is_out;
+ int pull;
+ u32 ctl_reg;
+
+ ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
+ is_out = ctl_reg & LPI_GPIO_OE_MASK;
+ pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (pull == LPI_GPIO_BIAS_DISABLE)
+ arg = 1;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (pull == LPI_GPIO_PULL_DOWN)
+ arg = 1;
+ break;
+ case PIN_CONFIG_BIAS_BUS_HOLD:
+ if (pull == LPI_GPIO_KEEPER)
+ arg = 1;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (pull == LPI_GPIO_PULL_UP)
+ arg = 1;
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ case PIN_CONFIG_OUTPUT:
+ if (is_out)
+ arg = 1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+ return 0;
+}
+
+static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
+ unsigned long *configs, unsigned int nconfs)
+{
+ struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
+ unsigned int param, arg, pullup, strength;
+ bool value, output_enabled = false;
+ const struct lpi_pingroup *g;
+ unsigned long sval;
+ int i, slew_offset;
+ u32 val;
+
+ g = &pctrl->data->groups[group];
+ for (i = 0; i < nconfs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ pullup = LPI_GPIO_BIAS_DISABLE;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ pullup = LPI_GPIO_PULL_DOWN;
+ break;
+ case PIN_CONFIG_BIAS_BUS_HOLD:
+ pullup = LPI_GPIO_KEEPER;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ pullup = LPI_GPIO_PULL_UP;
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ output_enabled = false;
+ break;
+ case PIN_CONFIG_OUTPUT:
+ output_enabled = true;
+ value = arg;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ strength = arg;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (arg > LPI_SLEW_RATE_MAX) {
+ dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
+ arg, group);
+ return -EINVAL;
+ }
+
+ slew_offset = g->slew_offset;
+ if (slew_offset == NO_SLEW)
+ break;
+
+ mutex_lock(&pctrl->slew_access_lock);
+
+ sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
+ sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
+ sval |= arg << slew_offset;
+ iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
+
+ mutex_unlock(&pctrl->slew_access_lock);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
+
+ u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
+ u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
+ LPI_GPIO_OUT_STRENGTH_MASK);
+ u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
+
+ lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
+
+ if (output_enabled) {
+ val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
+ lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops lpi_gpio_pinconf_ops = {
+ .is_generic = true,
+ .pin_config_group_get = lpi_config_get,
+ .pin_config_group_set = lpi_config_set,
+};
+
+static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
+{
+ struct lpi_pinctrl *state = gpiochip_get_data(chip);
+ unsigned long config;
+
+ config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
+
+ return lpi_config_set(state->ctrl, pin, &config, 1);
+}
+
+static int lpi_gpio_direction_output(struct gpio_chip *chip,
+ unsigned int pin, int val)
+{
+ struct lpi_pinctrl *state = gpiochip_get_data(chip);
+ unsigned long config;
+
+ config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
+
+ return lpi_config_set(state->ctrl, pin, &config, 1);
+}
+
+static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
+{
+ struct lpi_pinctrl *state = gpiochip_get_data(chip);
+
+ return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
+ LPI_GPIO_VALUE_IN_MASK;
+}
+
+static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
+{
+ struct lpi_pinctrl *state = gpiochip_get_data(chip);
+ unsigned long config;
+
+ config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
+
+ lpi_config_set(state->ctrl, pin, &config, 1);
+}
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/seq_file.h>
+
+static unsigned int lpi_regval_to_drive(u32 val)
+{
+ return (val + 1) * 2;
+}
+
+static void lpi_gpio_dbg_show_one(struct seq_file *s,
+ struct pinctrl_dev *pctldev,
+ struct gpio_chip *chip,
+ unsigned int offset,
+ unsigned int gpio)
+{
+ struct lpi_pinctrl *state = gpiochip_get_data(chip);
+ struct pinctrl_pin_desc pindesc;
+ unsigned int func;
+ int is_out;
+ int drive;
+ int pull;
+ u32 ctl_reg;
+
+ static const char * const pulls[] = {
+ "no pull",
+ "pull down",
+ "keeper",
+ "pull up"
+ };
+
+ pctldev = pctldev ? : state->ctrl;
+ pindesc = pctldev->desc->pins[offset];
+ ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
+ is_out = ctl_reg & LPI_GPIO_OE_MASK;
+
+ func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
+ drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
+ pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
+
+ seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
+ seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
+ seq_printf(s, " %s", pulls[pull]);
+}
+
+static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+ unsigned int gpio = chip->base;
+ unsigned int i;
+
+ for (i = 0; i < chip->ngpio; i++, gpio++) {
+ lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
+ seq_puts(s, "\n");
+ }
+}
+
+#else
+#define lpi_gpio_dbg_show NULL
+#endif
+
+static const struct gpio_chip lpi_gpio_template = {
+ .direction_input = lpi_gpio_direction_input,
+ .direction_output = lpi_gpio_direction_output,
+ .get = lpi_gpio_get,
+ .set = lpi_gpio_set,
+ .request = gpiochip_generic_request,
+ .free = gpiochip_generic_free,
+ .dbg_show = lpi_gpio_dbg_show,
+};
+
+static int lpi_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct lpi_pinctrl_variant_data *data;
+ struct device *dev = &pdev->dev;
+ struct lpi_pinctrl *pctrl;
+ int ret;
+
+ pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
+ if (!pctrl)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pctrl);
+
+ data = of_device_get_match_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ pctrl->data = data;
+ pctrl->dev = &pdev->dev;
+
+ pctrl->clks[0].id = "core";
+ pctrl->clks[1].id = "audio";
+
+ pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(pctrl->tlmm_base))
+ return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
+ "TLMM resource not provided\n");
+
+ pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(pctrl->slew_base))
+ return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
+ "Slew resource not provided\n");
+
+ ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
+ if (ret)
+ return dev_err_probe(dev, ret, "Can't get clocks\n");
+
+ ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
+ if (ret)
+ return dev_err_probe(dev, ret, "Can't enable clocks\n");
+
+ pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
+ pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
+ pctrl->desc.confops = &lpi_gpio_pinconf_ops;
+ pctrl->desc.owner = THIS_MODULE;
+ pctrl->desc.name = dev_name(dev);
+ pctrl->desc.pins = data->pins;
+ pctrl->desc.npins = data->npins;
+ pctrl->chip = lpi_gpio_template;
+ pctrl->chip.parent = dev;
+ pctrl->chip.base = -1;
+ pctrl->chip.ngpio = data->npins;
+ pctrl->chip.label = dev_name(dev);
+ pctrl->chip.of_gpio_n_cells = 2;
+ pctrl->chip.can_sleep = false;
+
+ mutex_init(&pctrl->slew_access_lock);
+
+ pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
+ if (IS_ERR(pctrl->ctrl)) {
+ ret = PTR_ERR(pctrl->ctrl);
+ dev_err(dev, "failed to add pin controller\n");
+ goto err_pinctrl;
+ }
+
+ ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
+ if (ret) {
+ dev_err(pctrl->dev, "can't add gpio chip\n");
+ goto err_pinctrl;
+ }
+
+ return 0;
+
+err_pinctrl:
+ mutex_destroy(&pctrl->slew_access_lock);
+ clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
+
+ return ret;
+}
+
+static int lpi_pinctrl_remove(struct platform_device *pdev)
+{
+ struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
+
+ mutex_destroy(&pctrl->slew_access_lock);
+ clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
+
+ return 0;
+}
+
+static const struct of_device_id lpi_pinctrl_of_match[] = {
+ {
+ .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
+ .data = &sm8250_lpi_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
+
+static struct platform_driver lpi_pinctrl_driver = {
+ .driver = {
+ .name = "qcom-lpass-lpi-pinctrl",
+ .of_match_table = lpi_pinctrl_of_match,
+ },
+ .probe = lpi_pinctrl_probe,
+ .remove = lpi_pinctrl_remove,
+};
+
+module_platform_driver(lpi_pinctrl_driver);
+MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 77a25bdf0da7..e051aecf95c4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -1449,3 +1449,5 @@ int msm_pinctrl_remove(struct platform_device *pdev)
}
EXPORT_SYMBOL(msm_pinctrl_remove);
+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8953.c b/drivers/pinctrl/qcom/pinctrl-msm8953.c
new file mode 100644
index 000000000000..e0c939ff3d54
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8953.c
@@ -0,0 +1,1844 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020, The Linux Foundation. All rights reserved.
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = 0x1000 * id, \
+ .io_reg = 0x4 + 0x1000 * id, \
+ .intr_cfg_reg = 0x8 + 0x1000 * id, \
+ .intr_status_reg = 0xc + 0x1000 * id, \
+ .intr_target_reg = 0x8 + 0x1000 * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 4, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+static const struct pinctrl_pin_desc msm8953_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "GPIO_119"),
+ PINCTRL_PIN(120, "GPIO_120"),
+ PINCTRL_PIN(121, "GPIO_121"),
+ PINCTRL_PIN(122, "GPIO_122"),
+ PINCTRL_PIN(123, "GPIO_123"),
+ PINCTRL_PIN(124, "GPIO_124"),
+ PINCTRL_PIN(125, "GPIO_125"),
+ PINCTRL_PIN(126, "GPIO_126"),
+ PINCTRL_PIN(127, "GPIO_127"),
+ PINCTRL_PIN(128, "GPIO_128"),
+ PINCTRL_PIN(129, "GPIO_129"),
+ PINCTRL_PIN(130, "GPIO_130"),
+ PINCTRL_PIN(131, "GPIO_131"),
+ PINCTRL_PIN(132, "GPIO_132"),
+ PINCTRL_PIN(133, "GPIO_133"),
+ PINCTRL_PIN(134, "GPIO_134"),
+ PINCTRL_PIN(135, "GPIO_135"),
+ PINCTRL_PIN(136, "GPIO_136"),
+ PINCTRL_PIN(137, "GPIO_137"),
+ PINCTRL_PIN(138, "GPIO_138"),
+ PINCTRL_PIN(139, "GPIO_139"),
+ PINCTRL_PIN(140, "GPIO_140"),
+ PINCTRL_PIN(141, "GPIO_141"),
+ PINCTRL_PIN(142, "SDC1_CLK"),
+ PINCTRL_PIN(143, "SDC1_CMD"),
+ PINCTRL_PIN(144, "SDC1_DATA"),
+ PINCTRL_PIN(145, "SDC1_RCLK"),
+ PINCTRL_PIN(146, "SDC2_CLK"),
+ PINCTRL_PIN(147, "SDC2_CMD"),
+ PINCTRL_PIN(148, "SDC2_DATA"),
+ PINCTRL_PIN(149, "QDSD_CLK"),
+ PINCTRL_PIN(150, "QDSD_CMD"),
+ PINCTRL_PIN(151, "QDSD_DATA0"),
+ PINCTRL_PIN(152, "QDSD_DATA1"),
+ PINCTRL_PIN(153, "QDSD_DATA2"),
+ PINCTRL_PIN(154, "QDSD_DATA3"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+DECLARE_MSM_GPIO_PINS(117);
+DECLARE_MSM_GPIO_PINS(118);
+DECLARE_MSM_GPIO_PINS(119);
+DECLARE_MSM_GPIO_PINS(120);
+DECLARE_MSM_GPIO_PINS(121);
+DECLARE_MSM_GPIO_PINS(122);
+DECLARE_MSM_GPIO_PINS(123);
+DECLARE_MSM_GPIO_PINS(124);
+DECLARE_MSM_GPIO_PINS(125);
+DECLARE_MSM_GPIO_PINS(126);
+DECLARE_MSM_GPIO_PINS(127);
+DECLARE_MSM_GPIO_PINS(128);
+DECLARE_MSM_GPIO_PINS(129);
+DECLARE_MSM_GPIO_PINS(130);
+DECLARE_MSM_GPIO_PINS(131);
+DECLARE_MSM_GPIO_PINS(132);
+DECLARE_MSM_GPIO_PINS(133);
+DECLARE_MSM_GPIO_PINS(134);
+DECLARE_MSM_GPIO_PINS(135);
+DECLARE_MSM_GPIO_PINS(136);
+DECLARE_MSM_GPIO_PINS(137);
+DECLARE_MSM_GPIO_PINS(138);
+DECLARE_MSM_GPIO_PINS(139);
+DECLARE_MSM_GPIO_PINS(140);
+DECLARE_MSM_GPIO_PINS(141);
+
+static const unsigned int qdsd_clk_pins[] = { 142 };
+static const unsigned int qdsd_cmd_pins[] = { 143 };
+static const unsigned int qdsd_data0_pins[] = { 144 };
+static const unsigned int qdsd_data1_pins[] = { 145 };
+static const unsigned int qdsd_data2_pins[] = { 146 };
+static const unsigned int qdsd_data3_pins[] = { 147 };
+static const unsigned int sdc1_clk_pins[] = { 148 };
+static const unsigned int sdc1_cmd_pins[] = { 149 };
+static const unsigned int sdc1_data_pins[] = { 150 };
+static const unsigned int sdc1_rclk_pins[] = { 151 };
+static const unsigned int sdc2_clk_pins[] = { 152 };
+static const unsigned int sdc2_cmd_pins[] = { 153 };
+static const unsigned int sdc2_data_pins[] = { 154 };
+
+enum msm8953_functions {
+ msm_mux_accel_int,
+ msm_mux_adsp_ext,
+ msm_mux_alsp_int,
+ msm_mux_atest_bbrx0,
+ msm_mux_atest_bbrx1,
+ msm_mux_atest_char,
+ msm_mux_atest_char0,
+ msm_mux_atest_char1,
+ msm_mux_atest_char2,
+ msm_mux_atest_char3,
+ msm_mux_atest_gpsadc_dtest0_native,
+ msm_mux_atest_gpsadc_dtest1_native,
+ msm_mux_atest_tsens,
+ msm_mux_atest_wlan0,
+ msm_mux_atest_wlan1,
+ msm_mux_bimc_dte0,
+ msm_mux_bimc_dte1,
+ msm_mux_blsp1_spi,
+ msm_mux_blsp3_spi,
+ msm_mux_blsp6_spi,
+ msm_mux_blsp7_spi,
+ msm_mux_blsp_i2c1,
+ msm_mux_blsp_i2c2,
+ msm_mux_blsp_i2c3,
+ msm_mux_blsp_i2c4,
+ msm_mux_blsp_i2c5,
+ msm_mux_blsp_i2c6,
+ msm_mux_blsp_i2c7,
+ msm_mux_blsp_i2c8,
+ msm_mux_blsp_spi1,
+ msm_mux_blsp_spi2,
+ msm_mux_blsp_spi3,
+ msm_mux_blsp_spi4,
+ msm_mux_blsp_spi5,
+ msm_mux_blsp_spi6,
+ msm_mux_blsp_spi7,
+ msm_mux_blsp_spi8,
+ msm_mux_blsp_uart2,
+ msm_mux_blsp_uart4,
+ msm_mux_blsp_uart5,
+ msm_mux_blsp_uart6,
+ msm_mux_cam0_ldo,
+ msm_mux_cam1_ldo,
+ msm_mux_cam1_rst,
+ msm_mux_cam1_standby,
+ msm_mux_cam2_rst,
+ msm_mux_cam2_standby,
+ msm_mux_cam3_rst,
+ msm_mux_cam3_standby,
+ msm_mux_cam_irq,
+ msm_mux_cam_mclk,
+ msm_mux_cap_int,
+ msm_mux_cci_async,
+ msm_mux_cci_i2c,
+ msm_mux_cci_timer0,
+ msm_mux_cci_timer1,
+ msm_mux_cci_timer2,
+ msm_mux_cci_timer3,
+ msm_mux_cci_timer4,
+ msm_mux_cdc_pdm0,
+ msm_mux_codec_int1,
+ msm_mux_codec_int2,
+ msm_mux_codec_reset,
+ msm_mux_cri_trng,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_dac_calib0,
+ msm_mux_dac_calib1,
+ msm_mux_dac_calib2,
+ msm_mux_dac_calib3,
+ msm_mux_dac_calib4,
+ msm_mux_dac_calib5,
+ msm_mux_dac_calib6,
+ msm_mux_dac_calib7,
+ msm_mux_dac_calib8,
+ msm_mux_dac_calib9,
+ msm_mux_dac_calib10,
+ msm_mux_dac_calib11,
+ msm_mux_dac_calib12,
+ msm_mux_dac_calib13,
+ msm_mux_dac_calib14,
+ msm_mux_dac_calib15,
+ msm_mux_dac_calib16,
+ msm_mux_dac_calib17,
+ msm_mux_dac_calib18,
+ msm_mux_dac_calib19,
+ msm_mux_dac_calib20,
+ msm_mux_dac_calib21,
+ msm_mux_dac_calib22,
+ msm_mux_dac_calib23,
+ msm_mux_dac_calib24,
+ msm_mux_dac_calib25,
+ msm_mux_dbg_out,
+ msm_mux_ddr_bist,
+ msm_mux_dmic0_clk,
+ msm_mux_dmic0_data,
+ msm_mux_ebi_cdc,
+ msm_mux_ebi_ch0,
+ msm_mux_ext_lpass,
+ msm_mux_flash_strobe,
+ msm_mux_fp_int,
+ msm_mux_gcc_gp1_clk_a,
+ msm_mux_gcc_gp1_clk_b,
+ msm_mux_gcc_gp2_clk_a,
+ msm_mux_gcc_gp2_clk_b,
+ msm_mux_gcc_gp3_clk_a,
+ msm_mux_gcc_gp3_clk_b,
+ msm_mux_gcc_plltest,
+ msm_mux_gcc_tlmm,
+ msm_mux_gpio,
+ msm_mux_gsm0_tx,
+ msm_mux_gsm1_tx,
+ msm_mux_gyro_int,
+ msm_mux_hall_int,
+ msm_mux_hdmi_int,
+ msm_mux_key_focus,
+ msm_mux_key_home,
+ msm_mux_key_snapshot,
+ msm_mux_key_volp,
+ msm_mux_ldo_en,
+ msm_mux_ldo_update,
+ msm_mux_lpass_slimbus,
+ msm_mux_lpass_slimbus0,
+ msm_mux_lpass_slimbus1,
+ msm_mux_m_voc,
+ msm_mux_mag_int,
+ msm_mux_mdp_vsync,
+ msm_mux_mipi_dsi0,
+ msm_mux_modem_tsync,
+ msm_mux_mss_lte,
+ msm_mux_nav_pps,
+ msm_mux_nav_pps_in_a,
+ msm_mux_nav_pps_in_b,
+ msm_mux_nav_tsync,
+ msm_mux_nfc_disable,
+ msm_mux_nfc_dwl,
+ msm_mux_nfc_irq,
+ msm_mux_ois_sync,
+ msm_mux_pa_indicator,
+ msm_mux_pbs0,
+ msm_mux_pbs1,
+ msm_mux_pbs2,
+ msm_mux_pressure_int,
+ msm_mux_pri_mi2s,
+ msm_mux_pri_mi2s_mclk_a,
+ msm_mux_pri_mi2s_mclk_b,
+ msm_mux_pri_mi2s_ws,
+ msm_mux_prng_rosc,
+ msm_mux_pwr_crypto_enabled_a,
+ msm_mux_pwr_crypto_enabled_b,
+ msm_mux_pwr_down,
+ msm_mux_pwr_modem_enabled_a,
+ msm_mux_pwr_modem_enabled_b,
+ msm_mux_pwr_nav_enabled_a,
+ msm_mux_pwr_nav_enabled_b,
+ msm_mux_qdss_cti_trig_in_a0,
+ msm_mux_qdss_cti_trig_in_a1,
+ msm_mux_qdss_cti_trig_in_b0,
+ msm_mux_qdss_cti_trig_in_b1,
+ msm_mux_qdss_cti_trig_out_a0,
+ msm_mux_qdss_cti_trig_out_a1,
+ msm_mux_qdss_cti_trig_out_b0,
+ msm_mux_qdss_cti_trig_out_b1,
+ msm_mux_qdss_traceclk_a,
+ msm_mux_qdss_traceclk_b,
+ msm_mux_qdss_tracectl_a,
+ msm_mux_qdss_tracectl_b,
+ msm_mux_qdss_tracedata_a,
+ msm_mux_qdss_tracedata_b,
+ msm_mux_sd_write,
+ msm_mux_sdcard_det,
+ msm_mux_sec_mi2s,
+ msm_mux_sec_mi2s_mclk_a,
+ msm_mux_sec_mi2s_mclk_b,
+ msm_mux_smb_int,
+ msm_mux_ss_switch,
+ msm_mux_ssbi_wtr1,
+ msm_mux_ts_resout,
+ msm_mux_ts_sample,
+ msm_mux_ts_xvdd,
+ msm_mux_tsens_max,
+ msm_mux_uim1_clk,
+ msm_mux_uim1_data,
+ msm_mux_uim1_present,
+ msm_mux_uim1_reset,
+ msm_mux_uim2_clk,
+ msm_mux_uim2_data,
+ msm_mux_uim2_present,
+ msm_mux_uim2_reset,
+ msm_mux_uim_batt,
+ msm_mux_us_emitter,
+ msm_mux_us_euro,
+ msm_mux_wcss_bt,
+ msm_mux_wcss_fm,
+ msm_mux_wcss_wlan,
+ msm_mux_wcss_wlan0,
+ msm_mux_wcss_wlan1,
+ msm_mux_wcss_wlan2,
+ msm_mux_wsa_en,
+ msm_mux_wsa_io,
+ msm_mux_wsa_irq,
+ msm_mux__,
+};
+
+static const char * const accel_int_groups[] = {
+ "gpio42",
+};
+
+static const char * const adsp_ext_groups[] = {
+ "gpio1",
+};
+
+static const char * const alsp_int_groups[] = {
+ "gpio43",
+};
+
+static const char * const atest_bbrx0_groups[] = {
+ "gpio17",
+};
+
+static const char * const atest_bbrx1_groups[] = {
+ "gpio16",
+};
+
+static const char * const atest_char0_groups[] = {
+ "gpio68",
+};
+
+static const char * const atest_char1_groups[] = {
+ "gpio67",
+};
+
+static const char * const atest_char2_groups[] = {
+ "gpio75",
+};
+
+static const char * const atest_char3_groups[] = {
+ "gpio63",
+};
+
+static const char * const atest_char_groups[] = {
+ "gpio120",
+};
+
+static const char * const atest_gpsadc_dtest0_native_groups[] = {
+ "gpio7",
+};
+
+static const char * const atest_gpsadc_dtest1_native_groups[] = {
+ "gpio18",
+};
+
+static const char * const atest_tsens_groups[] = {
+ "gpio120",
+};
+
+static const char * const atest_wlan0_groups[] = {
+ "gpio22",
+};
+
+static const char * const atest_wlan1_groups[] = {
+ "gpio23",
+};
+
+static const char * const bimc_dte0_groups[] = {
+ "gpio63", "gpio65",
+};
+
+static const char * const bimc_dte1_groups[] = {
+ "gpio121", "gpio122",
+};
+
+static const char * const blsp1_spi_groups[] = {
+ "gpio35", "gpio36",
+};
+
+static const char * const blsp3_spi_groups[] = {
+ "gpio41", "gpio50",
+};
+
+static const char * const blsp6_spi_groups[] = {
+ "gpio47", "gpio48",
+};
+
+static const char * const blsp7_spi_groups[] = {
+ "gpio89", "gpio90",
+};
+
+static const char * const blsp_i2c1_groups[] = {
+ "gpio2", "gpio3",
+};
+
+static const char * const blsp_i2c2_groups[] = {
+ "gpio6", "gpio7",
+};
+
+static const char * const blsp_i2c3_groups[] = {
+ "gpio10", "gpio11",
+};
+
+static const char * const blsp_i2c4_groups[] = {
+ "gpio14", "gpio15",
+};
+
+static const char * const blsp_i2c5_groups[] = {
+ "gpio18", "gpio19",
+};
+
+static const char * const blsp_i2c6_groups[] = {
+ "gpio22", "gpio23",
+};
+
+static const char * const blsp_i2c7_groups[] = {
+ "gpio135", "gpio136",
+};
+
+static const char * const blsp_i2c8_groups[] = {
+ "gpio98", "gpio99",
+};
+
+static const char * const blsp_spi1_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+
+static const char * const blsp_spi2_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+
+static const char * const blsp_spi3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+
+static const char * const blsp_spi4_groups[] = {
+ "gpio12", "gpio13", "gpio14", "gpio15",
+};
+
+static const char * const blsp_spi5_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19",
+};
+
+static const char * const blsp_spi6_groups[] = {
+ "gpio20", "gpio21", "gpio22", "gpio23",
+};
+
+static const char * const blsp_spi7_groups[] = {
+ "gpio135", "gpio136", "gpio137", "gpio138",
+};
+
+static const char * const blsp_spi8_groups[] = {
+ "gpio96", "gpio97", "gpio98", "gpio99",
+};
+
+static const char * const blsp_uart2_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+
+static const char * const blsp_uart4_groups[] = {
+ "gpio12", "gpio13", "gpio14", "gpio15",
+};
+
+static const char * const blsp_uart5_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19",
+};
+
+static const char * const blsp_uart6_groups[] = {
+ "gpio20", "gpio21", "gpio22", "gpio23",
+};
+
+static const char * const cam0_ldo_groups[] = {
+ "gpio50",
+};
+
+static const char * const cam1_ldo_groups[] = {
+ "gpio134",
+};
+
+static const char * const cam1_rst_groups[] = {
+ "gpio40",
+};
+
+static const char * const cam1_standby_groups[] = {
+ "gpio39",
+};
+
+static const char * const cam2_rst_groups[] = {
+ "gpio129",
+};
+
+static const char * const cam2_standby_groups[] = {
+ "gpio130",
+};
+
+static const char * const cam3_rst_groups[] = {
+ "gpio131",
+};
+
+static const char * const cam3_standby_groups[] = {
+ "gpio132",
+};
+
+static const char * const cam_irq_groups[] = {
+ "gpio35",
+};
+
+static const char * const cam_mclk_groups[] = {
+ "gpio26", "gpio27", "gpio28", "gpio128",
+};
+
+static const char * const cap_int_groups[] = {
+ "gpio13",
+};
+
+static const char * const cci_async_groups[] = {
+ "gpio38",
+};
+
+static const char * const cci_i2c_groups[] = {
+ "gpio29", "gpio30", "gpio31", "gpio32",
+};
+
+static const char * const cci_timer0_groups[] = {
+ "gpio33",
+};
+
+static const char * const cci_timer1_groups[] = {
+ "gpio34",
+};
+
+static const char * const cci_timer2_groups[] = {
+ "gpio35",
+};
+
+static const char * const cci_timer3_groups[] = {
+ "gpio36",
+};
+
+static const char * const cci_timer4_groups[] = {
+ "gpio41",
+};
+
+static const char * const cdc_pdm0_groups[] = {
+ "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73",
+ "gpio74",
+};
+
+static const char * const codec_int1_groups[] = {
+ "gpio73",
+};
+
+static const char * const codec_int2_groups[] = {
+ "gpio74",
+};
+
+static const char * const codec_reset_groups[] = {
+ "gpio67",
+};
+
+static const char * const cri_trng0_groups[] = {
+ "gpio85",
+};
+
+static const char * const cri_trng1_groups[] = {
+ "gpio86",
+};
+
+static const char * const cri_trng_groups[] = {
+ "gpio87",
+};
+
+static const char * const dac_calib0_groups[] = {
+ "gpio4",
+};
+
+static const char * const dac_calib1_groups[] = {
+ "gpio12",
+};
+
+static const char * const dac_calib2_groups[] = {
+ "gpio13",
+};
+
+static const char * const dac_calib3_groups[] = {
+ "gpio28",
+};
+
+static const char * const dac_calib4_groups[] = {
+ "gpio29",
+};
+
+static const char * const dac_calib5_groups[] = {
+ "gpio39",
+};
+
+static const char * const dac_calib6_groups[] = {
+ "gpio40",
+};
+
+static const char * const dac_calib7_groups[] = {
+ "gpio41",
+};
+
+static const char * const dac_calib8_groups[] = {
+ "gpio42",
+};
+
+static const char * const dac_calib9_groups[] = {
+ "gpio43",
+};
+
+static const char * const dac_calib10_groups[] = {
+ "gpio44",
+};
+
+static const char * const dac_calib11_groups[] = {
+ "gpio45",
+};
+
+static const char * const dac_calib12_groups[] = {
+ "gpio46",
+};
+
+static const char * const dac_calib13_groups[] = {
+ "gpio47",
+};
+
+static const char * const dac_calib14_groups[] = {
+ "gpio48",
+};
+
+static const char * const dac_calib15_groups[] = {
+ "gpio20",
+};
+
+static const char * const dac_calib16_groups[] = {
+ "gpio21",
+};
+
+static const char * const dac_calib17_groups[] = {
+ "gpio67",
+};
+
+static const char * const dac_calib18_groups[] = {
+ "gpio115",
+};
+
+static const char * const dac_calib19_groups[] = {
+ "gpio30",
+};
+
+static const char * const dac_calib20_groups[] = {
+ "gpio128",
+};
+
+static const char * const dac_calib21_groups[] = {
+ "gpio129",
+};
+
+static const char * const dac_calib22_groups[] = {
+ "gpio130",
+};
+
+static const char * const dac_calib23_groups[] = {
+ "gpio131",
+};
+
+static const char * const dac_calib24_groups[] = {
+ "gpio132",
+};
+
+static const char * const dac_calib25_groups[] = {
+ "gpio133",
+};
+
+static const char * const dbg_out_groups[] = {
+ "gpio63",
+};
+
+static const char * const ddr_bist_groups[] = {
+ "gpio129", "gpio130", "gpio131", "gpio132",
+};
+
+static const char * const dmic0_clk_groups[] = {
+ "gpio89",
+};
+
+static const char * const dmic0_data_groups[] = {
+ "gpio90",
+};
+
+static const char * const ebi_cdc_groups[] = {
+ "gpio67", "gpio69", "gpio118", "gpio119", "gpio120", "gpio123",
+};
+
+static const char * const ebi_ch0_groups[] = {
+ "gpio75",
+};
+
+static const char * const ext_lpass_groups[] = {
+ "gpio81",
+};
+
+static const char * const flash_strobe_groups[] = {
+ "gpio33", "gpio34",
+};
+
+static const char * const fp_int_groups[] = {
+ "gpio48",
+};
+
+static const char * const gcc_gp1_clk_a_groups[] = {
+ "gpio42",
+};
+
+static const char * const gcc_gp1_clk_b_groups[] = {
+ "gpio6", "gpio41",
+};
+
+static const char * const gcc_gp2_clk_a_groups[] = {
+ "gpio43",
+};
+
+static const char * const gcc_gp2_clk_b_groups[] = {
+ "gpio10",
+};
+
+static const char * const gcc_gp3_clk_a_groups[] = {
+ "gpio44",
+};
+
+static const char * const gcc_gp3_clk_b_groups[] = {
+ "gpio11",
+};
+
+static const char * const gcc_plltest_groups[] = {
+ "gpio98", "gpio99",
+};
+
+static const char * const gcc_tlmm_groups[] = {
+ "gpio87",
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
+ "gpio141",
+};
+
+static const char * const gsm0_tx_groups[] = {
+ "gpio117",
+};
+
+static const char * const gsm1_tx_groups[] = {
+ "gpio115",
+};
+
+static const char * const gyro_int_groups[] = {
+ "gpio45",
+};
+
+static const char * const hall_int_groups[] = {
+ "gpio12",
+};
+
+static const char * const hdmi_int_groups[] = {
+ "gpio90",
+};
+
+static const char * const key_focus_groups[] = {
+ "gpio87",
+};
+
+static const char * const key_home_groups[] = {
+ "gpio88",
+};
+
+static const char * const key_snapshot_groups[] = {
+ "gpio86",
+};
+
+static const char * const key_volp_groups[] = {
+ "gpio85",
+};
+
+static const char * const ldo_en_groups[] = {
+ "gpio5",
+};
+
+static const char * const ldo_update_groups[] = {
+ "gpio4",
+};
+
+static const char * const lpass_slimbus0_groups[] = {
+ "gpio71",
+};
+
+static const char * const lpass_slimbus1_groups[] = {
+ "gpio72",
+};
+
+static const char * const lpass_slimbus_groups[] = {
+ "gpio70",
+};
+
+static const char * const m_voc_groups[] = {
+ "gpio17", "gpio21",
+};
+
+static const char * const mag_int_groups[] = {
+ "gpio44",
+};
+
+static const char * const mdp_vsync_groups[] = {
+ "gpio24", "gpio25",
+};
+
+static const char * const mipi_dsi0_groups[] = {
+ "gpio61",
+};
+
+static const char * const modem_tsync_groups[] = {
+ "gpio113",
+};
+
+static const char * const mss_lte_groups[] = {
+ "gpio82", "gpio83",
+};
+
+static const char * const nav_pps_groups[] = {
+ "gpio113",
+};
+
+static const char * const nav_pps_in_a_groups[] = {
+ "gpio111",
+};
+
+static const char * const nav_pps_in_b_groups[] = {
+ "gpio113",
+};
+
+static const char * const nav_tsync_groups[] = {
+ "gpio113",
+};
+
+static const char * const nfc_disable_groups[] = {
+ "gpio16",
+};
+
+static const char * const nfc_dwl_groups[] = {
+ "gpio62",
+};
+
+static const char * const nfc_irq_groups[] = {
+ "gpio17",
+};
+
+static const char * const ois_sync_groups[] = {
+ "gpio36",
+};
+
+static const char * const pa_indicator_groups[] = {
+ "gpio112",
+};
+
+static const char * const pbs0_groups[] = {
+ "gpio85",
+};
+
+static const char * const pbs1_groups[] = {
+ "gpio86",
+};
+
+static const char * const pbs2_groups[] = {
+ "gpio87",
+};
+
+static const char * const pressure_int_groups[] = {
+ "gpio46",
+};
+
+static const char * const pri_mi2s_groups[] = {
+ "gpio66", "gpio88", "gpio91", "gpio93", "gpio94", "gpio95",
+};
+
+static const char * const pri_mi2s_mclk_a_groups[] = {
+ "gpio25",
+};
+
+static const char * const pri_mi2s_mclk_b_groups[] = {
+ "gpio69",
+};
+
+static const char * const pri_mi2s_ws_groups[] = {
+ "gpio92",
+};
+
+static const char * const prng_rosc_groups[] = {
+ "gpio2",
+};
+
+static const char * const pwr_crypto_enabled_a_groups[] = {
+ "gpio36",
+};
+
+static const char * const pwr_crypto_enabled_b_groups[] = {
+ "gpio13",
+};
+
+static const char * const pwr_down_groups[] = {
+ "gpio89",
+};
+
+static const char * const pwr_modem_enabled_a_groups[] = {
+ "gpio29",
+};
+
+static const char * const pwr_modem_enabled_b_groups[] = {
+ "gpio9",
+};
+
+static const char * const pwr_nav_enabled_a_groups[] = {
+ "gpio35",
+};
+
+static const char * const pwr_nav_enabled_b_groups[] = {
+ "gpio12",
+};
+
+static const char * const qdss_cti_trig_in_a0_groups[] = {
+ "gpio17",
+};
+
+static const char * const qdss_cti_trig_in_a1_groups[] = {
+ "gpio91",
+};
+
+static const char * const qdss_cti_trig_in_b0_groups[] = {
+ "gpio21",
+};
+
+static const char * const qdss_cti_trig_in_b1_groups[] = {
+ "gpio48",
+};
+
+static const char * const qdss_cti_trig_out_a0_groups[] = {
+ "gpio41",
+};
+
+static const char * const qdss_cti_trig_out_a1_groups[] = {
+ "gpio3",
+};
+
+static const char * const qdss_cti_trig_out_b0_groups[] = {
+ "gpio2",
+};
+
+static const char * const qdss_cti_trig_out_b1_groups[] = {
+ "gpio25",
+};
+
+static const char * const qdss_traceclk_a_groups[] = {
+ "gpio16",
+};
+
+static const char * const qdss_traceclk_b_groups[] = {
+ "gpio22",
+};
+
+static const char * const qdss_tracectl_a_groups[] = {
+ "gpio18",
+};
+
+static const char * const qdss_tracectl_b_groups[] = {
+ "gpio20",
+};
+
+static const char * const qdss_tracedata_a_groups[] = {
+ "gpio19", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
+ "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio38", "gpio39",
+ "gpio40", "gpio50",
+};
+
+static const char * const qdss_tracedata_b_groups[] = {
+ "gpio8", "gpio9", "gpio12", "gpio13", "gpio23", "gpio42", "gpio43",
+ "gpio44", "gpio45", "gpio46", "gpio47", "gpio66", "gpio86", "gpio87",
+ "gpio88", "gpio92",
+};
+
+static const char * const sd_write_groups[] = {
+ "gpio50",
+};
+
+static const char * const sdcard_det_groups[] = {
+ "gpio133",
+};
+
+static const char * const sec_mi2s_groups[] = {
+ "gpio135", "gpio136", "gpio137", "gpio138",
+};
+
+static const char * const sec_mi2s_mclk_a_groups[] = {
+ "gpio25",
+};
+
+static const char * const sec_mi2s_mclk_b_groups[] = {
+ "gpio66",
+};
+
+static const char * const smb_int_groups[] = {
+ "gpio1",
+};
+
+static const char * const ss_switch_groups[] = {
+ "gpio139",
+};
+
+static const char * const ssbi_wtr1_groups[] = {
+ "gpio114", "gpio123",
+};
+
+static const char * const ts_resout_groups[] = {
+ "gpio64",
+};
+
+static const char * const ts_sample_groups[] = {
+ "gpio65",
+};
+
+static const char * const ts_xvdd_groups[] = {
+ "gpio60",
+};
+
+static const char * const tsens_max_groups[] = {
+ "gpio139",
+};
+
+static const char * const uim1_clk_groups[] = {
+ "gpio52",
+};
+
+static const char * const uim1_data_groups[] = {
+ "gpio51",
+};
+
+static const char * const uim1_present_groups[] = {
+ "gpio54",
+};
+
+static const char * const uim1_reset_groups[] = {
+ "gpio53",
+};
+
+static const char * const uim2_clk_groups[] = {
+ "gpio56",
+};
+
+static const char * const uim2_data_groups[] = {
+ "gpio55",
+};
+
+static const char * const uim2_present_groups[] = {
+ "gpio58",
+};
+
+static const char * const uim2_reset_groups[] = {
+ "gpio57",
+};
+
+static const char * const uim_batt_groups[] = {
+ "gpio49",
+};
+
+static const char * const us_emitter_groups[] = {
+ "gpio68",
+};
+
+static const char * const us_euro_groups[] = {
+ "gpio63",
+};
+
+static const char * const wcss_bt_groups[] = {
+ "gpio75", "gpio83", "gpio84",
+};
+
+static const char * const wcss_fm_groups[] = {
+ "gpio81", "gpio82",
+};
+
+static const char * const wcss_wlan0_groups[] = {
+ "gpio78",
+};
+
+static const char * const wcss_wlan1_groups[] = {
+ "gpio77",
+};
+
+static const char * const wcss_wlan2_groups[] = {
+ "gpio76",
+};
+
+static const char * const wcss_wlan_groups[] = {
+ "gpio79", "gpio80",
+};
+
+static const char * const wsa_en_groups[] = {
+ "gpio96",
+};
+
+static const char * const wsa_io_groups[] = {
+ "gpio94", "gpio95",
+};
+
+static const char * const wsa_irq_groups[] = {
+ "gpio97",
+};
+
+static const struct msm_function msm8953_functions[] = {
+ FUNCTION(accel_int),
+ FUNCTION(adsp_ext),
+ FUNCTION(alsp_int),
+ FUNCTION(atest_bbrx0),
+ FUNCTION(atest_bbrx1),
+ FUNCTION(atest_char),
+ FUNCTION(atest_char0),
+ FUNCTION(atest_char1),
+ FUNCTION(atest_char2),
+ FUNCTION(atest_char3),
+ FUNCTION(atest_gpsadc_dtest0_native),
+ FUNCTION(atest_gpsadc_dtest1_native),
+ FUNCTION(atest_tsens),
+ FUNCTION(atest_wlan0),
+ FUNCTION(atest_wlan1),
+ FUNCTION(bimc_dte0),
+ FUNCTION(bimc_dte1),
+ FUNCTION(blsp1_spi),
+ FUNCTION(blsp3_spi),
+ FUNCTION(blsp6_spi),
+ FUNCTION(blsp7_spi),
+ FUNCTION(blsp_i2c1),
+ FUNCTION(blsp_i2c2),
+ FUNCTION(blsp_i2c3),
+ FUNCTION(blsp_i2c4),
+ FUNCTION(blsp_i2c5),
+ FUNCTION(blsp_i2c6),
+ FUNCTION(blsp_i2c7),
+ FUNCTION(blsp_i2c8),
+ FUNCTION(blsp_spi1),
+ FUNCTION(blsp_spi2),
+ FUNCTION(blsp_spi3),
+ FUNCTION(blsp_spi4),
+ FUNCTION(blsp_spi5),
+ FUNCTION(blsp_spi6),
+ FUNCTION(blsp_spi7),
+ FUNCTION(blsp_spi8),
+ FUNCTION(blsp_uart2),
+ FUNCTION(blsp_uart4),
+ FUNCTION(blsp_uart5),
+ FUNCTION(blsp_uart6),
+ FUNCTION(cam0_ldo),
+ FUNCTION(cam1_ldo),
+ FUNCTION(cam1_rst),
+ FUNCTION(cam1_standby),
+ FUNCTION(cam2_rst),
+ FUNCTION(cam2_standby),
+ FUNCTION(cam3_rst),
+ FUNCTION(cam3_standby),
+ FUNCTION(cam_irq),
+ FUNCTION(cam_mclk),
+ FUNCTION(cap_int),
+ FUNCTION(cci_async),
+ FUNCTION(cci_i2c),
+ FUNCTION(cci_timer0),
+ FUNCTION(cci_timer1),
+ FUNCTION(cci_timer2),
+ FUNCTION(cci_timer3),
+ FUNCTION(cci_timer4),
+ FUNCTION(cdc_pdm0),
+ FUNCTION(codec_int1),
+ FUNCTION(codec_int2),
+ FUNCTION(codec_reset),
+ FUNCTION(cri_trng),
+ FUNCTION(cri_trng0),
+ FUNCTION(cri_trng1),
+ FUNCTION(dac_calib0),
+ FUNCTION(dac_calib1),
+ FUNCTION(dac_calib10),
+ FUNCTION(dac_calib11),
+ FUNCTION(dac_calib12),
+ FUNCTION(dac_calib13),
+ FUNCTION(dac_calib14),
+ FUNCTION(dac_calib15),
+ FUNCTION(dac_calib16),
+ FUNCTION(dac_calib17),
+ FUNCTION(dac_calib18),
+ FUNCTION(dac_calib19),
+ FUNCTION(dac_calib2),
+ FUNCTION(dac_calib20),
+ FUNCTION(dac_calib21),
+ FUNCTION(dac_calib22),
+ FUNCTION(dac_calib23),
+ FUNCTION(dac_calib24),
+ FUNCTION(dac_calib25),
+ FUNCTION(dac_calib3),
+ FUNCTION(dac_calib4),
+ FUNCTION(dac_calib5),
+ FUNCTION(dac_calib6),
+ FUNCTION(dac_calib7),
+ FUNCTION(dac_calib8),
+ FUNCTION(dac_calib9),
+ FUNCTION(dbg_out),
+ FUNCTION(ddr_bist),
+ FUNCTION(dmic0_clk),
+ FUNCTION(dmic0_data),
+ FUNCTION(ebi_cdc),
+ FUNCTION(ebi_ch0),
+ FUNCTION(ext_lpass),
+ FUNCTION(flash_strobe),
+ FUNCTION(fp_int),
+ FUNCTION(gcc_gp1_clk_a),
+ FUNCTION(gcc_gp1_clk_b),
+ FUNCTION(gcc_gp2_clk_a),
+ FUNCTION(gcc_gp2_clk_b),
+ FUNCTION(gcc_gp3_clk_a),
+ FUNCTION(gcc_gp3_clk_b),
+ FUNCTION(gcc_plltest),
+ FUNCTION(gcc_tlmm),
+ FUNCTION(gpio),
+ FUNCTION(gsm0_tx),
+ FUNCTION(gsm1_tx),
+ FUNCTION(gyro_int),
+ FUNCTION(hall_int),
+ FUNCTION(hdmi_int),
+ FUNCTION(key_focus),
+ FUNCTION(key_home),
+ FUNCTION(key_snapshot),
+ FUNCTION(key_volp),
+ FUNCTION(ldo_en),
+ FUNCTION(ldo_update),
+ FUNCTION(lpass_slimbus),
+ FUNCTION(lpass_slimbus0),
+ FUNCTION(lpass_slimbus1),
+ FUNCTION(m_voc),
+ FUNCTION(mag_int),
+ FUNCTION(mdp_vsync),
+ FUNCTION(mipi_dsi0),
+ FUNCTION(modem_tsync),
+ FUNCTION(mss_lte),
+ FUNCTION(nav_pps),
+ FUNCTION(nav_pps_in_a),
+ FUNCTION(nav_pps_in_b),
+ FUNCTION(nav_tsync),
+ FUNCTION(nfc_disable),
+ FUNCTION(nfc_dwl),
+ FUNCTION(nfc_irq),
+ FUNCTION(ois_sync),
+ FUNCTION(pa_indicator),
+ FUNCTION(pbs0),
+ FUNCTION(pbs1),
+ FUNCTION(pbs2),
+ FUNCTION(pressure_int),
+ FUNCTION(pri_mi2s),
+ FUNCTION(pri_mi2s_mclk_a),
+ FUNCTION(pri_mi2s_mclk_b),
+ FUNCTION(pri_mi2s_ws),
+ FUNCTION(prng_rosc),
+ FUNCTION(pwr_crypto_enabled_a),
+ FUNCTION(pwr_crypto_enabled_b),
+ FUNCTION(pwr_down),
+ FUNCTION(pwr_modem_enabled_a),
+ FUNCTION(pwr_modem_enabled_b),
+ FUNCTION(pwr_nav_enabled_a),
+ FUNCTION(pwr_nav_enabled_b),
+ FUNCTION(qdss_cti_trig_in_a0),
+ FUNCTION(qdss_cti_trig_in_a1),
+ FUNCTION(qdss_cti_trig_in_b0),
+ FUNCTION(qdss_cti_trig_in_b1),
+ FUNCTION(qdss_cti_trig_out_a0),
+ FUNCTION(qdss_cti_trig_out_a1),
+ FUNCTION(qdss_cti_trig_out_b0),
+ FUNCTION(qdss_cti_trig_out_b1),
+ FUNCTION(qdss_traceclk_a),
+ FUNCTION(qdss_traceclk_b),
+ FUNCTION(qdss_tracectl_a),
+ FUNCTION(qdss_tracectl_b),
+ FUNCTION(qdss_tracedata_a),
+ FUNCTION(qdss_tracedata_b),
+ FUNCTION(sd_write),
+ FUNCTION(sdcard_det),
+ FUNCTION(sec_mi2s),
+ FUNCTION(sec_mi2s_mclk_a),
+ FUNCTION(sec_mi2s_mclk_b),
+ FUNCTION(smb_int),
+ FUNCTION(ss_switch),
+ FUNCTION(ssbi_wtr1),
+ FUNCTION(ts_resout),
+ FUNCTION(ts_sample),
+ FUNCTION(ts_xvdd),
+ FUNCTION(tsens_max),
+ FUNCTION(uim1_clk),
+ FUNCTION(uim1_data),
+ FUNCTION(uim1_present),
+ FUNCTION(uim1_reset),
+ FUNCTION(uim2_clk),
+ FUNCTION(uim2_data),
+ FUNCTION(uim2_present),
+ FUNCTION(uim2_reset),
+ FUNCTION(uim_batt),
+ FUNCTION(us_emitter),
+ FUNCTION(us_euro),
+ FUNCTION(wcss_bt),
+ FUNCTION(wcss_fm),
+ FUNCTION(wcss_wlan),
+ FUNCTION(wcss_wlan0),
+ FUNCTION(wcss_wlan1),
+ FUNCTION(wcss_wlan2),
+ FUNCTION(wsa_en),
+ FUNCTION(wsa_io),
+ FUNCTION(wsa_irq),
+};
+
+static const struct msm_pingroup msm8953_groups[] = {
+ PINGROUP(0, blsp_spi1, _, _, _, _, _, _, _, _),
+ PINGROUP(1, blsp_spi1, adsp_ext, _, _, _, _, _, _, _),
+ PINGROUP(2, blsp_spi1, blsp_i2c1, prng_rosc, _, _, _, qdss_cti_trig_out_b0, _, _),
+ PINGROUP(3, blsp_spi1, blsp_i2c1, _, _, _, qdss_cti_trig_out_a1, _, _, _),
+ PINGROUP(4, blsp_spi2, blsp_uart2, ldo_update, _, dac_calib0, _, _, _, _),
+ PINGROUP(5, blsp_spi2, blsp_uart2, ldo_en, _, _, _, _, _, _),
+ PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, _, _, _, _, _),
+ PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, _, atest_gpsadc_dtest0_native, _, _, _, _),
+ PINGROUP(8, blsp_spi3, _, _, qdss_tracedata_b, _, _, _, _, _),
+ PINGROUP(9, blsp_spi3, pwr_modem_enabled_b, _, _, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(10, blsp_spi3, blsp_i2c3, gcc_gp2_clk_b, _, _, _, _, _, _),
+ PINGROUP(11, blsp_spi3, blsp_i2c3, gcc_gp3_clk_b, _, _, _, _, _, _),
+ PINGROUP(12, blsp_spi4, blsp_uart4, pwr_nav_enabled_b, _, _,
+ qdss_tracedata_b, _, dac_calib1, _),
+ PINGROUP(13, blsp_spi4, blsp_uart4, pwr_crypto_enabled_b, _, _, _,
+ qdss_tracedata_b, _, dac_calib2),
+ PINGROUP(14, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _),
+ PINGROUP(15, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _),
+ PINGROUP(16, blsp_spi5, blsp_uart5, _, _, qdss_traceclk_a, _, atest_bbrx1, _, _),
+ PINGROUP(17, blsp_spi5, blsp_uart5, m_voc, qdss_cti_trig_in_a0, _, atest_bbrx0, _, _, _),
+ PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5,
+ qdss_tracectl_a, _, atest_gpsadc_dtest1_native, _, _, _),
+ PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(20, blsp_spi6, blsp_uart6, _, _, _, qdss_tracectl_b, _, dac_calib15, _),
+ PINGROUP(21, blsp_spi6, blsp_uart6, m_voc, _, _, _, qdss_cti_trig_in_b0, _, dac_calib16),
+ PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_traceclk_b, _, atest_wlan0, _, _, _),
+ PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_tracedata_b, _, atest_wlan1, _, _, _),
+ PINGROUP(24, mdp_vsync, _, _, _, _, _, _, _, _),
+ PINGROUP(25, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a,
+ qdss_cti_trig_out_b1, _, _, _, _, _),
+ PINGROUP(26, cam_mclk, _, _, _, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(27, cam_mclk, _, _, _, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(28, cam_mclk, _, _, _, qdss_tracedata_a, _, dac_calib3, _, _),
+ PINGROUP(29, cci_i2c, pwr_modem_enabled_a, _, _, _, qdss_tracedata_a, _, dac_calib4, _),
+ PINGROUP(30, cci_i2c, _, _, _, qdss_tracedata_a, _, dac_calib19, _, _),
+ PINGROUP(31, cci_i2c, _, _, _, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(32, cci_i2c, _, _, _, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(33, cci_timer0, _, _, _, _, qdss_tracedata_a, _, _, _),
+ PINGROUP(34, cci_timer1, _, _, _, _, qdss_tracedata_a, _, _, _),
+ PINGROUP(35, cci_timer2, blsp1_spi, pwr_nav_enabled_a, _, _, _, qdss_tracedata_a, _, _),
+ PINGROUP(36, cci_timer3, blsp1_spi, _, pwr_crypto_enabled_a, _, _, _, qdss_tracedata_a, _),
+ PINGROUP(37, _, _, _, _, _, _, _, _, _),
+ PINGROUP(38, cci_async, _, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(39, _, _, _, qdss_tracedata_a, _, dac_calib5, _, _, _),
+ PINGROUP(40, _, _, qdss_tracedata_a, _, dac_calib6, _, _, _, _),
+ PINGROUP(41, cci_timer4, blsp3_spi, gcc_gp1_clk_b, _, _,
+ qdss_cti_trig_out_a0, _, dac_calib7, _),
+ PINGROUP(42, gcc_gp1_clk_a, qdss_tracedata_b, _, dac_calib8, _, _, _, _, _),
+ PINGROUP(43, gcc_gp2_clk_a, qdss_tracedata_b, _, dac_calib9, _, _, _, _, _),
+ PINGROUP(44, gcc_gp3_clk_a, qdss_tracedata_b, _, dac_calib10, _, _, _, _, _),
+ PINGROUP(45, _, qdss_tracedata_b, _, dac_calib11, _, _, _, _, _),
+ PINGROUP(46, qdss_tracedata_b, _, dac_calib12, _, _, _, _, _, _),
+ PINGROUP(47, blsp6_spi, qdss_tracedata_b, _, dac_calib13, _, _, _, _, _),
+ PINGROUP(48, blsp6_spi, _, qdss_cti_trig_in_b1, _, dac_calib14, _, _, _, _),
+ PINGROUP(49, uim_batt, _, _, _, _, _, _, _, _),
+ PINGROUP(50, blsp3_spi, sd_write, _, _, _, qdss_tracedata_a, _, _, _),
+ PINGROUP(51, uim1_data, _, _, _, _, _, _, _, _),
+ PINGROUP(52, uim1_clk, _, _, _, _, _, _, _, _),
+ PINGROUP(53, uim1_reset, _, _, _, _, _, _, _, _),
+ PINGROUP(54, uim1_present, _, _, _, _, _, _, _, _),
+ PINGROUP(55, uim2_data, _, _, _, _, _, _, _, _),
+ PINGROUP(56, uim2_clk, _, _, _, _, _, _, _, _),
+ PINGROUP(57, uim2_reset, _, _, _, _, _, _, _, _),
+ PINGROUP(58, uim2_present, _, _, _, _, _, _, _, _),
+ PINGROUP(59, _, _, _, _, _, _, _, _, _),
+ PINGROUP(60, _, _, _, _, _, _, _, _, _),
+ PINGROUP(61, _, _, _, _, _, _, _, _, _),
+ PINGROUP(62, _, _, _, _, _, _, _, _, _),
+ PINGROUP(63, atest_char3, dbg_out, bimc_dte0, _, _, _, _, _, _),
+ PINGROUP(64, _, _, _, _, _, _, _, _, _),
+ PINGROUP(65, bimc_dte0, _, _, _, _, _, _, _, _),
+ PINGROUP(66, sec_mi2s_mclk_b, pri_mi2s, _, qdss_tracedata_b, _, _, _, _, _),
+ PINGROUP(67, cdc_pdm0, atest_char1, ebi_cdc, _, dac_calib17, _, _, _, _),
+ PINGROUP(68, cdc_pdm0, atest_char0, _, _, _, _, _, _, _),
+ PINGROUP(69, cdc_pdm0, pri_mi2s_mclk_b, ebi_cdc, _, _, _, _, _, _),
+ PINGROUP(70, lpass_slimbus, cdc_pdm0, _, _, _, _, _, _, _),
+ PINGROUP(71, lpass_slimbus0, cdc_pdm0, _, _, _, _, _, _, _),
+ PINGROUP(72, lpass_slimbus1, cdc_pdm0, _, _, _, _, _, _, _),
+ PINGROUP(73, cdc_pdm0, _, _, _, _, _, _, _, _),
+ PINGROUP(74, cdc_pdm0, _, _, _, _, _, _, _, _),
+ PINGROUP(75, wcss_bt, atest_char2, _, ebi_ch0, _, _, _, _, _),
+ PINGROUP(76, wcss_wlan2, _, _, _, _, _, _, _, _),
+ PINGROUP(77, wcss_wlan1, _, _, _, _, _, _, _, _),
+ PINGROUP(78, wcss_wlan0, _, _, _, _, _, _, _, _),
+ PINGROUP(79, wcss_wlan, _, _, _, _, _, _, _, _),
+ PINGROUP(80, wcss_wlan, _, _, _, _, _, _, _, _),
+ PINGROUP(81, wcss_fm, ext_lpass, _, _, _, _, _, _, _),
+ PINGROUP(82, wcss_fm, mss_lte, _, _, _, _, _, _, _),
+ PINGROUP(83, wcss_bt, mss_lte, _, _, _, _, _, _, _),
+ PINGROUP(84, wcss_bt, _, _, _, _, _, _, _, _),
+ PINGROUP(85, pbs0, cri_trng0, _, _, _, _, _, _, _),
+ PINGROUP(86, pbs1, cri_trng1, qdss_tracedata_b, _, _, _, _, _, _),
+ PINGROUP(87, pbs2, cri_trng, qdss_tracedata_b, gcc_tlmm, _, _, _, _, _),
+ PINGROUP(88, pri_mi2s, _, _, _, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(89, dmic0_clk, blsp7_spi, _, _, _, _, _, _, _),
+ PINGROUP(90, dmic0_data, blsp7_spi, _, _, _, _, _, _, _),
+ PINGROUP(91, pri_mi2s, _, _, _, qdss_cti_trig_in_a1, _, _, _, _),
+ PINGROUP(92, pri_mi2s_ws, _, _, _, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(93, pri_mi2s, _, _, _, _, _, _, _, _),
+ PINGROUP(94, wsa_io, pri_mi2s, _, _, _, _, _, _, _),
+ PINGROUP(95, wsa_io, pri_mi2s, _, _, _, _, _, _, _),
+ PINGROUP(96, blsp_spi8, _, _, _, _, _, _, _, _),
+ PINGROUP(97, blsp_spi8, _, _, _, _, _, _, _, _),
+ PINGROUP(98, blsp_i2c8, blsp_spi8, gcc_plltest, _, _, _, _, _, _),
+ PINGROUP(99, blsp_i2c8, blsp_spi8, gcc_plltest, _, _, _, _, _, _),
+ PINGROUP(100, _, _, _, _, _, _, _, _, _),
+ PINGROUP(101, _, _, _, _, _, _, _, _, _),
+ PINGROUP(102, _, _, _, _, _, _, _, _, _),
+ PINGROUP(103, _, _, _, _, _, _, _, _, _),
+ PINGROUP(104, _, _, _, _, _, _, _, _, _),
+ PINGROUP(105, _, _, _, _, _, _, _, _, _),
+ PINGROUP(106, _, _, _, _, _, _, _, _, _),
+ PINGROUP(107, _, _, _, _, _, _, _, _, _),
+ PINGROUP(108, _, _, _, _, _, _, _, _, _),
+ PINGROUP(109, _, _, _, _, _, _, _, _, _),
+ PINGROUP(110, _, _, _, _, _, _, _, _, _),
+ PINGROUP(111, _, _, nav_pps_in_a, _, _, _, _, _, _),
+ PINGROUP(112, _, pa_indicator, _, _, _, _, _, _, _),
+ PINGROUP(113, _, nav_pps_in_b, nav_pps, modem_tsync, nav_tsync, _, _, _, _),
+ PINGROUP(114, _, ssbi_wtr1, _, _, _, _, _, _, _),
+ PINGROUP(115, _, gsm1_tx, _, dac_calib18, _, _, _, _, _),
+ PINGROUP(116, _, _, _, _, _, _, _, _, _),
+ PINGROUP(117, gsm0_tx, _, _, _, _, _, _, _, _),
+ PINGROUP(118, _, ebi_cdc, _, _, _, _, _, _, _),
+ PINGROUP(119, _, ebi_cdc, _, _, _, _, _, _, _),
+ PINGROUP(120, _, atest_char, ebi_cdc, _, atest_tsens, _, _, _, _),
+ PINGROUP(121, _, _, _, bimc_dte1, _, _, _, _, _),
+ PINGROUP(122, _, _, _, bimc_dte1, _, _, _, _, _),
+ PINGROUP(123, _, ssbi_wtr1, ebi_cdc, _, _, _, _, _, _),
+ PINGROUP(124, _, _, _, _, _, _, _, _, _),
+ PINGROUP(125, _, _, _, _, _, _, _, _, _),
+ PINGROUP(126, _, _, _, _, _, _, _, _, _),
+ PINGROUP(127, _, _, _, _, _, _, _, _, _),
+ PINGROUP(128, cam_mclk, _, dac_calib20, _, _, _, _, _, _),
+ PINGROUP(129, ddr_bist, _, dac_calib21, _, _, _, _, _, _),
+ PINGROUP(130, ddr_bist, _, dac_calib22, _, _, _, _, _, _),
+ PINGROUP(131, ddr_bist, _, dac_calib23, _, _, _, _, _, _),
+ PINGROUP(132, ddr_bist, _, dac_calib24, _, _, _, _, _, _),
+ PINGROUP(133, _, dac_calib25, _, _, _, _, _, _, _),
+ PINGROUP(134, _, _, _, _, _, _, _, _, _),
+ PINGROUP(135, sec_mi2s, blsp_spi7, blsp_i2c7, _, _, _, _, _, _),
+ PINGROUP(136, sec_mi2s, blsp_spi7, blsp_i2c7, _, _, _, _, _, _),
+ PINGROUP(137, sec_mi2s, blsp_spi7, _, _, _, _, _, _, _),
+ PINGROUP(138, sec_mi2s, blsp_spi7, _, _, _, _, _, _, _),
+ PINGROUP(139, tsens_max, _, _, _, _, _, _, _, _),
+ PINGROUP(140, _, _, _, _, _, _, _, _, _),
+ PINGROUP(141, _, _, _, _, _, _, _, _, _),
+ SDC_QDSD_PINGROUP(qdsd_clk, 0x19c000, 3, 0),
+ SDC_QDSD_PINGROUP(qdsd_cmd, 0x19c000, 8, 5),
+ SDC_QDSD_PINGROUP(qdsd_data0, 0x19c000, 13, 10),
+ SDC_QDSD_PINGROUP(qdsd_data1, 0x19c000, 18, 15),
+ SDC_QDSD_PINGROUP(qdsd_data2, 0x19c000, 23, 20),
+ SDC_QDSD_PINGROUP(qdsd_data3, 0x19c000, 28, 25),
+ SDC_QDSD_PINGROUP(sdc1_clk, 0x10a000, 13, 6),
+ SDC_QDSD_PINGROUP(sdc1_cmd, 0x10a000, 11, 3),
+ SDC_QDSD_PINGROUP(sdc1_data, 0x10a000, 9, 0),
+ SDC_QDSD_PINGROUP(sdc1_rclk, 0x10a000, 15, 0),
+ SDC_QDSD_PINGROUP(sdc2_clk, 0x109000, 14, 6),
+ SDC_QDSD_PINGROUP(sdc2_cmd, 0x109000, 11, 3),
+ SDC_QDSD_PINGROUP(sdc2_data, 0x109000, 9, 0),
+};
+
+static const struct msm_pinctrl_soc_data msm8953_pinctrl = {
+ .pins = msm8953_pins,
+ .npins = ARRAY_SIZE(msm8953_pins),
+ .functions = msm8953_functions,
+ .nfunctions = ARRAY_SIZE(msm8953_functions),
+ .groups = msm8953_groups,
+ .ngroups = ARRAY_SIZE(msm8953_groups),
+ .ngpios = 142,
+};
+
+static int msm8953_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &msm8953_pinctrl);
+}
+
+static const struct of_device_id msm8953_pinctrl_of_match[] = {
+ { .compatible = "qcom,msm8953-pinctrl", },
+ { },
+};
+
+static struct platform_driver msm8953_pinctrl_driver = {
+ .driver = {
+ .name = "msm8953-pinctrl",
+ .of_match_table = msm8953_pinctrl_of_match,
+ },
+ .probe = msm8953_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init msm8953_pinctrl_init(void)
+{
+ return platform_driver_register(&msm8953_pinctrl_driver);
+}
+arch_initcall(msm8953_pinctrl_init);
+
+static void __exit msm8953_pinctrl_exit(void)
+{
+ platform_driver_unregister(&msm8953_pinctrl_driver);
+}
+module_exit(msm8953_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI msm8953 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, msm8953_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c
new file mode 100644
index 000000000000..8daccd530285
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
@@ -0,0 +1,1495 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = 0x1000 * id, \
+ .io_reg = 0x1000 * id + 0x4, \
+ .intr_cfg_reg = 0x1000 * id + 0x8, \
+ .intr_status_reg = 0x1000 * id + 0xc, \
+ .intr_target_reg = 0x1000 * id + 0x8, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+#define UFS_RESET(pg_name, offset) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = offset, \
+ .io_reg = offset + 0x4, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+static const struct pinctrl_pin_desc sc7280_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "GPIO_119"),
+ PINCTRL_PIN(120, "GPIO_120"),
+ PINCTRL_PIN(121, "GPIO_121"),
+ PINCTRL_PIN(122, "GPIO_122"),
+ PINCTRL_PIN(123, "GPIO_123"),
+ PINCTRL_PIN(124, "GPIO_124"),
+ PINCTRL_PIN(125, "GPIO_125"),
+ PINCTRL_PIN(126, "GPIO_126"),
+ PINCTRL_PIN(127, "GPIO_127"),
+ PINCTRL_PIN(128, "GPIO_128"),
+ PINCTRL_PIN(129, "GPIO_129"),
+ PINCTRL_PIN(130, "GPIO_130"),
+ PINCTRL_PIN(131, "GPIO_131"),
+ PINCTRL_PIN(132, "GPIO_132"),
+ PINCTRL_PIN(133, "GPIO_133"),
+ PINCTRL_PIN(134, "GPIO_134"),
+ PINCTRL_PIN(135, "GPIO_135"),
+ PINCTRL_PIN(136, "GPIO_136"),
+ PINCTRL_PIN(137, "GPIO_137"),
+ PINCTRL_PIN(138, "GPIO_138"),
+ PINCTRL_PIN(139, "GPIO_139"),
+ PINCTRL_PIN(140, "GPIO_140"),
+ PINCTRL_PIN(141, "GPIO_141"),
+ PINCTRL_PIN(142, "GPIO_142"),
+ PINCTRL_PIN(143, "GPIO_143"),
+ PINCTRL_PIN(144, "GPIO_144"),
+ PINCTRL_PIN(145, "GPIO_145"),
+ PINCTRL_PIN(146, "GPIO_146"),
+ PINCTRL_PIN(147, "GPIO_147"),
+ PINCTRL_PIN(148, "GPIO_148"),
+ PINCTRL_PIN(149, "GPIO_149"),
+ PINCTRL_PIN(150, "GPIO_150"),
+ PINCTRL_PIN(151, "GPIO_151"),
+ PINCTRL_PIN(152, "GPIO_152"),
+ PINCTRL_PIN(153, "GPIO_153"),
+ PINCTRL_PIN(154, "GPIO_154"),
+ PINCTRL_PIN(155, "GPIO_155"),
+ PINCTRL_PIN(156, "GPIO_156"),
+ PINCTRL_PIN(157, "GPIO_157"),
+ PINCTRL_PIN(158, "GPIO_158"),
+ PINCTRL_PIN(159, "GPIO_159"),
+ PINCTRL_PIN(160, "GPIO_160"),
+ PINCTRL_PIN(161, "GPIO_161"),
+ PINCTRL_PIN(162, "GPIO_162"),
+ PINCTRL_PIN(163, "GPIO_163"),
+ PINCTRL_PIN(164, "GPIO_164"),
+ PINCTRL_PIN(165, "GPIO_165"),
+ PINCTRL_PIN(166, "GPIO_166"),
+ PINCTRL_PIN(167, "GPIO_167"),
+ PINCTRL_PIN(168, "GPIO_168"),
+ PINCTRL_PIN(169, "GPIO_169"),
+ PINCTRL_PIN(170, "GPIO_170"),
+ PINCTRL_PIN(171, "GPIO_171"),
+ PINCTRL_PIN(172, "GPIO_172"),
+ PINCTRL_PIN(173, "GPIO_173"),
+ PINCTRL_PIN(174, "GPIO_174"),
+ PINCTRL_PIN(175, "UFS_RESET"),
+ PINCTRL_PIN(176, "SDC1_RCLK"),
+ PINCTRL_PIN(177, "SDC1_CLK"),
+ PINCTRL_PIN(178, "SDC1_CMD"),
+ PINCTRL_PIN(179, "SDC1_DATA"),
+ PINCTRL_PIN(180, "SDC2_CLK"),
+ PINCTRL_PIN(181, "SDC2_CMD"),
+ PINCTRL_PIN(182, "SDC2_DATA"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+DECLARE_MSM_GPIO_PINS(117);
+DECLARE_MSM_GPIO_PINS(118);
+DECLARE_MSM_GPIO_PINS(119);
+DECLARE_MSM_GPIO_PINS(120);
+DECLARE_MSM_GPIO_PINS(121);
+DECLARE_MSM_GPIO_PINS(122);
+DECLARE_MSM_GPIO_PINS(123);
+DECLARE_MSM_GPIO_PINS(124);
+DECLARE_MSM_GPIO_PINS(125);
+DECLARE_MSM_GPIO_PINS(126);
+DECLARE_MSM_GPIO_PINS(127);
+DECLARE_MSM_GPIO_PINS(128);
+DECLARE_MSM_GPIO_PINS(129);
+DECLARE_MSM_GPIO_PINS(130);
+DECLARE_MSM_GPIO_PINS(131);
+DECLARE_MSM_GPIO_PINS(132);
+DECLARE_MSM_GPIO_PINS(133);
+DECLARE_MSM_GPIO_PINS(134);
+DECLARE_MSM_GPIO_PINS(135);
+DECLARE_MSM_GPIO_PINS(136);
+DECLARE_MSM_GPIO_PINS(137);
+DECLARE_MSM_GPIO_PINS(138);
+DECLARE_MSM_GPIO_PINS(139);
+DECLARE_MSM_GPIO_PINS(140);
+DECLARE_MSM_GPIO_PINS(141);
+DECLARE_MSM_GPIO_PINS(142);
+DECLARE_MSM_GPIO_PINS(143);
+DECLARE_MSM_GPIO_PINS(144);
+DECLARE_MSM_GPIO_PINS(145);
+DECLARE_MSM_GPIO_PINS(146);
+DECLARE_MSM_GPIO_PINS(147);
+DECLARE_MSM_GPIO_PINS(148);
+DECLARE_MSM_GPIO_PINS(149);
+DECLARE_MSM_GPIO_PINS(150);
+DECLARE_MSM_GPIO_PINS(151);
+DECLARE_MSM_GPIO_PINS(152);
+DECLARE_MSM_GPIO_PINS(153);
+DECLARE_MSM_GPIO_PINS(154);
+DECLARE_MSM_GPIO_PINS(155);
+DECLARE_MSM_GPIO_PINS(156);
+DECLARE_MSM_GPIO_PINS(157);
+DECLARE_MSM_GPIO_PINS(158);
+DECLARE_MSM_GPIO_PINS(159);
+DECLARE_MSM_GPIO_PINS(160);
+DECLARE_MSM_GPIO_PINS(161);
+DECLARE_MSM_GPIO_PINS(162);
+DECLARE_MSM_GPIO_PINS(163);
+DECLARE_MSM_GPIO_PINS(164);
+DECLARE_MSM_GPIO_PINS(165);
+DECLARE_MSM_GPIO_PINS(166);
+DECLARE_MSM_GPIO_PINS(167);
+DECLARE_MSM_GPIO_PINS(168);
+DECLARE_MSM_GPIO_PINS(169);
+DECLARE_MSM_GPIO_PINS(170);
+DECLARE_MSM_GPIO_PINS(171);
+DECLARE_MSM_GPIO_PINS(172);
+DECLARE_MSM_GPIO_PINS(173);
+DECLARE_MSM_GPIO_PINS(174);
+
+static const unsigned int ufs_reset_pins[] = { 175 };
+static const unsigned int sdc1_rclk_pins[] = { 176 };
+static const unsigned int sdc1_clk_pins[] = { 177 };
+static const unsigned int sdc1_cmd_pins[] = { 178 };
+static const unsigned int sdc1_data_pins[] = { 179 };
+static const unsigned int sdc2_clk_pins[] = { 180 };
+static const unsigned int sdc2_cmd_pins[] = { 181 };
+static const unsigned int sdc2_data_pins[] = { 182 };
+
+enum sc7280_functions {
+ msm_mux_atest_char,
+ msm_mux_atest_char0,
+ msm_mux_atest_char1,
+ msm_mux_atest_char2,
+ msm_mux_atest_char3,
+ msm_mux_atest_usb0,
+ msm_mux_atest_usb00,
+ msm_mux_atest_usb01,
+ msm_mux_atest_usb02,
+ msm_mux_atest_usb03,
+ msm_mux_atest_usb1,
+ msm_mux_atest_usb10,
+ msm_mux_atest_usb11,
+ msm_mux_atest_usb12,
+ msm_mux_atest_usb13,
+ msm_mux_audio_ref,
+ msm_mux_cam_mclk,
+ msm_mux_cci_async,
+ msm_mux_cci_i2c,
+ msm_mux_cci_timer0,
+ msm_mux_cci_timer1,
+ msm_mux_cci_timer2,
+ msm_mux_cci_timer3,
+ msm_mux_cci_timer4,
+ msm_mux_cmu_rng0,
+ msm_mux_cmu_rng1,
+ msm_mux_cmu_rng2,
+ msm_mux_cmu_rng3,
+ msm_mux_coex_uart1,
+ msm_mux_cri_trng,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_dbg_out,
+ msm_mux_ddr_bist,
+ msm_mux_ddr_pxi0,
+ msm_mux_ddr_pxi1,
+ msm_mux_dp_hot,
+ msm_mux_dp_lcd,
+ msm_mux_edp_hot,
+ msm_mux_edp_lcd,
+ msm_mux_gcc_gp1,
+ msm_mux_gcc_gp2,
+ msm_mux_gcc_gp3,
+ msm_mux_gpio,
+ msm_mux_host2wlan_sol,
+ msm_mux_ibi_i3c,
+ msm_mux_jitter_bist,
+ msm_mux_lpass_slimbus,
+ msm_mux_mdp_vsync,
+ msm_mux_mdp_vsync0,
+ msm_mux_mdp_vsync1,
+ msm_mux_mdp_vsync2,
+ msm_mux_mdp_vsync3,
+ msm_mux_mdp_vsync4,
+ msm_mux_mdp_vsync5,
+ msm_mux_mi2s0_data0,
+ msm_mux_mi2s0_data1,
+ msm_mux_mi2s0_sck,
+ msm_mux_mi2s0_ws,
+ msm_mux_mi2s1_data0,
+ msm_mux_mi2s1_data1,
+ msm_mux_mi2s1_sck,
+ msm_mux_mi2s1_ws,
+ msm_mux_mi2s2_data0,
+ msm_mux_mi2s2_data1,
+ msm_mux_mi2s2_sck,
+ msm_mux_mi2s2_ws,
+ msm_mux_mss_grfc0,
+ msm_mux_mss_grfc1,
+ msm_mux_mss_grfc10,
+ msm_mux_mss_grfc11,
+ msm_mux_mss_grfc12,
+ msm_mux_mss_grfc2,
+ msm_mux_mss_grfc3,
+ msm_mux_mss_grfc4,
+ msm_mux_mss_grfc5,
+ msm_mux_mss_grfc6,
+ msm_mux_mss_grfc7,
+ msm_mux_mss_grfc8,
+ msm_mux_mss_grfc9,
+ msm_mux_nav_gpio0,
+ msm_mux_nav_gpio1,
+ msm_mux_nav_gpio2,
+ msm_mux_pa_indicator,
+ msm_mux_pcie0_clkreqn,
+ msm_mux_pcie1_clkreqn,
+ msm_mux_phase_flag,
+ msm_mux_pll_bist,
+ msm_mux_pll_bypassnl,
+ msm_mux_pll_clk,
+ msm_mux_pll_reset,
+ msm_mux_pri_mi2s,
+ msm_mux_prng_rosc,
+ msm_mux_qdss,
+ msm_mux_qdss_cti,
+ msm_mux_qlink0_enable,
+ msm_mux_qlink0_request,
+ msm_mux_qlink0_wmss,
+ msm_mux_qlink1_enable,
+ msm_mux_qlink1_request,
+ msm_mux_qlink1_wmss,
+ msm_mux_qspi_clk,
+ msm_mux_qspi_cs,
+ msm_mux_qspi_data,
+ msm_mux_qup00,
+ msm_mux_qup01,
+ msm_mux_qup02,
+ msm_mux_qup03,
+ msm_mux_qup04,
+ msm_mux_qup05,
+ msm_mux_qup06,
+ msm_mux_qup07,
+ msm_mux_qup10,
+ msm_mux_qup11,
+ msm_mux_qup12,
+ msm_mux_qup13,
+ msm_mux_qup14,
+ msm_mux_qup15,
+ msm_mux_qup16,
+ msm_mux_qup17,
+ msm_mux_sd_write,
+ msm_mux_sdc40,
+ msm_mux_sdc41,
+ msm_mux_sdc42,
+ msm_mux_sdc43,
+ msm_mux_sdc4_clk,
+ msm_mux_sdc4_cmd,
+ msm_mux_sec_mi2s,
+ msm_mux_tb_trig,
+ msm_mux_tgu_ch0,
+ msm_mux_tgu_ch1,
+ msm_mux_tsense_pwm1,
+ msm_mux_tsense_pwm2,
+ msm_mux_uim0_clk,
+ msm_mux_uim0_data,
+ msm_mux_uim0_present,
+ msm_mux_uim0_reset,
+ msm_mux_uim1_clk,
+ msm_mux_uim1_data,
+ msm_mux_uim1_present,
+ msm_mux_uim1_reset,
+ msm_mux_usb2phy_ac,
+ msm_mux_usb_phy,
+ msm_mux_vfr_0,
+ msm_mux_vfr_1,
+ msm_mux_vsense_trigger,
+ msm_mux__,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
+ "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
+ "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
+ "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
+ "gpio171", "gpio172", "gpio173", "gpio174",
+};
+static const char * const atest_char_groups[] = {
+ "gpio81",
+};
+static const char * const atest_char0_groups[] = {
+ "gpio77",
+};
+static const char * const atest_char1_groups[] = {
+ "gpio78",
+};
+static const char * const atest_char2_groups[] = {
+ "gpio79",
+};
+static const char * const atest_char3_groups[] = {
+ "gpio80",
+};
+static const char * const atest_usb0_groups[] = {
+ "gpio107",
+};
+static const char * const atest_usb00_groups[] = {
+ "gpio106",
+};
+static const char * const atest_usb01_groups[] = {
+ "gpio105",
+};
+static const char * const atest_usb02_groups[] = {
+ "gpio104",
+};
+static const char * const atest_usb03_groups[] = {
+ "gpio103",
+};
+static const char * const atest_usb1_groups[] = {
+ "gpio81",
+};
+static const char * const atest_usb10_groups[] = {
+ "gpio80",
+};
+static const char * const atest_usb11_groups[] = {
+ "gpio79",
+};
+static const char * const atest_usb12_groups[] = {
+ "gpio78",
+};
+static const char * const atest_usb13_groups[] = {
+ "gpio77",
+};
+static const char * const audio_ref_groups[] = {
+ "gpio105",
+};
+static const char * const cam_mclk_groups[] = {
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio93",
+};
+static const char * const cci_async_groups[] = {
+ "gpio78", "gpio79", "gpio93",
+};
+static const char * const cci_i2c_groups[] = {
+ "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75",
+ "gpio76",
+};
+static const char * const cci_timer0_groups[] = {
+ "gpio20",
+};
+static const char * const cci_timer1_groups[] = {
+ "gpio21",
+};
+static const char * const cci_timer2_groups[] = {
+ "gpio77",
+};
+static const char * const cci_timer3_groups[] = {
+ "gpio78",
+};
+static const char * const cci_timer4_groups[] = {
+ "gpio79",
+};
+static const char * const cmu_rng0_groups[] = {
+ "gpio120",
+};
+static const char * const cmu_rng1_groups[] = {
+ "gpio119",
+};
+static const char * const cmu_rng2_groups[] = {
+ "gpio118",
+};
+static const char * const cmu_rng3_groups[] = {
+ "gpio117",
+};
+static const char * const coex_uart1_groups[] = {
+ "gpio127", "gpio128",
+};
+static const char * const cri_trng_groups[] = {
+ "gpio124",
+};
+static const char * const cri_trng0_groups[] = {
+ "gpio121",
+};
+static const char * const cri_trng1_groups[] = {
+ "gpio122",
+};
+static const char * const dbg_out_groups[] = {
+ "gpio38",
+};
+static const char * const ddr_bist_groups[] = {
+ "gpio56", "gpio57", "gpio58", "gpio59",
+};
+static const char * const ddr_pxi0_groups[] = {
+ "gpio14", "gpio15",
+};
+static const char * const ddr_pxi1_groups[] = {
+ "gpio12", "gpio13",
+};
+static const char * const dp_hot_groups[] = {
+ "gpio47",
+};
+static const char * const dp_lcd_groups[] = {
+ "gpio81",
+};
+static const char * const edp_hot_groups[] = {
+ "gpio60",
+};
+static const char * const edp_lcd_groups[] = {
+ "gpio46",
+};
+static const char * const gcc_gp1_groups[] = {
+ "gpio76", "gpio105",
+};
+static const char * const gcc_gp2_groups[] = {
+ "gpio77", "gpio106",
+};
+static const char * const gcc_gp3_groups[] = {
+ "gpio78", "gpio107",
+};
+static const char * const host2wlan_sol_groups[] = {
+ "gpio26",
+};
+static const char * const ibi_i3c_groups[] = {
+ "gpio0", "gpio1", "gpio4", "gpio5", "gpio36", "gpio37",
+};
+static const char * const jitter_bist_groups[] = {
+ "gpio79",
+};
+static const char * const lpass_slimbus_groups[] = {
+ "gpio94", "gpio95",
+};
+static const char * const mdp_vsync_groups[] = {
+ "gpio14", "gpio16", "gpio79", "gpio80", "gpio81",
+};
+static const char * const mdp_vsync0_groups[] = {
+ "gpio80",
+};
+static const char * const mdp_vsync1_groups[] = {
+ "gpio80",
+};
+static const char * const mdp_vsync2_groups[] = {
+ "gpio81",
+};
+static const char * const mdp_vsync3_groups[] = {
+ "gpio81",
+};
+static const char * const mdp_vsync4_groups[] = {
+ "gpio80",
+};
+static const char * const mdp_vsync5_groups[] = {
+ "gpio81",
+};
+static const char * const mi2s0_data0_groups[] = {
+ "gpio98",
+};
+static const char * const mi2s0_data1_groups[] = {
+ "gpio99",
+};
+static const char * const mi2s0_sck_groups[] = {
+ "gpio97",
+};
+static const char * const mi2s0_ws_groups[] = {
+ "gpio100",
+};
+static const char * const mi2s1_data0_groups[] = {
+ "gpio107",
+};
+static const char * const mi2s1_data1_groups[] = {
+ "gpio105",
+};
+static const char * const mi2s1_sck_groups[] = {
+ "gpio106",
+};
+static const char * const mi2s1_ws_groups[] = {
+ "gpio108",
+};
+static const char * const mi2s2_data0_groups[] = {
+ "gpio102",
+};
+static const char * const mi2s2_data1_groups[] = {
+ "gpio104",
+};
+static const char * const mi2s2_sck_groups[] = {
+ "gpio101",
+};
+static const char * const mi2s2_ws_groups[] = {
+ "gpio103",
+};
+static const char * const mss_grfc0_groups[] = {
+ "gpio117", "gpio132",
+};
+static const char * const mss_grfc1_groups[] = {
+ "gpio118",
+};
+static const char * const mss_grfc10_groups[] = {
+ "gpio127",
+};
+static const char * const mss_grfc11_groups[] = {
+ "gpio128",
+};
+static const char * const mss_grfc12_groups[] = {
+ "gpio131",
+};
+static const char * const mss_grfc2_groups[] = {
+ "gpio119",
+};
+static const char * const mss_grfc3_groups[] = {
+ "gpio120",
+};
+static const char * const mss_grfc4_groups[] = {
+ "gpio121",
+};
+static const char * const mss_grfc5_groups[] = {
+ "gpio122",
+};
+static const char * const mss_grfc6_groups[] = {
+ "gpio123",
+};
+static const char * const mss_grfc7_groups[] = {
+ "gpio124",
+};
+static const char * const mss_grfc8_groups[] = {
+ "gpio125",
+};
+static const char * const mss_grfc9_groups[] = {
+ "gpio126",
+};
+static const char * const nav_gpio0_groups[] = {
+ "gpio129",
+};
+static const char * const nav_gpio1_groups[] = {
+ "gpio130",
+};
+static const char * const nav_gpio2_groups[] = {
+ "gpio131",
+};
+static const char * const pa_indicator_groups[] = {
+ "gpio131",
+};
+static const char * const pcie0_clkreqn_groups[] = {
+ "gpio88",
+};
+static const char * const pcie1_clkreqn_groups[] = {
+ "gpio79",
+};
+static const char * const phase_flag_groups[] = {
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
+ "gpio17", "gpio18", "gpio19", "gpio56", "gpio57",
+ "gpio58", "gpio59", "gpio60", "gpio61", "gpio62",
+ "gpio63", "gpio117", "gpio118", "gpio119", "gpio120",
+ "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
+ "gpio126", "gpio127", "gpio128", "gpio129", "gpio130",
+ "gpio131", "gpio132",
+};
+static const char * const pll_bist_groups[] = {
+ "gpio80",
+};
+static const char * const pll_bypassnl_groups[] = {
+ "gpio66",
+};
+static const char * const pll_clk_groups[] = {
+ "gpio140",
+};
+static const char * const pll_reset_groups[] = {
+ "gpio67",
+};
+static const char * const pri_mi2s_groups[] = {
+ "gpio96",
+};
+static const char * const prng_rosc_groups[] = {
+ "gpio123",
+};
+static const char * const qdss_groups[] = {
+ "gpio2", "gpio3", "gpio8", "gpio9", "gpio10",
+ "gpio11", "gpio12", "gpio13", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
+ "gpio27", "gpio28", "gpio29", "gpio58", "gpio59",
+ "gpio101", "gpio102", "gpio103", "gpio104", "gpio105",
+ "gpio106", "gpio107", "gpio108", "gpio150", "gpio151",
+ "gpio152", "gpio153", "gpio171", "gpio172", "gpio173",
+ "gpio174",
+};
+static const char * const qdss_cti_groups[] = {
+ "gpio15", "gpio16", "gpio18", "gpio19", "gpio156", "gpio157",
+ "gpio165", "gpio166",
+};
+static const char * const qlink0_enable_groups[] = {
+ "gpio134",
+};
+static const char * const qlink0_request_groups[] = {
+ "gpio133",
+};
+static const char * const qlink0_wmss_groups[] = {
+ "gpio135",
+};
+static const char * const qlink1_enable_groups[] = {
+ "gpio137",
+};
+static const char * const qlink1_request_groups[] = {
+ "gpio136",
+};
+static const char * const qlink1_wmss_groups[] = {
+ "gpio138",
+};
+static const char * const qspi_clk_groups[] = {
+ "gpio14",
+};
+static const char * const qspi_cs_groups[] = {
+ "gpio15", "gpio19",
+};
+static const char * const qspi_data_groups[] = {
+ "gpio12", "gpio13", "gpio16", "gpio17",
+};
+static const char * const qup00_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+static const char * const qup01_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+static const char * const qup02_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+static const char * const qup03_groups[] = {
+ "gpio12", "gpio13", "gpio14", "gpio15",
+};
+static const char * const qup04_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19",
+};
+static const char * const qup05_groups[] = {
+ "gpio20", "gpio21", "gpio22", "gpio23",
+};
+static const char * const qup06_groups[] = {
+ "gpio24", "gpio25", "gpio26", "gpio27",
+};
+static const char * const qup07_groups[] = {
+ "gpio2", "gpio3", "gpio6", "gpio28", "gpio29", "gpio30", "gpio31",
+};
+static const char * const qup10_groups[] = {
+ "gpio32", "gpio33", "gpio34", "gpio35",
+};
+static const char * const qup11_groups[] = {
+ "gpio36", "gpio37", "gpio38", "gpio39",
+};
+static const char * const qup12_groups[] = {
+ "gpio40", "gpio41", "gpio42", "gpio43",
+};
+static const char * const qup13_groups[] = {
+ "gpio44", "gpio45", "gpio46", "gpio47",
+};
+static const char * const qup14_groups[] = {
+ "gpio38", "gpio48", "gpio49", "gpio50", "gpio51", "gpio54", "gpio55",
+};
+static const char * const qup15_groups[] = {
+ "gpio52", "gpio53", "gpio54", "gpio55",
+};
+static const char * const qup16_groups[] = {
+ "gpio50", "gpio56", "gpio57", "gpio58", "gpio59", "gpio62", "gpio63",
+};
+static const char * const qup17_groups[] = {
+ "gpio60", "gpio61", "gpio62", "gpio63",
+};
+static const char * const sd_write_groups[] = {
+ "gpio61",
+};
+static const char * const sdc40_groups[] = {
+ "gpio12",
+};
+static const char * const sdc41_groups[] = {
+ "gpio13",
+};
+static const char * const sdc42_groups[] = {
+ "gpio16",
+};
+static const char * const sdc43_groups[] = {
+ "gpio17",
+};
+static const char * const sdc4_clk_groups[] = {
+ "gpio14",
+};
+static const char * const sdc4_cmd_groups[] = {
+ "gpio19",
+};
+static const char * const sec_mi2s_groups[] = {
+ "gpio105",
+};
+static const char * const tb_trig_groups[] = {
+ "gpio12", "gpio13", "gpio15",
+};
+static const char * const tgu_ch0_groups[] = {
+ "gpio65",
+};
+static const char * const tgu_ch1_groups[] = {
+ "gpio66",
+};
+static const char * const tsense_pwm1_groups[] = {
+ "gpio61",
+};
+static const char * const tsense_pwm2_groups[] = {
+ "gpio61",
+};
+static const char * const uim0_clk_groups[] = {
+ "gpio114",
+};
+static const char * const uim0_data_groups[] = {
+ "gpio113",
+};
+static const char * const uim0_present_groups[] = {
+ "gpio116",
+};
+static const char * const uim0_reset_groups[] = {
+ "gpio115",
+};
+static const char * const uim1_clk_groups[] = {
+ "gpio110",
+};
+static const char * const uim1_data_groups[] = {
+ "gpio109",
+};
+static const char * const uim1_present_groups[] = {
+ "gpio112",
+};
+static const char * const uim1_reset_groups[] = {
+ "gpio111",
+};
+static const char * const usb2phy_ac_groups[] = {
+ "gpio84", "gpio85",
+};
+static const char * const usb_phy_groups[] = {
+ "gpio140",
+};
+static const char * const vfr_0_groups[] = {
+ "gpio80",
+};
+static const char * const vfr_1_groups[] = {
+ "gpio103",
+};
+static const char * const vsense_trigger_groups[] = {
+ "gpio100",
+};
+
+static const struct msm_function sc7280_functions[] = {
+ FUNCTION(atest_char),
+ FUNCTION(atest_char0),
+ FUNCTION(atest_char1),
+ FUNCTION(atest_char2),
+ FUNCTION(atest_char3),
+ FUNCTION(atest_usb0),
+ FUNCTION(atest_usb00),
+ FUNCTION(atest_usb01),
+ FUNCTION(atest_usb02),
+ FUNCTION(atest_usb03),
+ FUNCTION(atest_usb1),
+ FUNCTION(atest_usb10),
+ FUNCTION(atest_usb11),
+ FUNCTION(atest_usb12),
+ FUNCTION(atest_usb13),
+ FUNCTION(audio_ref),
+ FUNCTION(cam_mclk),
+ FUNCTION(cci_async),
+ FUNCTION(cci_i2c),
+ FUNCTION(cci_timer0),
+ FUNCTION(cci_timer1),
+ FUNCTION(cci_timer2),
+ FUNCTION(cci_timer3),
+ FUNCTION(cci_timer4),
+ FUNCTION(cmu_rng0),
+ FUNCTION(cmu_rng1),
+ FUNCTION(cmu_rng2),
+ FUNCTION(cmu_rng3),
+ FUNCTION(coex_uart1),
+ FUNCTION(cri_trng),
+ FUNCTION(cri_trng0),
+ FUNCTION(cri_trng1),
+ FUNCTION(dbg_out),
+ FUNCTION(ddr_bist),
+ FUNCTION(ddr_pxi0),
+ FUNCTION(ddr_pxi1),
+ FUNCTION(dp_hot),
+ FUNCTION(dp_lcd),
+ FUNCTION(edp_hot),
+ FUNCTION(edp_lcd),
+ FUNCTION(gcc_gp1),
+ FUNCTION(gcc_gp2),
+ FUNCTION(gcc_gp3),
+ FUNCTION(gpio),
+ FUNCTION(host2wlan_sol),
+ FUNCTION(ibi_i3c),
+ FUNCTION(jitter_bist),
+ FUNCTION(lpass_slimbus),
+ FUNCTION(mdp_vsync),
+ FUNCTION(mdp_vsync0),
+ FUNCTION(mdp_vsync1),
+ FUNCTION(mdp_vsync2),
+ FUNCTION(mdp_vsync3),
+ FUNCTION(mdp_vsync4),
+ FUNCTION(mdp_vsync5),
+ FUNCTION(mi2s0_data0),
+ FUNCTION(mi2s0_data1),
+ FUNCTION(mi2s0_sck),
+ FUNCTION(mi2s0_ws),
+ FUNCTION(mi2s1_data0),
+ FUNCTION(mi2s1_data1),
+ FUNCTION(mi2s1_sck),
+ FUNCTION(mi2s1_ws),
+ FUNCTION(mi2s2_data0),
+ FUNCTION(mi2s2_data1),
+ FUNCTION(mi2s2_sck),
+ FUNCTION(mi2s2_ws),
+ FUNCTION(mss_grfc0),
+ FUNCTION(mss_grfc1),
+ FUNCTION(mss_grfc10),
+ FUNCTION(mss_grfc11),
+ FUNCTION(mss_grfc12),
+ FUNCTION(mss_grfc2),
+ FUNCTION(mss_grfc3),
+ FUNCTION(mss_grfc4),
+ FUNCTION(mss_grfc5),
+ FUNCTION(mss_grfc6),
+ FUNCTION(mss_grfc7),
+ FUNCTION(mss_grfc8),
+ FUNCTION(mss_grfc9),
+ FUNCTION(nav_gpio0),
+ FUNCTION(nav_gpio1),
+ FUNCTION(nav_gpio2),
+ FUNCTION(pa_indicator),
+ FUNCTION(pcie0_clkreqn),
+ FUNCTION(pcie1_clkreqn),
+ FUNCTION(phase_flag),
+ FUNCTION(pll_bist),
+ FUNCTION(pll_bypassnl),
+ FUNCTION(pll_clk),
+ FUNCTION(pll_reset),
+ FUNCTION(pri_mi2s),
+ FUNCTION(prng_rosc),
+ FUNCTION(qdss),
+ FUNCTION(qdss_cti),
+ FUNCTION(qlink0_enable),
+ FUNCTION(qlink0_request),
+ FUNCTION(qlink0_wmss),
+ FUNCTION(qlink1_enable),
+ FUNCTION(qlink1_request),
+ FUNCTION(qlink1_wmss),
+ FUNCTION(qspi_clk),
+ FUNCTION(qspi_cs),
+ FUNCTION(qspi_data),
+ FUNCTION(qup00),
+ FUNCTION(qup01),
+ FUNCTION(qup02),
+ FUNCTION(qup03),
+ FUNCTION(qup04),
+ FUNCTION(qup05),
+ FUNCTION(qup06),
+ FUNCTION(qup07),
+ FUNCTION(qup10),
+ FUNCTION(qup11),
+ FUNCTION(qup12),
+ FUNCTION(qup13),
+ FUNCTION(qup14),
+ FUNCTION(qup15),
+ FUNCTION(qup16),
+ FUNCTION(qup17),
+ FUNCTION(sdc40),
+ FUNCTION(sdc41),
+ FUNCTION(sdc42),
+ FUNCTION(sdc43),
+ FUNCTION(sdc4_clk),
+ FUNCTION(sdc4_cmd),
+ FUNCTION(sd_write),
+ FUNCTION(sec_mi2s),
+ FUNCTION(tb_trig),
+ FUNCTION(tgu_ch0),
+ FUNCTION(tgu_ch1),
+ FUNCTION(tsense_pwm1),
+ FUNCTION(tsense_pwm2),
+ FUNCTION(uim0_clk),
+ FUNCTION(uim0_data),
+ FUNCTION(uim0_present),
+ FUNCTION(uim0_reset),
+ FUNCTION(uim1_clk),
+ FUNCTION(uim1_data),
+ FUNCTION(uim1_present),
+ FUNCTION(uim1_reset),
+ FUNCTION(usb2phy_ac),
+ FUNCTION(usb_phy),
+ FUNCTION(vfr_0),
+ FUNCTION(vfr_1),
+ FUNCTION(vsense_trigger),
+};
+
+/* Every pin is maintained as a single group, and missing or non-existing pin
+ * would be maintained as dummy group to synchronize pin group index with
+ * pin descriptor registered with pinctrl core.
+ * Clients would not be able to request these dummy pin groups.
+ */
+static const struct msm_pingroup sc7280_groups[] = {
+ [0] = PINGROUP(0, qup00, ibi_i3c, _, _, _, _, _, _, _),
+ [1] = PINGROUP(1, qup00, ibi_i3c, _, _, _, _, _, _, _),
+ [2] = PINGROUP(2, qup00, qup07, _, qdss, _, _, _, _, _),
+ [3] = PINGROUP(3, qup00, qup07, _, qdss, _, _, _, _, _),
+ [4] = PINGROUP(4, qup01, ibi_i3c, _, _, _, _, _, _, _),
+ [5] = PINGROUP(5, qup01, ibi_i3c, _, _, _, _, _, _, _),
+ [6] = PINGROUP(6, qup01, qup07, _, _, _, _, _, _, _),
+ [7] = PINGROUP(7, qup01, _, _, _, _, _, _, _, _),
+ [8] = PINGROUP(8, qup02, _, qdss, _, _, _, _, _, _),
+ [9] = PINGROUP(9, qup02, _, qdss, _, _, _, _, _, _),
+ [10] = PINGROUP(10, qup02, _, qdss, _, _, _, _, _, _),
+ [11] = PINGROUP(11, qup02, _, qdss, _, _, _, _, _, _),
+ [12] = PINGROUP(12, qup03, qspi_data, sdc40, tb_trig, phase_flag, qdss, ddr_pxi1, _, _),
+ [13] = PINGROUP(13, qup03, qspi_data, sdc41, tb_trig, phase_flag, qdss, ddr_pxi1, _, _),
+ [14] = PINGROUP(14, qup03, qspi_clk, sdc4_clk, mdp_vsync, phase_flag, ddr_pxi0, _, _, _),
+ [15] = PINGROUP(15, qup03, qspi_cs, tb_trig, phase_flag, qdss_cti, ddr_pxi0, _, _, _),
+ [16] = PINGROUP(16, qup04, qspi_data, sdc42, mdp_vsync, phase_flag, qdss_cti, _, _, _),
+ [17] = PINGROUP(17, qup04, qspi_data, sdc43, _, phase_flag, _, _, _, _),
+ [18] = PINGROUP(18, qup04, _, phase_flag, qdss_cti, _, _, _, _, _),
+ [19] = PINGROUP(19, qup04, qspi_cs, sdc4_cmd, _, phase_flag, qdss_cti, _, _, _),
+ [20] = PINGROUP(20, qup05, cci_timer0, _, qdss, _, _, _, _, _),
+ [21] = PINGROUP(21, qup05, cci_timer1, _, qdss, _, _, _, _, _),
+ [22] = PINGROUP(22, qup05, _, qdss, _, _, _, _, _, _),
+ [23] = PINGROUP(23, qup05, _, qdss, _, _, _, _, _, _),
+ [24] = PINGROUP(24, qup06, _, qdss, _, _, _, _, _, _),
+ [25] = PINGROUP(25, qup06, _, qdss, _, _, _, _, _, _),
+ [26] = PINGROUP(26, qup06, host2wlan_sol, _, qdss, _, _, _, _, _),
+ [27] = PINGROUP(27, qup06, _, qdss, _, _, _, _, _, _),
+ [28] = PINGROUP(28, qup07, _, qdss, _, _, _, _, _, _),
+ [29] = PINGROUP(29, qup07, qdss, _, _, _, _, _, _, _),
+ [30] = PINGROUP(30, qup07, _, _, _, _, _, _, _, _),
+ [31] = PINGROUP(31, qup07, _, _, _, _, _, _, _, _),
+ [32] = PINGROUP(32, qup10, _, _, _, _, _, _, _, _),
+ [33] = PINGROUP(33, qup10, _, _, _, _, _, _, _, _),
+ [34] = PINGROUP(34, qup10, _, _, _, _, _, _, _, _),
+ [35] = PINGROUP(35, qup10, _, _, _, _, _, _, _, _),
+ [36] = PINGROUP(36, qup11, ibi_i3c, _, _, _, _, _, _, _),
+ [37] = PINGROUP(37, qup11, ibi_i3c, _, _, _, _, _, _, _),
+ [38] = PINGROUP(38, qup11, qup14, dbg_out, _, _, _, _, _, _),
+ [39] = PINGROUP(39, qup11, _, _, _, _, _, _, _, _),
+ [40] = PINGROUP(40, qup12, _, _, _, _, _, _, _, _),
+ [41] = PINGROUP(41, qup12, _, _, _, _, _, _, _, _),
+ [42] = PINGROUP(42, qup12, _, _, _, _, _, _, _, _),
+ [43] = PINGROUP(43, qup12, _, _, _, _, _, _, _, _),
+ [44] = PINGROUP(44, qup13, _, _, _, _, _, _, _, _),
+ [45] = PINGROUP(45, qup13, _, _, _, _, _, _, _, _),
+ [46] = PINGROUP(46, qup13, edp_lcd, _, _, _, _, _, _, _),
+ [47] = PINGROUP(47, qup13, dp_hot, _, _, _, _, _, _, _),
+ [48] = PINGROUP(48, qup14, _, _, _, _, _, _, _, _),
+ [49] = PINGROUP(49, qup14, _, _, _, _, _, _, _, _),
+ [50] = PINGROUP(50, qup14, qup16, _, _, _, _, _, _, _),
+ [51] = PINGROUP(51, qup14, _, _, _, _, _, _, _, _),
+ [52] = PINGROUP(52, qup15, _, _, _, _, _, _, _, _),
+ [53] = PINGROUP(53, qup15, _, _, _, _, _, _, _, _),
+ [54] = PINGROUP(54, qup15, qup14, _, _, _, _, _, _, _),
+ [55] = PINGROUP(55, qup15, qup14, _, _, _, _, _, _, _),
+ [56] = PINGROUP(56, qup16, ddr_bist, phase_flag, _, _, _, _, _, _),
+ [57] = PINGROUP(57, qup16, ddr_bist, phase_flag, _, _, _, _, _, _),
+ [58] = PINGROUP(58, qup16, ddr_bist, phase_flag, qdss, _, _, _, _, _),
+ [59] = PINGROUP(59, qup16, ddr_bist, phase_flag, qdss, _, _, _, _, _),
+ [60] = PINGROUP(60, qup17, edp_hot, _, phase_flag, _, _, _, _, _),
+ [61] = PINGROUP(61, qup17, sd_write, phase_flag, tsense_pwm1, tsense_pwm2, _, _, _, _),
+ [62] = PINGROUP(62, qup17, qup16, phase_flag, _, _, _, _, _, _),
+ [63] = PINGROUP(63, qup17, qup16, phase_flag, _, _, _, _, _, _),
+ [64] = PINGROUP(64, cam_mclk, _, _, _, _, _, _, _, _),
+ [65] = PINGROUP(65, cam_mclk, tgu_ch0, _, _, _, _, _, _, _),
+ [66] = PINGROUP(66, cam_mclk, pll_bypassnl, tgu_ch1, _, _, _, _, _, _),
+ [67] = PINGROUP(67, cam_mclk, pll_reset, _, _, _, _, _, _, _),
+ [68] = PINGROUP(68, cam_mclk, _, _, _, _, _, _, _, _),
+ [69] = PINGROUP(69, cci_i2c, _, _, _, _, _, _, _, _),
+ [70] = PINGROUP(70, cci_i2c, _, _, _, _, _, _, _, _),
+ [71] = PINGROUP(71, cci_i2c, _, _, _, _, _, _, _, _),
+ [72] = PINGROUP(72, cci_i2c, _, _, _, _, _, _, _, _),
+ [73] = PINGROUP(73, cci_i2c, _, _, _, _, _, _, _, _),
+ [74] = PINGROUP(74, cci_i2c, _, _, _, _, _, _, _, _),
+ [75] = PINGROUP(75, cci_i2c, _, _, _, _, _, _, _, _),
+ [76] = PINGROUP(76, cci_i2c, gcc_gp1, _, _, _, _, _, _, _),
+ [77] = PINGROUP(77, cci_timer2, gcc_gp2, _, atest_usb13, atest_char0, _, _, _, _),
+ [78] = PINGROUP(78, cci_timer3, cci_async, gcc_gp3, _, atest_usb12, atest_char1, _, _, _),
+ [79] = PINGROUP(79, cci_timer4, cci_async, pcie1_clkreqn, mdp_vsync, jitter_bist, atest_usb11, atest_char2, _, _),
+ [80] = PINGROUP(80, mdp_vsync, vfr_0, mdp_vsync0, mdp_vsync1, mdp_vsync4, pll_bist, atest_usb10, atest_char3, _),
+ [81] = PINGROUP(81, mdp_vsync, dp_lcd, mdp_vsync2, mdp_vsync3, mdp_vsync5, atest_usb1, atest_char, _, _),
+ [82] = PINGROUP(82, _, _, _, _, _, _, _, _, _),
+ [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _),
+ [84] = PINGROUP(84, usb2phy_ac, _, _, _, _, _, _, _, _),
+ [85] = PINGROUP(85, usb2phy_ac, _, _, _, _, _, _, _, _),
+ [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _),
+ [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _),
+ [88] = PINGROUP(88, pcie0_clkreqn, _, _, _, _, _, _, _, _),
+ [89] = PINGROUP(89, _, _, _, _, _, _, _, _, _),
+ [90] = PINGROUP(90, _, _, _, _, _, _, _, _, _),
+ [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _),
+ [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _),
+ [93] = PINGROUP(93, cam_mclk, cci_async, _, _, _, _, _, _, _),
+ [94] = PINGROUP(94, lpass_slimbus, _, _, _, _, _, _, _, _),
+ [95] = PINGROUP(95, lpass_slimbus, _, _, _, _, _, _, _, _),
+ [96] = PINGROUP(96, pri_mi2s, _, _, _, _, _, _, _, _),
+ [97] = PINGROUP(97, mi2s0_sck, _, _, _, _, _, _, _, _),
+ [98] = PINGROUP(98, mi2s0_data0, _, _, _, _, _, _, _, _),
+ [99] = PINGROUP(99, mi2s0_data1, _, _, _, _, _, _, _, _),
+ [100] = PINGROUP(100, mi2s0_ws, _, vsense_trigger, _, _, _, _, _, _),
+ [101] = PINGROUP(101, mi2s2_sck, _, qdss, _, _, _, _, _, _),
+ [102] = PINGROUP(102, mi2s2_data0, _, _, qdss, _, _, _, _, _),
+ [103] = PINGROUP(103, mi2s2_ws, vfr_1, _, _, qdss, _, atest_usb03, _, _),
+ [104] = PINGROUP(104, mi2s2_data1, _, _, qdss, _, atest_usb02, _, _, _),
+ [105] = PINGROUP(105, sec_mi2s, mi2s1_data1, audio_ref, gcc_gp1, _, qdss, atest_usb01, _, _),
+ [106] = PINGROUP(106, mi2s1_sck, gcc_gp2, _, qdss, atest_usb00, _, _, _, _),
+ [107] = PINGROUP(107, mi2s1_data0, gcc_gp3, _, qdss, atest_usb0, _, _, _, _),
+ [108] = PINGROUP(108, mi2s1_ws, _, qdss, _, _, _, _, _, _),
+ [109] = PINGROUP(109, uim1_data, _, _, _, _, _, _, _, _),
+ [110] = PINGROUP(110, uim1_clk, _, _, _, _, _, _, _, _),
+ [111] = PINGROUP(111, uim1_reset, _, _, _, _, _, _, _, _),
+ [112] = PINGROUP(112, uim1_present, _, _, _, _, _, _, _, _),
+ [113] = PINGROUP(113, uim0_data, _, _, _, _, _, _, _, _),
+ [114] = PINGROUP(114, uim0_clk, _, _, _, _, _, _, _, _),
+ [115] = PINGROUP(115, uim0_reset, _, _, _, _, _, _, _, _),
+ [116] = PINGROUP(116, uim0_present, _, _, _, _, _, _, _, _),
+ [117] = PINGROUP(117, _, mss_grfc0, cmu_rng3, phase_flag, _, _, _, _, _),
+ [118] = PINGROUP(118, _, mss_grfc1, cmu_rng2, phase_flag, _, _, _, _, _),
+ [119] = PINGROUP(119, _, mss_grfc2, cmu_rng1, phase_flag, _, _, _, _, _),
+ [120] = PINGROUP(120, _, mss_grfc3, cmu_rng0, phase_flag, _, _, _, _, _),
+ [121] = PINGROUP(121, _, mss_grfc4, cri_trng0, phase_flag, _, _, _, _, _),
+ [122] = PINGROUP(122, _, mss_grfc5, cri_trng1, phase_flag, _, _, _, _, _),
+ [123] = PINGROUP(123, _, mss_grfc6, prng_rosc, phase_flag, _, _, _, _, _),
+ [124] = PINGROUP(124, _, mss_grfc7, cri_trng, phase_flag, _, _, _, _, _),
+ [125] = PINGROUP(125, _, mss_grfc8, phase_flag, _, _, _, _, _, _),
+ [126] = PINGROUP(126, _, mss_grfc9, phase_flag, _, _, _, _, _, _),
+ [127] = PINGROUP(127, coex_uart1, mss_grfc10, phase_flag, _, _, _, _, _, _),
+ [128] = PINGROUP(128, coex_uart1, mss_grfc11, phase_flag, _, _, _, _, _, _),
+ [129] = PINGROUP(129, nav_gpio0, phase_flag, _, _, _, _, _, _, _),
+ [130] = PINGROUP(130, nav_gpio1, phase_flag, _, _, _, _, _, _, _),
+ [131] = PINGROUP(131, mss_grfc12, nav_gpio2, pa_indicator, phase_flag, _, _, _, _, _),
+ [132] = PINGROUP(132, mss_grfc0, phase_flag, _, _, _, _, _, _, _),
+ [133] = PINGROUP(133, qlink0_request, _, _, _, _, _, _, _, _),
+ [134] = PINGROUP(134, qlink0_enable, _, _, _, _, _, _, _, _),
+ [135] = PINGROUP(135, qlink0_wmss, _, _, _, _, _, _, _, _),
+ [136] = PINGROUP(136, qlink1_request, _, _, _, _, _, _, _, _),
+ [137] = PINGROUP(137, qlink1_enable, _, _, _, _, _, _, _, _),
+ [138] = PINGROUP(138, qlink1_wmss, _, _, _, _, _, _, _, _),
+ [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _),
+ [140] = PINGROUP(140, usb_phy, pll_clk, _, _, _, _, _, _, _),
+ [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _),
+ [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _),
+ [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _),
+ [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _),
+ [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _),
+ [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _),
+ [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _),
+ [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _),
+ [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _),
+ [150] = PINGROUP(150, qdss, _, _, _, _, _, _, _, _),
+ [151] = PINGROUP(151, qdss, _, _, _, _, _, _, _, _),
+ [152] = PINGROUP(152, qdss, _, _, _, _, _, _, _, _),
+ [153] = PINGROUP(153, qdss, _, _, _, _, _, _, _, _),
+ [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _),
+ [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _),
+ [156] = PINGROUP(156, qdss_cti, _, _, _, _, _, _, _, _),
+ [157] = PINGROUP(157, qdss_cti, _, _, _, _, _, _, _, _),
+ [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _),
+ [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _),
+ [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _),
+ [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _),
+ [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _),
+ [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _),
+ [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _),
+ [165] = PINGROUP(165, qdss_cti, _, _, _, _, _, _, _, _),
+ [166] = PINGROUP(166, qdss_cti, _, _, _, _, _, _, _, _),
+ [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _),
+ [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _),
+ [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _),
+ [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _),
+ [171] = PINGROUP(171, qdss, _, _, _, _, _, _, _, _),
+ [172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, _),
+ [173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, _),
+ [174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, _),
+ [175] = UFS_RESET(ufs_reset, 0x1be000),
+ [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1b3000, 15, 0),
+ [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0x1b3000, 13, 6),
+ [178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x1b3000, 11, 3),
+ [179] = SDC_QDSD_PINGROUP(sdc1_data, 0x1b3000, 9, 0),
+ [180] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1b4000, 14, 6),
+ [181] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1b4000, 11, 3),
+ [182] = SDC_QDSD_PINGROUP(sdc2_data, 0x1b4000, 9, 0),
+};
+
+static const struct msm_pinctrl_soc_data sc7280_pinctrl = {
+ .pins = sc7280_pins,
+ .npins = ARRAY_SIZE(sc7280_pins),
+ .functions = sc7280_functions,
+ .nfunctions = ARRAY_SIZE(sc7280_functions),
+ .groups = sc7280_groups,
+ .ngroups = ARRAY_SIZE(sc7280_groups),
+ .ngpios = 176,
+};
+
+static int sc7280_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &sc7280_pinctrl);
+}
+
+static const struct of_device_id sc7280_pinctrl_of_match[] = {
+ { .compatible = "qcom,sc7280-pinctrl", },
+ { },
+};
+
+static struct platform_driver sc7280_pinctrl_driver = {
+ .driver = {
+ .name = "sc7280-pinctrl",
+ .of_match_table = sc7280_pinctrl_of_match,
+ },
+ .probe = sc7280_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init sc7280_pinctrl_init(void)
+{
+ return platform_driver_register(&sc7280_pinctrl_driver);
+}
+arch_initcall(sc7280_pinctrl_init);
+
+static void __exit sc7280_pinctrl_exit(void)
+{
+ platform_driver_unregister(&sc7280_pinctrl_driver);
+}
+module_exit(sc7280_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI sc7280 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, sc7280_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c
new file mode 100644
index 000000000000..2b5b0e2b03ad
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c
@@ -0,0 +1,1018 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define REG_SIZE 0x1000
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = REG_SIZE * id, \
+ .io_reg = 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
+ .intr_status_reg = 0xc + REG_SIZE * id, \
+ .intr_target_reg = 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+static const struct pinctrl_pin_desc sdx55_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "SDC1_RCLK"),
+ PINCTRL_PIN(109, "SDC1_CLK"),
+ PINCTRL_PIN(110, "SDC1_CMD"),
+ PINCTRL_PIN(111, "SDC1_DATA"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+
+static const unsigned int sdc1_rclk_pins[] = { 108 };
+static const unsigned int sdc1_clk_pins[] = { 109 };
+static const unsigned int sdc1_cmd_pins[] = { 110 };
+static const unsigned int sdc1_data_pins[] = { 111 };
+
+enum sdx55_functions {
+ msm_mux_adsp_ext,
+ msm_mux_atest,
+ msm_mux_audio_ref,
+ msm_mux_bimc_dte0,
+ msm_mux_bimc_dte1,
+ msm_mux_blsp_i2c1,
+ msm_mux_blsp_i2c2,
+ msm_mux_blsp_i2c3,
+ msm_mux_blsp_i2c4,
+ msm_mux_blsp_spi1,
+ msm_mux_blsp_spi2,
+ msm_mux_blsp_spi3,
+ msm_mux_blsp_spi4,
+ msm_mux_blsp_uart1,
+ msm_mux_blsp_uart2,
+ msm_mux_blsp_uart3,
+ msm_mux_blsp_uart4,
+ msm_mux_char_exec,
+ msm_mux_coex_uart,
+ msm_mux_coex_uart2,
+ msm_mux_cri_trng,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_dbg_out,
+ msm_mux_ddr_bist,
+ msm_mux_ddr_pxi0,
+ msm_mux_ebi0_wrcdc,
+ msm_mux_ebi2_a,
+ msm_mux_ebi2_lcd,
+ msm_mux_emac_gcc0,
+ msm_mux_emac_gcc1,
+ msm_mux_emac_pps0,
+ msm_mux_emac_pps1,
+ msm_mux_ext_dbg,
+ msm_mux_gcc_gp1,
+ msm_mux_gcc_gp2,
+ msm_mux_gcc_gp3,
+ msm_mux_gcc_plltest,
+ msm_mux_gpio,
+ msm_mux_i2s_mclk,
+ msm_mux_jitter_bist,
+ msm_mux_ldo_en,
+ msm_mux_ldo_update,
+ msm_mux_mgpi_clk,
+ msm_mux_m_voc,
+ msm_mux_native_char,
+ msm_mux_native_char0,
+ msm_mux_native_char1,
+ msm_mux_native_char2,
+ msm_mux_native_char3,
+ msm_mux_native_tsens,
+ msm_mux_native_tsense,
+ msm_mux_nav_gpio,
+ msm_mux_pa_indicator,
+ msm_mux_pcie_clkreq,
+ msm_mux_pci_e,
+ msm_mux_pll_bist,
+ msm_mux_pll_ref,
+ msm_mux_pll_test,
+ msm_mux_pri_mi2s,
+ msm_mux_prng_rosc,
+ msm_mux_qdss_cti,
+ msm_mux_qdss_gpio,
+ msm_mux_qdss_stm,
+ msm_mux_qlink0_en,
+ msm_mux_qlink0_req,
+ msm_mux_qlink0_wmss,
+ msm_mux_qlink1_en,
+ msm_mux_qlink1_req,
+ msm_mux_qlink1_wmss,
+ msm_mux_spmi_coex,
+ msm_mux_sec_mi2s,
+ msm_mux_spmi_vgi,
+ msm_mux_tgu_ch0,
+ msm_mux_uim1_clk,
+ msm_mux_uim1_data,
+ msm_mux_uim1_present,
+ msm_mux_uim1_reset,
+ msm_mux_uim2_clk,
+ msm_mux_uim2_data,
+ msm_mux_uim2_present,
+ msm_mux_uim2_reset,
+ msm_mux_usb2phy_ac,
+ msm_mux_vsense_trigger,
+ msm_mux__,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio52", "gpio53", "gpio53", "gpio54",
+ "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68",
+ "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75",
+ "gpio76", "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82",
+ "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
+ "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
+ "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102",
+ "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
+};
+
+static const char * const qdss_stm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13",
+ "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19" "gpio20", "gpio21", "gpio22",
+ "gpio23", "gpio44", "gpio45", "gpio52", "gpio53", "gpio56", "gpio57", "gpio61", "gpio62",
+ "gpio63", "gpio64", "gpio65", "gpio66",
+};
+
+static const char * const ddr_pxi0_groups[] = {
+ "gpio45", "gpio46",
+};
+
+static const char * const m_voc_groups[] = {
+ "gpio46", "gpio48", "gpio49", "gpio59", "gpio60",
+};
+
+static const char * const ddr_bist_groups[] = {
+ "gpio46", "gpio47", "gpio48", "gpio49",
+};
+
+static const char * const blsp_spi1_groups[] = {
+ "gpio52", "gpio62", "gpio71", "gpio80", "gpio81", "gpio82", "gpio83",
+};
+
+static const char * const pci_e_groups[] = {
+ "gpio53",
+};
+
+static const char * const tgu_ch0_groups[] = {
+ "gpio55",
+};
+
+static const char * const pcie_clkreq_groups[] = {
+ "gpio56",
+};
+
+static const char * const mgpi_clk_groups[] = {
+ "gpio61", "gpio71",
+};
+
+static const char * const i2s_mclk_groups[] = {
+ "gpio62",
+};
+
+static const char * const audio_ref_groups[] = {
+ "gpio62",
+};
+
+static const char * const ldo_update_groups[] = {
+ "gpio62",
+};
+
+static const char * const atest_groups[] = {
+ "gpio63", "gpio64", "gpio65", "gpio66", "gpio67",
+};
+
+static const char * const uim1_data_groups[] = {
+ "gpio67",
+};
+
+static const char * const uim1_present_groups[] = {
+ "gpio68",
+};
+
+static const char * const uim1_reset_groups[] = {
+ "gpio69",
+};
+
+static const char * const uim1_clk_groups[] = {
+ "gpio70",
+};
+
+static const char * const qlink1_en_groups[] = {
+ "gpio72",
+};
+
+static const char * const qlink1_req_groups[] = {
+ "gpio73",
+};
+
+static const char * const qlink1_wmss_groups[] = {
+ "gpio74",
+};
+
+static const char * const coex_uart2_groups[] = {
+ "gpio75", "gpio76",
+};
+
+static const char * const spmi_vgi_groups[] = {
+ "gpio78", "gpio79",
+};
+
+static const char * const gcc_plltest_groups[] = {
+ "gpio81", "gpio82",
+};
+
+static const char * const usb2phy_ac_groups[] = {
+ "gpio93",
+};
+
+static const char * const emac_pps1_groups[] = {
+ "gpio95",
+};
+
+static const char * const emac_pps0_groups[] = {
+ "gpio106",
+};
+
+static const char * const uim2_data_groups[] = {
+ "gpio0",
+};
+
+static const char * const ebi0_wrcdc_groups[] = {
+ "gpio0", "gpio2",
+};
+
+static const char * const uim2_present_groups[] = {
+ "gpio1",
+};
+
+static const char * const blsp_uart1_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio20", "gpio21", "gpio22",
+ "gpio23",
+};
+
+static const char * const uim2_reset_groups[] = {
+ "gpio2",
+};
+
+static const char * const blsp_i2c1_groups[] = {
+ "gpio2", "gpio3", "gpio82", "gpio83",
+};
+
+static const char * const uim2_clk_groups[] = {
+ "gpio3",
+};
+
+static const char * const blsp_spi2_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7", "gpio52", "gpio62", "gpio71",
+};
+
+static const char * const blsp_uart2_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65",
+ "gpio66",
+};
+
+static const char * const blsp_i2c2_groups[] = {
+ "gpio6", "gpio7", "gpio65", "gpio66",
+};
+
+static const char * const char_exec_groups[] = {
+ "gpio6", "gpio7",
+};
+
+static const char * const pri_mi2s_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15",
+};
+
+static const char * const blsp_spi3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio52", "gpio62", "gpio71",
+};
+
+static const char * const blsp_uart3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+
+static const char * const ext_dbg_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+
+static const char * const ldo_en_groups[] = {
+ "gpio8",
+};
+
+static const char * const blsp_i2c3_groups[] = {
+ "gpio10", "gpio11",
+};
+
+static const char * const gcc_gp3_groups[] = {
+ "gpio11",
+};
+
+static const char * const emac_gcc1_groups[] = {
+ "gpio14",
+};
+
+static const char * const bimc_dte0_groups[] = {
+ "gpio14", "gpio59",
+};
+
+static const char * const native_tsens_groups[] = {
+ "gpio14",
+};
+
+static const char * const vsense_trigger_groups[] = {
+ "gpio14",
+};
+
+static const char * const emac_gcc0_groups[] = {
+ "gpio15",
+};
+
+static const char * const bimc_dte1_groups[] = {
+ "gpio15", "gpio61",
+};
+
+static const char * const sec_mi2s_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
+ "gpio23",
+};
+
+static const char * const blsp_spi4_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19", "gpio52", "gpio62", "gpio71",
+};
+
+static const char * const blsp_uart4_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
+ "gpio23",
+};
+
+static const char * const qdss_cti_groups[] = {
+ "gpio16", "gpio16", "gpio17", "gpio17", "gpio22", "gpio22", "gpio23",
+ "gpio23", "gpio54", "gpio54", "gpio55", "gpio55", "gpio59", "gpio60",
+ "gpio94", "gpio94", "gpio95", "gpio95",
+};
+
+static const char * const blsp_i2c4_groups[] = {
+ "gpio18", "gpio19", "gpio78", "gpio79",
+};
+
+static const char * const gcc_gp1_groups[] = {
+ "gpio18",
+};
+
+static const char * const jitter_bist_groups[] = {
+ "gpio19",
+};
+
+static const char * const gcc_gp2_groups[] = {
+ "gpio19",
+};
+
+static const char * const ebi2_a_groups[] = {
+ "gpio20",
+};
+
+static const char * const ebi2_lcd_groups[] = {
+ "gpio21", "gpio22", "gpio23",
+};
+
+static const char * const pll_bist_groups[] = {
+ "gpio22",
+};
+
+static const char * const adsp_ext_groups[] = {
+ "gpio24", "gpio25",
+};
+
+static const char * const native_char_groups[] = {
+ "gpio26",
+};
+
+static const char * const qlink0_wmss_groups[] = {
+ "gpio28",
+};
+
+static const char * const native_char3_groups[] = {
+ "gpio28",
+};
+
+static const char * const native_char2_groups[] = {
+ "gpio29",
+};
+
+static const char * const native_tsense_groups[] = {
+ "gpio29",
+};
+
+static const char * const nav_gpio_groups[] = {
+ "gpio31", "gpio32", "gpio76",
+};
+
+static const char * const pll_ref_groups[] = {
+ "gpio32",
+};
+
+static const char * const pa_indicator_groups[] = {
+ "gpio33",
+};
+
+static const char * const native_char0_groups[] = {
+ "gpio33",
+};
+
+static const char * const qlink0_en_groups[] = {
+ "gpio34",
+};
+
+static const char * const qlink0_req_groups[] = {
+ "gpio35",
+};
+
+static const char * const pll_test_groups[] = {
+ "gpio35",
+};
+
+static const char * const cri_trng_groups[] = {
+ "gpio36",
+};
+
+static const char * const dbg_out_groups[] = {
+ "gpio36",
+};
+
+static const char * const prng_rosc_groups[] = {
+ "gpio38",
+};
+
+static const char * const cri_trng0_groups[] = {
+ "gpio40",
+};
+
+static const char * const cri_trng1_groups[] = {
+ "gpio41",
+};
+
+static const char * const qdss_gpio_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
+ "gpio42", "gpio61", "gpio63", "gpio64", "gpio65", "gpio66",
+};
+
+static const char * const native_char1_groups[] = {
+ "gpio42",
+};
+
+static const char * const coex_uart_groups[] = {
+ "gpio44", "gpio45",
+};
+
+static const char * const spmi_coex_groups[] = {
+ "gpio44", "gpio45",
+};
+
+static const struct msm_function sdx55_functions[] = {
+ FUNCTION(adsp_ext),
+ FUNCTION(atest),
+ FUNCTION(audio_ref),
+ FUNCTION(bimc_dte0),
+ FUNCTION(bimc_dte1),
+ FUNCTION(blsp_i2c1),
+ FUNCTION(blsp_i2c2),
+ FUNCTION(blsp_i2c3),
+ FUNCTION(blsp_i2c4),
+ FUNCTION(blsp_spi1),
+ FUNCTION(blsp_spi2),
+ FUNCTION(blsp_spi3),
+ FUNCTION(blsp_spi4),
+ FUNCTION(blsp_uart1),
+ FUNCTION(blsp_uart2),
+ FUNCTION(blsp_uart3),
+ FUNCTION(blsp_uart4),
+ FUNCTION(char_exec),
+ FUNCTION(coex_uart),
+ FUNCTION(coex_uart2),
+ FUNCTION(cri_trng),
+ FUNCTION(cri_trng0),
+ FUNCTION(cri_trng1),
+ FUNCTION(dbg_out),
+ FUNCTION(ddr_bist),
+ FUNCTION(ddr_pxi0),
+ FUNCTION(ebi0_wrcdc),
+ FUNCTION(ebi2_a),
+ FUNCTION(ebi2_lcd),
+ FUNCTION(emac_gcc0),
+ FUNCTION(emac_gcc1),
+ FUNCTION(emac_pps0),
+ FUNCTION(emac_pps1),
+ FUNCTION(ext_dbg),
+ FUNCTION(gcc_gp1),
+ FUNCTION(gcc_gp2),
+ FUNCTION(gcc_gp3),
+ FUNCTION(gcc_plltest),
+ FUNCTION(gpio),
+ FUNCTION(i2s_mclk),
+ FUNCTION(jitter_bist),
+ FUNCTION(ldo_en),
+ FUNCTION(ldo_update),
+ FUNCTION(mgpi_clk),
+ FUNCTION(m_voc),
+ FUNCTION(native_char),
+ FUNCTION(native_char0),
+ FUNCTION(native_char1),
+ FUNCTION(native_char2),
+ FUNCTION(native_char3),
+ FUNCTION(native_tsens),
+ FUNCTION(native_tsense),
+ FUNCTION(nav_gpio),
+ FUNCTION(pa_indicator),
+ FUNCTION(pcie_clkreq),
+ FUNCTION(pci_e),
+ FUNCTION(pll_bist),
+ FUNCTION(pll_ref),
+ FUNCTION(pll_test),
+ FUNCTION(pri_mi2s),
+ FUNCTION(prng_rosc),
+ FUNCTION(qdss_cti),
+ FUNCTION(qdss_gpio),
+ FUNCTION(qdss_stm),
+ FUNCTION(qlink0_en),
+ FUNCTION(qlink0_req),
+ FUNCTION(qlink0_wmss),
+ FUNCTION(qlink1_en),
+ FUNCTION(qlink1_req),
+ FUNCTION(qlink1_wmss),
+ FUNCTION(spmi_coex),
+ FUNCTION(sec_mi2s),
+ FUNCTION(spmi_vgi),
+ FUNCTION(tgu_ch0),
+ FUNCTION(uim1_clk),
+ FUNCTION(uim1_data),
+ FUNCTION(uim1_present),
+ FUNCTION(uim1_reset),
+ FUNCTION(uim2_clk),
+ FUNCTION(uim2_data),
+ FUNCTION(uim2_present),
+ FUNCTION(uim2_reset),
+ FUNCTION(usb2phy_ac),
+ FUNCTION(vsense_trigger),
+};
+
+/* Every pin is maintained as a single group, and missing or non-existing pin
+ * would be maintained as dummy group to synchronize pin group index with
+ * pin descriptor registered with pinctrl core.
+ * Clients would not be able to request these dummy pin groups.
+ */
+static const struct msm_pingroup sdx55_groups[] = {
+ [0] = PINGROUP(0, uim2_data, blsp_uart1, qdss_stm, ebi0_wrcdc, _, _, _, _, _),
+ [1] = PINGROUP(1, uim2_present, blsp_uart1, qdss_stm, _, _, _, _, _, _),
+ [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, qdss_stm, ebi0_wrcdc, _, _, _, _),
+ [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, qdss_stm, _, _, _, _, _),
+ [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _),
+ [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _),
+ [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _),
+ [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _),
+ [8] = PINGROUP(8, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _),
+ [9] = PINGROUP(9, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _),
+ [10] = PINGROUP(10, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _),
+ [11] = PINGROUP(11, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _),
+ [12] = PINGROUP(12, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _),
+ [13] = PINGROUP(13, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _),
+ [14] = PINGROUP(14, pri_mi2s, emac_gcc1, _, _, qdss_stm, qdss_gpio, bimc_dte0, native_tsens, vsense_trigger),
+ [15] = PINGROUP(15, pri_mi2s, emac_gcc0, _, _, qdss_stm, qdss_gpio, bimc_dte1, _, _),
+ [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_stm, qdss_gpio),
+ [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_stm, qdss_gpio, _),
+ [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_stm, qdss_gpio, _, _),
+ [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_stm, qdss_gpio),
+ [20] = PINGROUP(20, sec_mi2s, ebi2_a, blsp_uart1, blsp_uart4, qdss_stm, _, _, _, _),
+ [21] = PINGROUP(21, sec_mi2s, ebi2_lcd, blsp_uart1, blsp_uart4, _, qdss_stm, _, _, _),
+ [22] = PINGROUP(22, sec_mi2s, ebi2_lcd, blsp_uart1, qdss_cti, qdss_cti, blsp_uart4, pll_bist, _, qdss_stm),
+ [23] = PINGROUP(23, sec_mi2s, ebi2_lcd, qdss_cti, qdss_cti, blsp_uart1, blsp_uart4, qdss_stm, _, _),
+ [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _),
+ [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _),
+ [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _),
+ [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _),
+ [28] = PINGROUP(28, qlink0_wmss, _, native_char3, _, _, _, _, _, _),
+ [29] = PINGROUP(29, _, _, _, native_char2, native_tsense, _, _, _, _),
+ [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _),
+ [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _),
+ [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _),
+ [33] = PINGROUP(33, _, pa_indicator, native_char0, _, _, _, _, _, _),
+ [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _),
+ [35] = PINGROUP(35, qlink0_req, pll_test, _, _, _, _, _, _, _),
+ [36] = PINGROUP(36, _, _, cri_trng, dbg_out, _, _, _, _, _),
+ [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _),
+ [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _),
+ [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _),
+ [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _),
+ [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _),
+ [42] = PINGROUP(42, _, qdss_gpio, native_char1, _, _, _, _, _, _),
+ [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _),
+ [44] = PINGROUP(44, coex_uart, spmi_coex, _, qdss_stm, _, _, _, _, _),
+ [45] = PINGROUP(45, coex_uart, spmi_coex, qdss_stm, ddr_pxi0, _, _, _, _, _),
+ [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _),
+ [47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _, _, _),
+ [48] = PINGROUP(48, m_voc, ddr_bist, _, _, _, _, _, _, _),
+ [49] = PINGROUP(49, m_voc, ddr_bist, _, _, _, _, _, _, _),
+ [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _),
+ [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _),
+ [52] = PINGROUP(52, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, qdss_stm, _, _),
+ [53] = PINGROUP(53, pci_e, _, _, qdss_stm, _, _, _, _, _),
+ [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
+ [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _),
+ [56] = PINGROUP(56, pcie_clkreq, _, qdss_stm, _, _, _, _, _, _),
+ [57] = PINGROUP(57, _, qdss_stm, _, _, _, _, _, _, _),
+ [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _),
+ [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _),
+ [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _),
+ [61] = PINGROUP(61, mgpi_clk, qdss_stm, qdss_gpio, bimc_dte1, _, _, _, _, _),
+ [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, qdss_stm, _),
+ [63] = PINGROUP(63, blsp_uart2, _, qdss_stm, qdss_gpio, atest, _, _, _, _),
+ [64] = PINGROUP(64, blsp_uart2, qdss_stm, qdss_gpio, atest, _, _, _, _, _),
+ [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, _, qdss_stm, qdss_gpio, atest, _, _, _),
+ [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_stm, qdss_gpio, atest, _, _, _, _),
+ [67] = PINGROUP(67, uim1_data, atest, _, _, _, _, _, _, _),
+ [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _),
+ [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _),
+ [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _),
+ [71] = PINGROUP(71, mgpi_clk, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _),
+ [72] = PINGROUP(72, qlink1_en, _, _, _, _, _, _, _, _),
+ [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _),
+ [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _),
+ [75] = PINGROUP(75, coex_uart2, _, _, _, _, _, _, _, _),
+ [76] = PINGROUP(76, coex_uart2, nav_gpio, _, _, _, _, _, _, _),
+ [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _),
+ [78] = PINGROUP(78, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _),
+ [79] = PINGROUP(79, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _),
+ [80] = PINGROUP(80, _, blsp_spi1, _, _, _, _, _, _, _),
+ [81] = PINGROUP(81, _, blsp_spi1, _, gcc_plltest, _, _, _, _, _),
+ [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _),
+ [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _),
+ [84] = PINGROUP(84, _, _, _, _, _, _, _, _, _),
+ [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _),
+ [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _),
+ [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _),
+ [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _),
+ [89] = PINGROUP(89, _, _, _, _, _, _, _, _, _),
+ [90] = PINGROUP(90, _, _, _, _, _, _, _, _, _),
+ [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _),
+ [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _),
+ [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _),
+ [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
+ [95] = PINGROUP(95, qdss_cti, qdss_cti, emac_pps1, _, _, _, _, _, _),
+ [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _),
+ [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _),
+ [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _),
+ [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _),
+ [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _),
+ [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _),
+ [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _),
+ [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _),
+ [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _),
+ [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _),
+ [106] = PINGROUP(106, emac_pps0, _, _, _, _, _, _, _, _),
+ [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _),
+ [109] = SDC_PINGROUP(sdc1_rclk, 0x9a000, 15, 0),
+ [110] = SDC_PINGROUP(sdc1_clk, 0x9a000, 13, 6),
+ [111] = SDC_PINGROUP(sdc1_cmd, 0x9a000, 11, 3),
+ [112] = SDC_PINGROUP(sdc1_data, 0x9a000, 9, 0),
+};
+
+static const struct msm_pinctrl_soc_data sdx55_pinctrl = {
+ .pins = sdx55_pins,
+ .npins = ARRAY_SIZE(sdx55_pins),
+ .functions = sdx55_functions,
+ .nfunctions = ARRAY_SIZE(sdx55_functions),
+ .groups = sdx55_groups,
+ .ngroups = ARRAY_SIZE(sdx55_groups),
+ .ngpios = 108,
+};
+
+static int sdx55_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &sdx55_pinctrl);
+}
+
+static const struct of_device_id sdx55_pinctrl_of_match[] = {
+ { .compatible = "qcom,sdx55-pinctrl", },
+ { },
+};
+
+static struct platform_driver sdx55_pinctrl_driver = {
+ .driver = {
+ .name = "sdx55-pinctrl",
+ .of_match_table = sdx55_pinctrl_of_match,
+ },
+ .probe = sdx55_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init sdx55_pinctrl_init(void)
+{
+ return platform_driver_register(&sdx55_pinctrl_driver);
+}
+arch_initcall(sdx55_pinctrl_init);
+
+static void __exit sdx55_pinctrl_exit(void)
+{
+ platform_driver_unregister(&sdx55_pinctrl_driver);
+}
+module_exit(sdx55_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI sdx55 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index 17441388ce8f..9801c717e311 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -1129,6 +1129,8 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
+ /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
+ { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
{ },
};
diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c
index c528c124fb0e..2cc457279345 100644
--- a/drivers/pinctrl/renesas/core.c
+++ b/drivers/pinctrl/renesas/core.c
@@ -315,6 +315,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
range = NULL;
break;
+#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
case PINMUX_TYPE_OUTPUT:
range = &pfc->info->output;
break;
@@ -322,6 +323,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
case PINMUX_TYPE_INPUT:
range = &pfc->info->input;
break;
+#endif /* CONFIG_PINCTRL_SH_PFC_GPIO */
default:
return -EINVAL;
diff --git a/drivers/pinctrl/renesas/core.h b/drivers/pinctrl/renesas/core.h
index b5b1d163e98a..5ca7e0830ae9 100644
--- a/drivers/pinctrl/renesas/core.h
+++ b/drivers/pinctrl/renesas/core.h
@@ -33,4 +33,8 @@ const struct pinmux_bias_reg *
sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *bit);
+unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
+void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ unsigned int bias);
+
#endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c
index 9c6e931ae766..ad06f5355d1e 100644
--- a/drivers/pinctrl/renesas/gpio.c
+++ b/drivers/pinctrl/renesas/gpio.c
@@ -328,7 +328,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
if (pfc->info->data_regs == NULL)
return 0;
- /* Find the memory window that contain the GPIO registers. Boards that
+ /* Find the memory window that contains the GPIO registers. Boards that
* register a separate GPIO device will not supply a memory resource
* that covers the data registers. In that case don't try to handle
* GPIOs.
diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c
index a9875038ed9b..75f52b1798c3 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7778.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7778.c
@@ -2909,7 +2909,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
};
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
- { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
+ { PINMUX_BIAS_REG("PUPR0", 0xfffc0100, "N/A", 0) {
[ 0] = RCAR_GP_PIN(0, 6), /* A0 */
[ 1] = RCAR_GP_PIN(0, 7), /* A1 */
[ 2] = RCAR_GP_PIN(0, 8), /* A2 */
@@ -2943,7 +2943,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = RCAR_GP_PIN(1, 7), /* /EX_CS4 */
[31] = RCAR_GP_PIN(1, 8), /* /EX_CS5 */
} },
- { PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) {
+ { PINMUX_BIAS_REG("PUPR1", 0xfffc0104, "N/A", 0) {
[ 0] = RCAR_GP_PIN(0, 0), /* /PRESETOUT */
[ 1] = RCAR_GP_PIN(0, 5), /* /BS */
[ 2] = RCAR_GP_PIN(1, 0), /* RD//WR */
@@ -2977,7 +2977,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
+ { PINMUX_BIAS_REG("PUPR2", 0xfffc0108, "N/A", 0) {
[ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */
[ 1] = RCAR_GP_PIN(1, 23), /* DU0_DR1 */
[ 2] = RCAR_GP_PIN(1, 24), /* DU0_DR2 */
@@ -3011,7 +3011,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = RCAR_GP_PIN(2, 21), /* DU0_CDE */
[31] = RCAR_GP_PIN(2, 16), /* DU0_DOTCLKOUT1 */
} },
- { PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) {
+ { PINMUX_BIAS_REG("PUPR3", 0xfffc010c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(3, 24), /* VI0_CLK */
[ 1] = RCAR_GP_PIN(3, 25), /* VI0_CLKENB */
[ 2] = RCAR_GP_PIN(3, 26), /* VI0_FIELD */
@@ -3045,7 +3045,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = RCAR_GP_PIN(4, 18), /* ETH_MDIO */
[31] = RCAR_GP_PIN(4, 19), /* ETH_LINK */
} },
- { PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) {
+ { PINMUX_BIAS_REG("PUPR4", 0xfffc0110, "N/A", 0) {
[ 0] = RCAR_GP_PIN(3, 6), /* SSI_SCK012 */
[ 1] = RCAR_GP_PIN(3, 7), /* SSI_WS012 */
[ 2] = RCAR_GP_PIN(3, 10), /* SSI_SDATA0 */
@@ -3079,7 +3079,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = RCAR_GP_PIN(1, 14), /* IRQ2 */
[31] = RCAR_GP_PIN(1, 15), /* IRQ3 */
} },
- { PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) {
+ { PINMUX_BIAS_REG("PUPR5", 0xfffc0114, "N/A", 0) {
[ 0] = RCAR_GP_PIN(0, 1), /* PENC0 */
[ 1] = RCAR_GP_PIN(0, 2), /* PENC1 */
[ 2] = RCAR_GP_PIN(0, 3), /* USB_OVC0 */
@@ -3116,48 +3116,9 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
-static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
- unsigned int pin)
-{
- const struct pinmux_bias_reg *reg;
- void __iomem *addr;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return PIN_CONFIG_BIAS_DISABLE;
-
- addr = pfc->windows->virt + reg->puen;
-
- if (ioread32(addr) & BIT(bit))
- return PIN_CONFIG_BIAS_PULL_UP;
- else
- return PIN_CONFIG_BIAS_DISABLE;
-}
-
-static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
- unsigned int bias)
-{
- const struct pinmux_bias_reg *reg;
- void __iomem *addr;
- unsigned int bit;
- u32 value;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return;
-
- addr = pfc->windows->virt + reg->puen;
-
- value = ioread32(addr) & ~BIT(bit);
- if (bias == PIN_CONFIG_BIAS_PULL_UP)
- value |= BIT(bit);
- iowrite32(value, addr);
-}
-
static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
- .get_bias = r8a7778_pinmux_get_bias,
- .set_bias = r8a7778_pinmux_set_bias,
+ .get_bias = rcar_pinmux_get_bias,
+ .set_bias = rcar_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a7778_pinmux_info = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c
index 60f973c5dffe..e9a64e0e2734 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7790.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
@@ -2393,6 +2393,8 @@ static const unsigned int intc_irq3_pins[] = {
static const unsigned int intc_irq3_mux[] = {
IRQ3_MARK,
};
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
/* - MLB+ ------------------------------------------------------------------- */
static const unsigned int mlb_3pin_pins[] = {
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
@@ -2400,6 +2402,8 @@ static const unsigned int mlb_3pin_pins[] = {
static const unsigned int mlb_3pin_mux[] = {
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
+
/* - MMCIF0 ----------------------------------------------------------------- */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
@@ -3866,6 +3870,72 @@ static const unsigned int vin1_data18_mux[] = {
VI1_R4_MARK, VI1_R5_MARK,
VI1_R6_MARK, VI1_R7_MARK,
};
+static const union vin_data vin1_data_b_pins = {
+ .data24 = {
+ /* B */
+ RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ /* G */
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
+ /* R */
+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
+ },
+};
+static const union vin_data vin1_data_b_mux = {
+ .data24 = {
+ /* B */
+ VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
+ VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+ VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+ VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
+ /* G */
+ VI1_G0_B_MARK, VI1_G1_B_MARK,
+ VI1_G2_B_MARK, VI1_G3_B_MARK,
+ VI1_G4_B_MARK, VI1_G5_B_MARK,
+ VI1_G6_B_MARK, VI1_G7_B_MARK,
+ /* R */
+ VI1_R0_B_MARK, VI1_R1_B_MARK,
+ VI1_R2_B_MARK, VI1_R3_B_MARK,
+ VI1_R4_B_MARK, VI1_R5_B_MARK,
+ VI1_R6_B_MARK, VI1_R7_B_MARK,
+ },
+};
+static const unsigned int vin1_data18_b_pins[] = {
+ /* B */
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ /* G */
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
+ /* R */
+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int vin1_data18_b_mux[] = {
+ /* B */
+ VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+ VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+ VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
+ /* G */
+ VI1_G2_B_MARK, VI1_G3_B_MARK,
+ VI1_G4_B_MARK, VI1_G5_B_MARK,
+ VI1_G6_B_MARK, VI1_G7_B_MARK,
+ /* R */
+ VI1_R2_B_MARK, VI1_R3_B_MARK,
+ VI1_R4_B_MARK, VI1_R5_B_MARK,
+ VI1_R6_B_MARK, VI1_R7_B_MARK,
+};
static const unsigned int vin1_sync_pins[] = {
RCAR_GP_PIN(1, 24), /* HSYNC */
RCAR_GP_PIN(1, 25), /* VSYNC */
@@ -3874,24 +3944,50 @@ static const unsigned int vin1_sync_mux[] = {
VI1_HSYNC_N_MARK,
VI1_VSYNC_N_MARK,
};
+static const unsigned int vin1_sync_b_pins[] = {
+ RCAR_GP_PIN(1, 24), /* HSYNC */
+ RCAR_GP_PIN(1, 25), /* VSYNC */
+};
+static const unsigned int vin1_sync_b_mux[] = {
+ VI1_HSYNC_N_B_MARK,
+ VI1_VSYNC_N_B_MARK,
+};
static const unsigned int vin1_field_pins[] = {
RCAR_GP_PIN(1, 13),
};
static const unsigned int vin1_field_mux[] = {
VI1_FIELD_MARK,
};
+static const unsigned int vin1_field_b_pins[] = {
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int vin1_field_b_mux[] = {
+ VI1_FIELD_B_MARK,
+};
static const unsigned int vin1_clkenb_pins[] = {
RCAR_GP_PIN(1, 26),
};
static const unsigned int vin1_clkenb_mux[] = {
VI1_CLKENB_MARK,
};
+static const unsigned int vin1_clkenb_b_pins[] = {
+ RCAR_GP_PIN(1, 26),
+};
+static const unsigned int vin1_clkenb_b_mux[] = {
+ VI1_CLKENB_B_MARK,
+};
static const unsigned int vin1_clk_pins[] = {
RCAR_GP_PIN(2, 9),
};
static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
+static const unsigned int vin1_clk_b_pins[] = {
+ RCAR_GP_PIN(3, 15),
+};
+static const unsigned int vin1_clk_b_mux[] = {
+ VI1_CLK_B_MARK,
+};
/* - VIN2 ----------------------------------------------------------------- */
static const union vin_data vin2_data_pins = {
.data24 = {
@@ -3959,6 +4055,18 @@ static const unsigned int vin2_data18_mux[] = {
VI2_R4_MARK, VI2_R5_MARK,
VI2_R6_MARK, VI2_R7_MARK,
};
+static const unsigned int vin2_g8_pins[] = {
+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int vin2_g8_mux[] = {
+ VI2_G0_MARK, VI2_G1_MARK,
+ VI2_G2_MARK, VI2_G3_MARK,
+ VI2_G4_MARK, VI2_G5_MARK,
+ VI2_G6_MARK, VI2_G7_MARK,
+};
static const unsigned int vin2_sync_pins[] = {
RCAR_GP_PIN(1, 16), /* HSYNC */
RCAR_GP_PIN(1, 21), /* VSYNC */
@@ -4026,8 +4134,10 @@ static const unsigned int vin3_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[298];
+ struct sh_pfc_pin_group common[311];
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
struct sh_pfc_pin_group automotive[1];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a),
@@ -4310,15 +4420,28 @@ static const struct {
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 8),
VIN_DATA_PIN_GROUP(vin1_data, 4),
+ VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
+ SH_PFC_PIN_GROUP(vin1_data18_b),
+ VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 4, _b),
SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_sync_b),
SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_field_b),
SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clkenb_b),
SH_PFC_PIN_GROUP(vin1_clk),
+ SH_PFC_PIN_GROUP(vin1_clk_b),
VIN_DATA_PIN_GROUP(vin2_data, 24),
SH_PFC_PIN_GROUP(vin2_data18),
VIN_DATA_PIN_GROUP(vin2_data, 16),
VIN_DATA_PIN_GROUP(vin2_data, 8),
VIN_DATA_PIN_GROUP(vin2_data, 4),
+ SH_PFC_PIN_GROUP(vin2_g8),
SH_PFC_PIN_GROUP(vin2_sync),
SH_PFC_PIN_GROUP(vin2_field),
SH_PFC_PIN_GROUP(vin2_clkenb),
@@ -4329,9 +4452,11 @@ static const struct {
SH_PFC_PIN_GROUP(vin3_clkenb),
SH_PFC_PIN_GROUP(vin3_clk),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
.automotive = {
SH_PFC_PIN_GROUP(mlb_3pin),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
};
static const char * const audio_clk_groups[] = {
@@ -4475,9 +4600,11 @@ static const char * const intc_groups[] = {
"intc_irq3",
};
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
static const char * const mlb_groups[] = {
"mlb_3pin",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
static const char * const mmc0_groups[] = {
"mmc0_data1",
@@ -4784,10 +4911,22 @@ static const char * const vin1_groups[] = {
"vin1_data10",
"vin1_data8",
"vin1_data4",
+ "vin1_data24_b",
+ "vin1_data20_b",
+ "vin1_data18_b",
+ "vin1_data16_b",
+ "vin1_data12_b",
+ "vin1_data10_b",
+ "vin1_data8_b",
+ "vin1_data4_b",
"vin1_sync",
+ "vin1_sync_b",
"vin1_field",
+ "vin1_field_b",
"vin1_clkenb",
+ "vin1_clkenb_b",
"vin1_clk",
+ "vin1_clk_b",
};
static const char * const vin2_groups[] = {
@@ -4796,6 +4935,7 @@ static const char * const vin2_groups[] = {
"vin2_data16",
"vin2_data8",
"vin2_data4",
+ "vin2_g8",
"vin2_sync",
"vin2_field",
"vin2_clkenb",
@@ -4812,7 +4952,9 @@ static const char * const vin3_groups[] = {
static const struct {
struct sh_pfc_function common[58];
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
struct sh_pfc_function automotive[1];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -4874,9 +5016,11 @@ static const struct {
SH_PFC_FUNCTION(vin2),
SH_PFC_FUNCTION(vin3),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
.automotive = {
SH_PFC_FUNCTION(mlb),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c
index bc9caf812fc1..6fce9fe2e98f 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7791.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
@@ -1700,6 +1700,7 @@ static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
/* - ADI -------------------------------------------------------------------- */
static const unsigned int adi_common_pins[] = {
/* ADIDATA, ADICS/SAMP, ADICLK */
@@ -1765,6 +1766,7 @@ static const unsigned int adi_chsel2_b_mux[] = {
/* ADICHS B 2 */
ADICHS2_B_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
/* - Audio Clock ------------------------------------------------------------ */
static const unsigned int audio_clk_a_pins[] = {
@@ -2553,6 +2555,8 @@ static const unsigned int intc_irq3_pins[] = {
static const unsigned int intc_irq3_mux[] = {
IRQ3_MARK,
};
+
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
/* - MLB+ ------------------------------------------------------------------- */
static const unsigned int mlb_3pin_pins[] = {
RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
@@ -2560,6 +2564,8 @@ static const unsigned int mlb_3pin_pins[] = {
static const unsigned int mlb_3pin_mux[] = {
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
+
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc_data1_pins[] = {
/* D[0] */
@@ -4452,7 +4458,9 @@ static const unsigned int vin2_clk_mux[] = {
static const struct {
struct sh_pfc_pin_group common[346];
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
struct sh_pfc_pin_group automotive[9];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a),
@@ -4802,6 +4810,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin2_clkenb),
SH_PFC_PIN_GROUP(vin2_clk),
},
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
.automotive = {
SH_PFC_PIN_GROUP(adi_common),
SH_PFC_PIN_GROUP(adi_chsel0),
@@ -4813,8 +4822,10 @@ static const struct {
SH_PFC_PIN_GROUP(adi_chsel2_b),
SH_PFC_PIN_GROUP(mlb_3pin),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
};
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
static const char * const adi_groups[] = {
"adi_common",
"adi_chsel0",
@@ -4825,6 +4836,7 @@ static const char * const adi_groups[] = {
"adi_chsel1_b",
"adi_chsel2_b",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
static const char * const audio_clk_groups[] = {
"audio_clk_a",
@@ -5002,9 +5014,11 @@ static const char * const intc_groups[] = {
"intc_irq3",
};
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
static const char * const mlb_groups[] = {
"mlb_3pin",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
static const char * const mmc_groups[] = {
"mmc_data1",
@@ -5359,7 +5373,9 @@ static const char * const vin2_groups[] = {
static const struct {
struct sh_pfc_function common[58];
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
struct sh_pfc_function automotive[2];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -5421,10 +5437,12 @@ static const struct {
SH_PFC_FUNCTION(vin1),
SH_PFC_FUNCTION(vin2),
},
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
.automotive = {
SH_PFC_FUNCTION(adi),
SH_PFC_FUNCTION(mlb),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c
index 04812e62f3a4..32b66b9999b8 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77950.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77950.c
@@ -5820,51 +5820,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
-static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc,
- unsigned int pin)
-{
- const struct pinmux_bias_reg *reg;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return PIN_CONFIG_BIAS_DISABLE;
-
- if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
- return PIN_CONFIG_BIAS_DISABLE;
- else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
- return PIN_CONFIG_BIAS_PULL_UP;
- else
- return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
- unsigned int bias)
-{
- const struct pinmux_bias_reg *reg;
- u32 enable, updown;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return;
-
- enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
- if (bias != PIN_CONFIG_BIAS_DISABLE)
- enable |= BIT(bit);
-
- updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
- if (bias == PIN_CONFIG_BIAS_PULL_UP)
- updown |= BIT(bit);
-
- sh_pfc_write(pfc, reg->pud, updown);
- sh_pfc_write(pfc, reg->puen, enable);
-}
-
static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
.pin_to_pocctrl = r8a77950_pin_to_pocctrl,
- .get_bias = r8a77950_pinmux_get_bias,
- .set_bias = r8a77950_pinmux_set_bias,
+ .get_bias = rcar_pinmux_get_bias,
+ .set_bias = rcar_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a77950_pinmux_info = {
diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
index a94ebe0bf5d0..cf14420794c7 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77951.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -1827,6 +1827,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2041,6 +2042,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
@@ -3250,6 +3252,57 @@ static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* QSPI0_SPCLK, QSPI0_SSL */
+ PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+ /* QSPI0_IO2, QSPI0_IO3 */
+ PIN_QSPI0_IO2, PIN_QSPI0_IO3,
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* QSPI1_SPCLK, QSPI1_SSL */
+ PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+ /* QSPI1_IO2, QSPI1_IO3 */
+ PIN_QSPI1_IO2, PIN_QSPI1_IO3,
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+
/* - SATA --------------------------------------------------------------------*/
static const unsigned int sata0_devslp_a_pins[] = {
/* DEVSLP */
@@ -4158,8 +4211,10 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[320];
+ struct sh_pfc_pin_group common[326];
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
struct sh_pfc_pin_group automotive[30];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4361,6 +4416,12 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(scif0_data),
@@ -4483,6 +4544,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4515,7 +4577,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
-
+#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
};
static const char * const audio_clk_groups[] = {
@@ -4574,6 +4636,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4615,6 +4678,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
static const char * const du_groups[] = {
"du_rgb666",
@@ -4852,6 +4916,18 @@ static const char * const pwm6_groups[] = {
"pwm6_b",
};
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
static const char * const sata0_groups[] = {
"sata0_devslp_a",
"sata0_devslp_b",
@@ -5040,8 +5116,10 @@ static const char * const vin5_groups[] = {
};
static const struct {
- struct sh_pfc_function common[53];
+ struct sh_pfc_function common[55];
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
struct sh_pfc_function automotive[4];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -5075,6 +5153,8 @@ static const struct {
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(sata0),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
@@ -5098,13 +5178,14 @@ static const struct {
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
}
-
+#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -6191,51 +6272,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
-static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc,
- unsigned int pin)
-{
- const struct pinmux_bias_reg *reg;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return PIN_CONFIG_BIAS_DISABLE;
-
- if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
- return PIN_CONFIG_BIAS_DISABLE;
- else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
- return PIN_CONFIG_BIAS_PULL_UP;
- else
- return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
- unsigned int bias)
-{
- const struct pinmux_bias_reg *reg;
- u32 enable, updown;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return;
-
- enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
- if (bias != PIN_CONFIG_BIAS_DISABLE)
- enable |= BIT(bit);
-
- updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
- if (bias == PIN_CONFIG_BIAS_PULL_UP)
- updown |= BIT(bit);
-
- sh_pfc_write(pfc, reg->pud, updown);
- sh_pfc_write(pfc, reg->puen, enable);
-}
-
static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
.pin_to_pocctrl = r8a77951_pin_to_pocctrl,
- .get_bias = r8a77951_pinmux_get_bias,
- .set_bias = r8a77951_pinmux_set_bias,
+ .get_bias = rcar_pinmux_get_bias,
+ .set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 55f0344a3d3e..38d963561b5f 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -1831,6 +1831,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2045,6 +2046,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
@@ -3255,6 +3257,57 @@ static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* QSPI0_SPCLK, QSPI0_SSL */
+ PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+ /* QSPI0_IO2, QSPI0_IO3 */
+ PIN_QSPI0_IO2, PIN_QSPI0_IO3,
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* QSPI1_SPCLK, QSPI1_SSL */
+ PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+ /* QSPI1_IO2, QSPI1_IO3 */
+ PIN_QSPI1_IO2, PIN_QSPI1_IO3,
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX, TX */
@@ -4132,8 +4185,10 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[316];
+ struct sh_pfc_pin_group common[322];
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
struct sh_pfc_pin_group automotive[30];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4335,6 +4390,12 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -4453,6 +4514,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4485,6 +4547,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
};
static const char * const audio_clk_groups[] = {
@@ -4543,6 +4606,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4584,6 +4648,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
static const char * const du_groups[] = {
"du_rgb666",
@@ -4821,6 +4886,18 @@ static const char * const pwm6_groups[] = {
"pwm6_b",
};
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@@ -4996,8 +5073,10 @@ static const char * const vin5_groups[] = {
};
static const struct {
- struct sh_pfc_function common[50];
+ struct sh_pfc_function common[52];
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
struct sh_pfc_function automotive[4];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -5031,6 +5110,8 @@ static const struct {
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
@@ -5051,12 +5132,14 @@ static const struct {
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -6138,51 +6221,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
-static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
- unsigned int pin)
-{
- const struct pinmux_bias_reg *reg;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return PIN_CONFIG_BIAS_DISABLE;
-
- if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
- return PIN_CONFIG_BIAS_DISABLE;
- else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
- return PIN_CONFIG_BIAS_PULL_UP;
- else
- return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
- unsigned int bias)
-{
- const struct pinmux_bias_reg *reg;
- u32 enable, updown;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return;
-
- enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
- if (bias != PIN_CONFIG_BIAS_DISABLE)
- enable |= BIT(bit);
-
- updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
- if (bias == PIN_CONFIG_BIAS_PULL_UP)
- updown |= BIT(bit);
-
- sh_pfc_write(pfc, reg->pud, updown);
- sh_pfc_write(pfc, reg->puen, enable);
-}
-
static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
- .get_bias = r8a7796_pinmux_get_bias,
- .set_bias = r8a7796_pinmux_set_bias,
+ .get_bias = rcar_pinmux_get_bias,
+ .set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A774A1
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 7a50b9b69a7d..92f231baff7d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -1847,6 +1847,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2120,6 +2121,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
@@ -3406,6 +3408,57 @@ static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* QSPI0_SPCLK, QSPI0_SSL */
+ PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+ /* QSPI0_IO2, QSPI0_IO3 */
+ PIN_QSPI0_IO2, PIN_QSPI0_IO3,
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* QSPI1_SPCLK, QSPI1_SSL */
+ PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+ /* QSPI1_IO2, QSPI1_IO3 */
+ PIN_QSPI1_IO2, PIN_QSPI1_IO3,
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+
/* - SATA --------------------------------------------------------------------*/
static const unsigned int sata0_devslp_a_pins[] = {
/* DEVSLP */
@@ -4379,8 +4432,10 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[318];
+ struct sh_pfc_pin_group common[324];
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
struct sh_pfc_pin_group automotive[30];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4582,6 +4637,12 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(scif0_data),
@@ -4702,6 +4763,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4734,6 +4796,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
};
static const char * const audio_clk_groups[] = {
@@ -4792,6 +4855,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4833,6 +4897,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
static const char * const du_groups[] = {
"du_rgb666",
@@ -5070,6 +5135,18 @@ static const char * const pwm6_groups[] = {
"pwm6_b",
};
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
static const char * const sata0_groups[] = {
"sata0_devslp_a",
"sata0_devslp_b",
@@ -5249,8 +5326,10 @@ static const char * const vin5_groups[] = {
};
static const struct {
- struct sh_pfc_function common[51];
+ struct sh_pfc_function common[53];
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
struct sh_pfc_function automotive[4];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -5284,6 +5363,8 @@ static const struct {
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(sata0),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
@@ -5305,12 +5386,14 @@ static const struct {
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -6392,51 +6475,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
-static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
- unsigned int pin)
-{
- const struct pinmux_bias_reg *reg;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return PIN_CONFIG_BIAS_DISABLE;
-
- if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
- return PIN_CONFIG_BIAS_DISABLE;
- else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
- return PIN_CONFIG_BIAS_PULL_UP;
- else
- return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
- unsigned int bias)
-{
- const struct pinmux_bias_reg *reg;
- u32 enable, updown;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return;
-
- enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
- if (bias != PIN_CONFIG_BIAS_DISABLE)
- enable |= BIT(bit);
-
- updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
- if (bias == PIN_CONFIG_BIAS_PULL_UP)
- updown |= BIT(bit);
-
- sh_pfc_write(pfc, reg->pud, updown);
- sh_pfc_write(pfc, reg->puen, enable);
-}
-
static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
.pin_to_pocctrl = r8a77965_pin_to_pocctrl,
- .get_bias = r8a77965_pinmux_get_bias,
- .set_bias = r8a77965_pinmux_set_bias,
+ .get_bias = rcar_pinmux_get_bias,
+ .set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A774B1
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index aed04a4c6116..0a32e3c317c1 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -1593,6 +1593,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -1785,6 +1786,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
@@ -2808,6 +2810,57 @@ static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* QSPI0_SPCLK, QSPI0_SSL */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+ /* QSPI0_IO2, QSPI0_IO3 */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* QSPI1_SPCLK, QSPI1_SSL */
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+ /* QSPI1_IO2, QSPI1_IO3 */
+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */
@@ -3760,8 +3813,10 @@ static const unsigned int vin5_clk_b_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[247];
+ struct sh_pfc_pin_group common[253];
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
struct sh_pfc_pin_group automotive[21];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a),
@@ -3906,6 +3961,12 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_clk_a),
SH_PFC_PIN_GROUP(scif0_ctrl_a),
@@ -4012,6 +4073,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clk_a),
SH_PFC_PIN_GROUP(vin5_clk_b),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4035,6 +4097,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
};
static const char * const audio_clk_groups[] = {
@@ -4088,6 +4151,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4120,6 +4184,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
static const char * const du_groups[] = {
"du_rgb666",
@@ -4305,6 +4370,18 @@ static const char * const pwm6_groups[] = {
"pwm6_b",
};
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
static const char * const scif0_groups[] = {
"scif0_data_a",
"scif0_clk_a",
@@ -4459,8 +4536,10 @@ static const char * const vin5_groups[] = {
};
static const struct {
- struct sh_pfc_function common[47];
+ struct sh_pfc_function common[49];
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
struct sh_pfc_function automotive[4];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -4494,6 +4573,8 @@ static const struct {
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
@@ -4511,12 +4592,14 @@ static const struct {
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -5225,51 +5308,10 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
-static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
- unsigned int pin)
-{
- const struct pinmux_bias_reg *reg;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return PIN_CONFIG_BIAS_DISABLE;
-
- if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
- return PIN_CONFIG_BIAS_DISABLE;
- else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
- return PIN_CONFIG_BIAS_PULL_UP;
- else
- return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
- unsigned int bias)
-{
- const struct pinmux_bias_reg *reg;
- u32 enable, updown;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return;
-
- enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
- if (bias != PIN_CONFIG_BIAS_DISABLE)
- enable |= BIT(bit);
-
- updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
- if (bias == PIN_CONFIG_BIAS_PULL_UP)
- updown |= BIT(bit);
-
- sh_pfc_write(pfc, reg->pud, updown);
- sh_pfc_write(pfc, reg->puen, enable);
-}
-
static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
.pin_to_pocctrl = r8a77990_pin_to_pocctrl,
- .get_bias = r8a77990_pinmux_get_bias,
- .set_bias = r8a77990_pinmux_set_bias,
+ .get_bias = rcar_pinmux_get_bias,
+ .set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A774C0
diff --git a/drivers/pinctrl/renesas/pfc-sh73a0.c b/drivers/pinctrl/renesas/pfc-sh73a0.c
index afabd95105d5..96b91e95b1e1 100644
--- a/drivers/pinctrl/renesas/pfc-sh73a0.c
+++ b/drivers/pinctrl/renesas/pfc-sh73a0.c
@@ -4279,7 +4279,7 @@ static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
return 3300000;
}
-static struct regulator_ops sh73a0_vccq_mc0_ops = {
+static const struct regulator_ops sh73a0_vccq_mc0_ops = {
.enable = sh73a0_vccq_mc0_enable,
.disable = sh73a0_vccq_mc0_disable,
.is_enabled = sh73a0_vccq_mc0_is_enabled,
diff --git a/drivers/pinctrl/renesas/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c
index 15dd007700c2..10020fe302b8 100644
--- a/drivers/pinctrl/renesas/pinctrl-rza1.c
+++ b/drivers/pinctrl/renesas/pinctrl-rza1.c
@@ -931,6 +931,7 @@ static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */
case PIN_CONFIG_OUTPUT_ENABLE:
pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
+ break;
default:
break;
diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c
index 212a4a9c3a8f..ac542d278a38 100644
--- a/drivers/pinctrl/renesas/pinctrl.c
+++ b/drivers/pinctrl/renesas/pinctrl.c
@@ -26,9 +26,8 @@
#include "../pinconf.h"
struct sh_pfc_pin_config {
- unsigned int mux_mark;
- bool mux_set;
- bool gpio_enabled;
+ u16 gpio_enabled:1;
+ u16 mux_mark:15;
};
struct sh_pfc_pinctrl {
@@ -371,12 +370,11 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
goto done;
}
- /* All group pins are configured, mark the pins as mux_set */
+ /* All group pins are configured, mark the pins as muxed */
for (i = 0; i < grp->nr_pins; ++i) {
int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
- cfg->mux_set = true;
cfg->mux_mark = grp->mux[i];
}
@@ -399,7 +397,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
spin_lock_irqsave(&pfc->lock, flags);
if (!pfc->gpio) {
- /* If GPIOs are handled externally the pin mux type need to be
+ /* If GPIOs are handled externally the pin mux type needs to be
* set to GPIO here.
*/
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
@@ -432,11 +430,12 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
spin_lock_irqsave(&pfc->lock, flags);
cfg->gpio_enabled = false;
/* If mux is already set, this configures it here */
- if (cfg->mux_set)
+ if (cfg->mux_mark)
sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);
spin_unlock_irqrestore(&pfc->lock, flags);
}
+#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset, bool input)
@@ -450,8 +449,8 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned int dir;
int ret;
- /* Check if the requested direction is supported by the pin. Not all SoC
- * provide pin config data, so perform the check conditionally.
+ /* Check if the requested direction is supported by the pin. Not all
+ * SoCs provide pin config data, so perform the check conditionally.
*/
if (pin->configs) {
dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
@@ -460,15 +459,13 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
}
spin_lock_irqsave(&pfc->lock, flags);
-
ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
- if (ret < 0)
- goto done;
-
-done:
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
}
+#else
+#define sh_pfc_gpio_set_direction NULL
+#endif
static const struct pinmux_ops sh_pfc_pinmux_ops = {
.get_functions_count = sh_pfc_get_functions_count,
@@ -830,3 +827,46 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
return pinctrl_enable(pmx->pctl);
}
+
+unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+ const struct pinmux_bias_reg *reg;
+ unsigned int bit;
+
+ reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
+ if (!reg)
+ return PIN_CONFIG_BIAS_DISABLE;
+
+ if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
+ return PIN_CONFIG_BIAS_DISABLE;
+ else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))
+ return PIN_CONFIG_BIAS_PULL_UP;
+ else
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+}
+
+void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ unsigned int bias)
+{
+ const struct pinmux_bias_reg *reg;
+ u32 enable, updown;
+ unsigned int bit;
+
+ reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
+ if (!reg)
+ return;
+
+ enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
+ if (bias != PIN_CONFIG_BIAS_DISABLE)
+ enable |= BIT(bit);
+
+ if (reg->pud) {
+ updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
+ if (bias == PIN_CONFIG_BIAS_PULL_UP)
+ updown |= BIT(bit);
+
+ sh_pfc_write(pfc, reg->pud, updown);
+ }
+
+ sh_pfc_write(pfc, reg->puen, enable);
+}
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index eff1bb872325..dc484c13f59c 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -34,10 +34,10 @@ enum {
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
struct sh_pfc_pin {
- u16 pin;
- u16 enum_id;
const char *name;
unsigned int configs;
+ u16 pin;
+ u16 enum_id;
};
#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
@@ -270,8 +270,13 @@ struct sh_pfc_soc_info {
const char *name;
const struct sh_pfc_soc_operations *ops;
+#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
struct pinmux_range input;
struct pinmux_range output;
+ const struct pinmux_irq *gpio_irq;
+ unsigned int gpio_irq_size;
+#endif
+
struct pinmux_range function;
const struct sh_pfc_pin *pins;
@@ -295,9 +300,6 @@ struct sh_pfc_soc_info {
const u16 *pinmux_data;
unsigned int pinmux_data_size;
- const struct pinmux_irq *gpio_irq;
- unsigned int gpio_irq_size;
-
u32 unlock_reg;
};
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
index 5e24838a582f..2223ead5bd72 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
@@ -108,19 +108,14 @@ static int s3c24xx_eint_get_trigger(unsigned int type)
switch (type) {
case IRQ_TYPE_EDGE_RISING:
return EINT_EDGE_RISING;
- break;
case IRQ_TYPE_EDGE_FALLING:
return EINT_EDGE_FALLING;
- break;
case IRQ_TYPE_EDGE_BOTH:
return EINT_EDGE_BOTH;
- break;
case IRQ_TYPE_LEVEL_HIGH:
return EINT_LEVEL_HIGH;
- break;
case IRQ_TYPE_LEVEL_LOW:
return EINT_LEVEL_LOW;
- break;
default:
return -EINVAL;
}
diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c
index e39913a18139..d53a04597cbe 100644
--- a/drivers/pinctrl/spear/pinctrl-spear300.c
+++ b/drivers/pinctrl/spear/pinctrl-spear300.c
@@ -654,8 +654,6 @@ static const struct of_device_id spear300_pinctrl_of_match[] = {
static int spear300_pinctrl_probe(struct platform_device *pdev)
{
- int ret;
-
spear3xx_machdata.groups = spear300_pingroups;
spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
spear3xx_machdata.functions = spear300_functions;
@@ -669,11 +667,7 @@ static int spear300_pinctrl_probe(struct platform_device *pdev)
pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
- ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
- if (ret)
- return ret;
-
- return 0;
+ return spear_pinctrl_probe(pdev, &spear3xx_machdata);
}
static struct platform_driver spear300_pinctrl_driver = {
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
index 19cfd1e76ee2..e69f6da40dc0 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
@@ -677,7 +677,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)),
};
-static const unsigned int a100_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6};
+static const unsigned int a100_irq_bank_map[] = { 1, 2, 3, 4, 5, 6, 7};
static const struct sunxi_pinctrl_desc a100_pinctrl_data = {
.pins = a100_pins,
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 8e792f8e2dc9..dc8d39ae045b 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -1139,8 +1139,9 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
if (irq == pctl->irq[bank])
break;
- if (bank == pctl->desc->irq_banks)
- return;
+ WARN_ON(bank == pctl->desc->irq_banks);
+
+ chained_irq_enter(chip, desc);
reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
val = readl(pctl->membase + reg);
@@ -1148,14 +1149,14 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
if (val) {
int irqoffset;
- chained_irq_enter(chip, desc);
for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
int pin_irq = irq_find_mapping(pctl->domain,
bank * IRQ_PER_BANK + irqoffset);
generic_handle_irq(pin_irq);
}
- chained_irq_exit(chip, desc);
}
+
+ chained_irq_exit(chip, desc);
}
static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,