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authorHariprasad Kelam <hkelam@marvell.com>2023-06-30 11:58:42 +0530
committerDavid S. Miller <davem@davemloft.net>2023-07-02 15:47:18 +0100
commit4c5a331cacda995e995a7857f0e44e8937d98d2c (patch)
tree273d3d568a6ffda8b5a5dbc781d9890e205d6b75 /drivers/net/ethernet/marvell/octeontx2/af/rpm.h
parentc97d3fb9e0e716b77d5c0d3051d46e2f41dc6fe4 (diff)
octeontx2-af: cn10kb: fix interrupt csr addresses
The current design is that, for asynchronous events like link_up and link_down firmware raises the interrupt to kernel. The previous patch which added RPM_USX driver has a bug where it uses old csr addresses for configuring interrupts. Which is resulting in losing interrupts from source firmware. This patch fixes the issue by correcting csr addresses. Fixes: b9d0fedc6234 ("octeontx2-af: cn10kb: Add RPM_USX MAC support") Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/rpm.h')
-rw-r--r--drivers/net/ethernet/marvell/octeontx2/af/rpm.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h
index 22147b4c2137..be294eebab26 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h
@@ -94,7 +94,8 @@
/* CN10KB CSR Declaration */
#define RPM2_CMRX_SW_INT 0x1b0
-#define RPM2_CMRX_SW_INT_ENA_W1S 0x1b8
+#define RPM2_CMRX_SW_INT_ENA_W1S 0x1c8
+#define RPM2_LMAC_FWI 0x12
#define RPM2_CMR_CHAN_MSK_OR 0x3120
#define RPM2_CMR_RX_OVR_BP_EN BIT_ULL(2)
#define RPM2_CMR_RX_OVR_BP_BP BIT_ULL(1)