diff options
| author | Alexander Sverdlin <alexander.sverdlin@nokia.com> | 2019-07-12 12:14:39 +0000 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-08-21 11:09:46 +0300 |
| commit | 913787ca40b9b5981bea1d1157cdd8cb23e12b54 (patch) | |
| tree | 8f09e40d9811c0ecef76c65f1fd900c27f684274 /drivers/mtd/spi-nor/intel-spi.c | |
| parent | 313aca5a9c781a19537e6cc882511c13eff3bdba (diff) | |
mtd: spi-nor: intel-spi: Whitelist 4B read commands
spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes.
Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports
Flash chips up to 64Mbytes.
D-1500 Integrated PCH documenation however has inconsistencies regarding
FADDR register width and says nothing about particular commands issued
to support 64Mbytes of Flash.
Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips
Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and
read operations work just fine after SPINOR_OP_READ_4B and
SPINOR_OP_READ_FAST_4B are white-listed (currently only
SPINOR_OP_READ_FAST_4B is used and only for Macronix).
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'drivers/mtd/spi-nor/intel-spi.c')
| -rw-r--r-- | drivers/mtd/spi-nor/intel-spi.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c index 1ccf23fe7e4b..43e55a2e9b27 100644 --- a/drivers/mtd/spi-nor/intel-spi.c +++ b/drivers/mtd/spi-nor/intel-spi.c @@ -621,6 +621,8 @@ static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len, switch (nor->read_opcode) { case SPINOR_OP_READ: case SPINOR_OP_READ_FAST: + case SPINOR_OP_READ_4B: + case SPINOR_OP_READ_FAST_4B: break; default: return -EINVAL; |