diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2017-08-21 18:02:48 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2017-08-30 15:03:42 +0200 |
| commit | 52899b99767a34050b94d5e2d4b295def2164903 (patch) | |
| tree | 659c2bf303c5efb0c7e6fcf9481ace7004d8c6e3 /drivers/mmc | |
| parent | 130b4bd8f94889e092b8d2fc3c3fe2b483c749a8 (diff) | |
mmc: meson-gx: clean up some constants
Remove unused clock rate defines. These should not be defined but
requested from the clock framework.
Also correct typo on the DELAY register
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/meson-gx-mmc.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index d480a8052a06..8a74a048db88 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -45,9 +45,7 @@ #define CLK_DIV_MAX 63 #define CLK_SRC_MASK GENMASK(7, 6) #define CLK_SRC_XTAL 0 /* external crystal */ -#define CLK_SRC_XTAL_RATE 24000000 #define CLK_SRC_PLL 1 /* FCLK_DIV2 */ -#define CLK_SRC_PLL_RATE 1000000000 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) @@ -57,7 +55,7 @@ #define CLK_PHASE_270 3 #define CLK_ALWAYS_ON BIT(24) -#define SD_EMMC_DElAY 0x4 +#define SD_EMMC_DELAY 0x4 #define SD_EMMC_ADJUST 0x8 #define SD_EMMC_CALOUT 0x10 #define SD_EMMC_START 0x40 |