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authorAbhishek Sahu <absahu@codeaurora.org>2016-11-25 21:11:31 +0530
committerStephen Boyd <sboyd@codeaurora.org>2016-12-21 15:57:28 -0800
commitb52a0c2c11401a8f39b4fcb0b59baf0059902a98 (patch)
tree2b408e4fdeac1c7fbd130c83dd29660794b29696 /drivers/clk/qcom
parent5c1a96935f782c516af585e47020c3e214efd861 (diff)
clk: qcom: ipq4019: correct sdcc frequency and parent name
1. The parent for sdcc clock is sdccpll. 2. The frequency value was wrong so modified the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom')
-rw-r--r--drivers/clk/qcom/gcc-ipq4019.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index f4780c0aaeee..62a36e05dcde 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -124,7 +124,7 @@ static struct parent_map gcc_xo_sdcc1_500_map[] = {
static const char * const gcc_xo_sdcc1_500[] = {
"xo",
- "ddrpll",
+ "ddrpllsdcc",
"fepll500",
};
@@ -549,7 +549,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
F(25000000, P_FEPLL500, 1, 1, 20),
F(50000000, P_FEPLL500, 1, 1, 10),
F(100000000, P_FEPLL500, 1, 1, 5),
- F(193000000, P_DDRPLL, 1, 0, 0),
+ F(192000000, P_DDRPLL, 1, 0, 0),
{ }
};