diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2024-03-07 19:05:29 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2024-03-07 19:05:29 +0000 |
| commit | 88f0912253ea47a2bde36e0820f0b9c025d389ad (patch) | |
| tree | fb477daef419d79cc960de26157e5de2a6fc9b69 /arch/xtensa/include/asm/ptrace.h | |
| parent | 0c5ade742e91d7bf3a508bf6223deb7410009b6d (diff) | |
| parent | 27f2b9fcddc76d542ac339febf2af55b67f610ca (diff) | |
Merge branch 'for-next/stage1-lpa2' into for-next/core
* for-next/stage1-lpa2: (48 commits)
: Add support for LPA2 and WXN and stage 1
arm64/mm: Avoid ID mapping of kpti flag if it is no longer needed
arm64/mm: Use generic __pud_free() helper in pud_free() implementation
arm64: gitignore: ignore relacheck
arm64: Use Signed/Unsigned enums for TGRAN{4,16,64} and VARange
arm64: mm: Make PUD folding check in set_pud() a runtime check
arm64: mm: add support for WXN memory translation attribute
mm: add arch hook to validate mmap() prot flags
arm64: defconfig: Enable LPA2 support
arm64: Enable 52-bit virtual addressing for 4k and 16k granule configs
arm64: kvm: avoid CONFIG_PGTABLE_LEVELS for runtime levels
arm64: ptdump: Deal with translation levels folded at runtime
arm64: ptdump: Disregard unaddressable VA space
arm64: mm: Add support for folding PUDs at runtime
arm64: kasan: Reduce minimum shadow alignment and enable 5 level paging
arm64: mm: Add 5 level paging support to fixmap and swapper handling
arm64: Enable LPA2 at boot if supported by the system
arm64: mm: add LPA2 and 5 level paging support to G-to-nG conversion
arm64: mm: Add definitions to support 5 levels of paging
arm64: mm: Add LPA2 support to phys<->pte conversion routines
arm64: mm: Wire up TCR.DS bit to PTE shareability fields
...
Diffstat (limited to 'arch/xtensa/include/asm/ptrace.h')
0 files changed, 0 insertions, 0 deletions