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authorKrzysztof Kozlowski <k.kozlowski.k@gmail.com>2016-01-11 20:40:28 +0900
committerKrzysztof Kozlowski <k.kozlowski@samsung.com>2016-01-25 15:25:45 +0900
commitcb4f2d7537686e6b0bfad0bc433d1cbd68a7eb08 (patch)
treeeacce7487829d4a39e9f6fd7cfa0f1703bab91d9 /arch/arm
parenta090435727f6ccf0c5e77793ca48681122e5b950 (diff)
ARM: dts: Allow simultaneous usage exynos-rng and s5p-sss drivers on exynos5
The s5p-sss crypto HW acceleration driver supports only AES algorithms thus it accesses only registers from feeder (offset 0x0, length 0x100) and AES (offset 0x200, length 0x100) blocks of Security SubSystem (SSS). The exynos-rng Pseudo Random Number Generator driver accesses only PRNG block at offset 0x400 (length 0x100). Narrow the size of memory mapped by s5p-sss driver so both drivers can be loaded at the same time. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 33e2d5f7315b..234403422c6f 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -807,7 +807,7 @@
sss@10830000 {
compatible = "samsung,exynos4210-secss";
- reg = <0x10830000 0x10000>;
+ reg = <0x10830000 0x300>;
interrupts = <0 112 0>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 48a0a55314f5..7c8a606d65aa 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -859,7 +859,7 @@
sss: sss@10830000 {
compatible = "samsung,exynos4210-secss";
- reg = <0x10830000 0x10000>;
+ reg = <0x10830000 0x300>;
interrupts = <0 112 0>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";