diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2011-11-22 17:30:29 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2011-12-08 10:30:39 +0000 |
| commit | dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89 (patch) | |
| tree | 815a5d36f6d80465ab33686a03af7be9485bfad1 /arch/arm/include/asm/page.h | |
| parent | d675d0bc47f28c5414fbbe17fcc801f69c45b960 (diff) | |
ARM: LPAE: Introduce the 3-level page table format definitions
This patch introduces the pgtable-3level*.h files with definitions
specific to the LPAE page table format (3 levels of page tables).
Each table is 4KB and has 512 64-bit entries. An entry can point to a
40-bit physical address. The young, write and exec software bits share
the corresponding hardware bits (negated). Other software bits use spare
bits in the PTE.
The patch also changes some variable types from unsigned long or int to
pteval_t or pgprot_t.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/include/asm/page.h')
| -rw-r--r-- | arch/arm/include/asm/page.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index ca94653f1ecb..97b440c25c58 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h @@ -151,7 +151,11 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from, #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) extern void copy_page(void *to, const void *from); +#ifdef CONFIG_ARM_LPAE +#include <asm/pgtable-3level-types.h> +#else #include <asm/pgtable-2level-types.h> +#endif #endif /* CONFIG_MMU */ |