diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2014-05-23 09:46:19 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2014-06-17 19:56:34 +0900 |
| commit | 5cc8afcbc47c5f33732fb1a4b37a35841e7494e8 (patch) | |
| tree | 5ac70e26f2fdcba35d9fa6dc585f0eb2ce18b1ae /arch/arm/boot/dts/r8a7779.dtsi | |
| parent | 2909b8746d6f5534aa7714d2df110b3633a59556 (diff) | |
ARM: shmobile: r8a7779 dtsi: Correct #address-cells/#size-cells for clocks
Warning (ranges_format): /clocks has empty "ranges" property but its #address-cells (2) differs from / (1)
Warning (ranges_format): /clocks has empty "ranges" property but its #size-cells (2) differs from / (1)
As r8a7779 doesn't support LPAE, change #address-cells and #size-cells from
"<2>" to "<1>", and update the affected "reg" properties to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7779.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7779.dtsi | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 27bf2274ff08..61d08f42456c 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -284,8 +284,8 @@ }; clocks { - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; ranges; /* External root clock */ @@ -300,7 +300,7 @@ /* Special CPG clocks */ cpg_clocks: clocks@ffc80000 { compatible = "renesas,r8a7779-cpg-clocks"; - reg = <0 0xffc80000 0 0x30>; + reg = <0xffc80000 0x30>; clocks = <&extal_clk>; #clock-cells = <1>; clock-output-names = "plla", "z", "zs", "s", @@ -345,7 +345,7 @@ mstp0_clks: clocks@ffc80030 { compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xffc80030 0 4>; + reg = <0xffc80030 4>; clocks = <&cpg_clocks R8A7779_CLK_S>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, @@ -382,7 +382,7 @@ mstp1_clks: clocks@ffc80034 { compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>; + reg = <0xffc80034 4>, <0xffc80044 4>; clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_S>, @@ -411,7 +411,7 @@ mstp3_clks: clocks@ffc8003c { compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xffc8003c 0 4>; + reg = <0xffc8003c 4>; clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>; #clock-cells = <1>; |