diff options
| author | Matthew McClintock <mmcclint@codeaurora.org> | 2016-03-23 17:05:12 -0500 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2016-04-19 21:42:16 -0500 |
| commit | 9ca595f08e021972e6113dacf06b247a71e09530 (patch) | |
| tree | d31cd8cff1df39a2464950a48080d7ed7c82540b /arch/arm/boot/dts/qcom-ipq4019.dtsi | |
| parent | fd6fd38692171e12aff2ef3ae854de24b1c3a3df (diff) | |
qcom: ipq4019: add DMA nodes to ipq4019 SoC and DK01 device tree
This adds the blsp_dma node to the device tree and the required
properties for using DMA with serial
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq4019.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-ipq4019.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 3cd42c04421b..5c08d19066c2 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -123,6 +123,17 @@ interrupts = <0 208 0>; }; + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; + interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + spi_0: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x78b5000 0x600>; @@ -224,6 +235,8 @@ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 1>, <&blsp_dma 0>; + dma-names = "rx", "tx"; }; serial@78b0000 { @@ -234,6 +247,8 @@ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 3>, <&blsp_dma 2>; + dma-names = "rx", "tx"; }; watchdog@b017000 { |