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authorVidya Sagar <vidyas@nvidia.com>2019-09-05 16:15:49 +0530
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2019-09-08 13:00:59 +0100
commit7ed106d8fdfa4e6cbf9226f49ce921a681c9f240 (patch)
treecee33e6a2758c0f963405a6142969ef6ca910e2e /Documentation
parent151481ef5e360af4ca68835943a036339d3c7826 (diff)
dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
Add optional bindings "vpcie3v3-supply" and "vpcie12v-supply" to describe regulators of a PCIe slot's supplies 3.3V and 12V provided the platform is designed to have regulator controlled slot supplies. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt8
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
index 0ac1b867ac24..b739f92da58e 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
@@ -104,6 +104,12 @@ Optional properties:
specified in microseconds
- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
specified in microseconds
+- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
+ if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
+ in p2972-0000 platform).
+- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
+ if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
+ in p2972-0000 platform).
Examples:
=========
@@ -156,6 +162,8 @@ Tegra194:
0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
vddio-pex-ctl-supply = <&vdd_1v8ao>;
+ vpcie3v3-supply = <&vdd_3v3_pcie>;
+ vpcie12v-supply = <&vdd_12v_pcie>;
phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
<&p2u_hsio_5>;