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authorAdrian Hunter <adrian.hunter@intel.com>2024-06-24 23:10:57 +0300
committerPeter Zijlstra <peterz@infradead.org>2024-07-04 16:00:21 +0200
commit3520b251dcae2b4a27b95cd6f745c54fd658bda5 (patch)
tree8d4339ee1cf737f5021b17c2332876f9a4816b7b /Documentation/hwmon/sht21.rst
parentad97196379d0b8cb24ef3d5006978a6554e6467f (diff)
perf/x86/intel/pt: Fix pt_topa_entry_for_page() address calculation
Currently, perf allocates an array of page pointers which is limited in size by MAX_PAGE_ORDER. That in turn limits the maximum Intel PT buffer size to 2GiB. Should that limitation be lifted, the Intel PT driver can support larger sizes, except for one calculation in pt_topa_entry_for_page(), which is limited to 32-bits. Fix pt_topa_entry_for_page() address calculation by adding a cast. Fixes: 39152ee51b77 ("perf/x86/intel/pt: Get rid of reverse lookup table for ToPA") Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20240624201101.60186-4-adrian.hunter@intel.com
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