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| author | Mark Brown <broonie@kernel.org> | 2024-05-29 11:24:37 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2024-05-29 11:24:37 +0100 |
| commit | 4ccaf60062c3682cf4f1438b143c29648edadfda (patch) | |
| tree | 7e8a3e3f46cc02de85fd3e7c48ac9c091e48b58d /Documentation/devicetree/bindings/spi | |
| parent | d879675bc09a18e2f32c1261cb9e1a15662bc08d (diff) | |
| parent | 9c84429324ea2b5bc537ef8ec7d3727579d37116 (diff) | |
Add support for GPIO based CS
Merge series from Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>:
The Microchip PolarFire SoC SPI "hard" controller supports eight
chip selects. However, only one chip select is physically wired.
Therefore, use GPIO descriptors to configure additional chip select
lines.
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
| -rw-r--r-- | Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml index 74a817cc7d94..ffa8d1b48f8b 100644 --- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml @@ -13,9 +13,6 @@ description: maintainers: - Conor Dooley <conor.dooley@microchip.com> -allOf: - - $ref: spi-controller.yaml# - properties: compatible: oneOf: @@ -43,6 +40,32 @@ required: - interrupts - clocks +allOf: + - $ref: spi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: microchip,mpfs-spi + then: + properties: + num-cs: + default: 1 + + - if: + properties: + compatible: + contains: + const: microchip,mpfs-spi + not: + required: + - cs-gpios + then: + properties: + num-cs: + maximum: 1 + unevaluatedProperties: false examples: |