Merge tag 'riscv-dt-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V DeviceTrees for v6.2

dt-bindings:
- new compatibles to support the StarFive VisionFive & thead CPU cores
- a fix for the PolarFire SoC's pwm binding, merged through my tree as
  suggested by the PWM maintainers

Microchip:
- Non-urgent fix for the node address not matches the reg in a way that
  the checkers don't complain about
- Add GPIO controlled LEDs for Icicle
- Support for the "CCC" clocks in the FPGA fabric. Previously these
  used fixed-frequency clocks in the dt, but if which CCC is in use is
  known, as in the v2022.09 Icicle Kit Reference Design, the rates can
  be read dynamically. It's an "is known" as it *can* be set via
  constraints in the FPGA tooling but does not have to be.
- A fix for the Icicle's pwm-cells
- Removal of some unused PCI clocks

StarFive:
- Addition of the VisionFive DT, which has been a long time coming!

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
  riscv: dts: microchip: remove unused pcie clocks
  riscv: dts: microchip: remove pcie node from the sev kit
  riscv: dts: microchip: fix the icicle's #pwm-cells
  dt-bindings: pwm: fix microchip corePWM's pwm-cells
  riscv: dts: starfive: Add StarFive VisionFive V1 device tree
  riscv: dts: starfive: Add common DT for JH7100 based boards
  dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board
  riscv: dts: microchip: fix memory node unit address for icicle
  riscv: dts: microchip: icicle: Add GPIO controlled LEDs
  riscv: dts: microchip: add the mpfs' fabric clock control

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 3 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
index a7fae1772a81..cd8e9a8907f8 100644
--- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
@@ -30,7 +30,9 @@ properties:
     maxItems: 1
 
   "#pwm-cells":
-    const: 2
+    enum: [2, 3]
+    description:
+      The only flag supported by the controller is PWM_POLARITY_INVERTED.
 
   microchip,sync-update-mask:
     description: |