diff options
| author | Liam Girdwood <liam.r.girdwood@linux.intel.com> | 2014-07-30 20:05:44 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-07-30 13:16:58 +0100 |
| commit | ee4a6ce6cd74a9eace247656c5b109f31c73ab8d (patch) | |
| tree | a4d93c0a641a66a0ed4e6ef6071f7a46faf531aa | |
| parent | afdb74fd708fb4330485212f76a70b91967b1f70 (diff) | |
ASoC: Intel: Fix naming of HMDC register macros.
HMDC is the correct naming for this register.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Jie Yang <yang.jie@intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
| -rw-r--r-- | sound/soc/intel/sst-dsp.h | 8 | ||||
| -rw-r--r-- | sound/soc/intel/sst-haswell-dsp.c | 6 |
2 files changed, 7 insertions, 7 deletions
diff --git a/sound/soc/intel/sst-dsp.h b/sound/soc/intel/sst-dsp.h index 967fb32c981d..21a85eb196f1 100644 --- a/sound/soc/intel/sst-dsp.h +++ b/sound/soc/intel/sst-dsp.h @@ -52,7 +52,7 @@ #define SST_CLKCTL 0x78 #define SST_CSR2 0x80 #define SST_LTRC 0xE0 -#define SST_HDMC 0xE8 +#define SST_HMDC 0xE8 #define SST_SHIM_BEGIN SST_CSR #define SST_SHIM_END SST_HDMC @@ -122,9 +122,9 @@ /* LTRC */ #define SST_LTRC_VAL(x) (x << 0) -/* HDMC */ -#define SST_HDMC_HDDA0(x) (x << 0) -#define SST_HDMC_HDDA1(x) (x << 7) +/* HMDC */ +#define SST_HMDC_HDDA0(x) (x << 0) +#define SST_HMDC_HDDA1(x) (x << 7) /* SST Vendor Defined Registers and bits */ diff --git a/sound/soc/intel/sst-haswell-dsp.c b/sound/soc/intel/sst-haswell-dsp.c index 7b8ad9923fe4..0e1dde8c35e6 100644 --- a/sound/soc/intel/sst-haswell-dsp.c +++ b/sound/soc/intel/sst-haswell-dsp.c @@ -269,9 +269,9 @@ static void hsw_boot(struct sst_dsp *sst) SST_CSR2_SDFD_SSP1); /* enable DMA engine 0,1 all channels to access host memory */ - sst_dsp_shim_update_bits_unlocked(sst, SST_HDMC, - SST_HDMC_HDDA1(0xff) | SST_HDMC_HDDA0(0xff), - SST_HDMC_HDDA1(0xff) | SST_HDMC_HDDA0(0xff)); + sst_dsp_shim_update_bits_unlocked(sst, SST_HMDC, + SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff), + SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff)); /* disable all clock gating */ writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2); |