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authorHarninder Rai <harninder.rai@nxp.com>2016-11-09 23:34:39 +0530
committerShawn Guo <shawnguo@kernel.org>2017-01-29 10:09:44 +0800
commitce3ef577276c1f1a04425c2bf637f2747b17ca84 (patch)
treece1d10c7f784e7ff2c8da17811660fb1f673d73e
parent6d3db2f79b8317853d65569973f54cc9e3fffc46 (diff)
Documentation: DT: add LS1012A compatible for SCFG and DCFG
Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 3b01338c7c29..c9c567ae227f 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -108,7 +108,7 @@ status.
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-scfg",
The following <chip>s are known to be supported:
- ls1021a, ls1043a, ls1046a, ls2080a.
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
- reg: should contain base address and length of SCFG memory-mapped registers
@@ -126,7 +126,7 @@ core start address and release the secondary core from holdoff and startup.
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
- ls1021a, ls1043a, ls1046a, ls2080a.
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
- reg : should contain base address and length of DCFG memory-mapped registers