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authorDan Carpenter <error27@gmail.com>2022-11-29 09:44:57 +0000
committerMauro Carvalho Chehab <mchehab@kernel.org>2022-12-06 07:18:37 +0000
commit94ae11885fae1717f2017cb96ceef5d0f6d6dd4a (patch)
tree81a8e62b8bd08f1b6a2a8d31ada1ba4d1f4dd26f
parente54334cdf86960cc781a6d457fbad1277ca4267c (diff)
media: rzg2l-cru: fix a test for timeout
The test for if the loop timed out is wrong and Smatch complains: drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c:411 rzg2l_csi2_mipi_link_disable() warn: should this be 'timeout == -1' Let's change it to a preop loop instead of a post op loop. Fixes: 51e8415e39a9 ("media: platform: Add Renesas RZ/G2L MIPI CSI-2 receiver driver") Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-rw-r--r--drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
index 3deb09be6400..33e08efa3039 100644
--- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
+++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
@@ -402,7 +402,7 @@ static void rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 *csi2)
rzg2l_csi2_write(csi2, CSI2nRTCT, CSI2nRTCT_VSRST);
/* Make sure CSI2nRTST.VSRSTS bit is cleared */
- while (timeout--) {
+ while (--timeout) {
if (!(rzg2l_csi2_read(csi2, CSI2nRTST) & CSI2nRTST_VSRSTS))
break;
usleep_range(100, 200);