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path:
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arch
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mips
/
sibyte
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bcm1480
/
smp.c
Age
Commit message (
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Author
Files
Lines
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 156
Thomas Gleixner
1
-14
/
+1
2017-08-30
MIPS: SMP: Allow boot_secondary SMP op to return errors
Paul Burton
1
-1
/
+2
2017-08-29
MIPS: SMP: Constify smp ops
Matt Redfearn
1
-1
/
+1
2017-03-02
sched/headers: Prepare for new header dependencies before moving code to <lin...
Ingo Molnar
1
-0
/
+1
2015-08-03
MIPS: SMP: Don't increment irq_count multiple times for call function IPIs
Alex Smith
1
-4
/
+5
2014-05-27
MIPS: SMP: Remove plat_smp_ops cpus_done method.
Ralf Baechle
1
-8
/
+0
2014-03-04
mips: Use the core irq stats function
Thomas Gleixner
1
-1
/
+1
2013-07-14
MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code
Paul Gortmaker
1
-4
/
+4
2012-03-29
documentation: remove references to cpu_*_map.
Rusty Russell
1
-1
/
+1
2012-03-29
remove references to cpu_*_map in arch/
Rusty Russell
1
-3
/
+2
2011-04-14
sched: Provide scheduler_ipi() callback in response to smp_send_reschedule()
Peter Zijlstra
1
-4
/
+3
2009-09-24
cpumask: arch_send_call_function_ipi_mask: mips
Rusty Russell
1
-2
/
+3
2009-01-15
irq: update all arches for new irq_desc, fix
Mike Travis
1
-1
/
+2
2008-12-13
cpumask: centralize cpu_online_map and cpu_possible_map
Rusty Russell
1
-4
/
+4
2008-02-19
[MIPS] BCM1480: Remove stray function call resulting in infinite recursion
Ralf Baechle
1
-1
/
+0
2008-01-29
[MIPS] SMP: Call platform methods via ops structure.
Ralf Baechle
1
-7
/
+94
2007-10-22
[MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.
Ralf Baechle
1
-2
/
+2
2007-10-19
[MIPS] Sibyte: Finish conversion to modern time APIs.
Ralf Baechle
1
-2
/
+3
2007-03-24
[MIPS] SB1250: Fix bugs/warnings by creative use of volatile.
Ralf Baechle
1
-3
/
+3
2006-10-11
[MIPS] Fix compilation warnings in arch/mips/sibyte/bcm1480/smp.c
Mark Mason
1
-3
/
+3
2006-10-08
[MIPS] Complete fixes after removal of pt_regs argument to int handlers.
Ralf Baechle
1
-1
/
+1
2005-10-29
Add support for BCM1480 family of chips.
Andrew Isaacson
1
-0
/
+110