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authorLendacky, Thomas <Thomas.Lendacky@amd.com>2017-06-28 13:43:09 -0500
committerDavid S. Miller <davem@davemloft.net>2017-06-29 15:14:18 -0400
commit9916716a1bb677be8371f602f53989bf04a70d7f (patch)
tree2d7481be8671ef53c4fb7c8c40f94034d021f6a2 /drivers/net/ethernet/amd/xgbe/xgbe-pci.c
parentf00ba49d8ef9b7a8a9f17be4128fad397e42683b (diff)
amd-xgbe: Prepare for more fine grained cache coherency controls
In prep for setting fine grained read and write DMA cache coherency controls, allow specific values to be used to set the cache coherency registers. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/amd/xgbe/xgbe-pci.c')
-rw-r--r--drivers/net/ethernet/amd/xgbe/xgbe-pci.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
index f0c2e88a5037..1e7376887568 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
@@ -327,9 +327,8 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
/* Set the DMA coherency values */
pdata->coherent = 1;
- pdata->axdomain = XGBE_DMA_OS_AXDOMAIN;
- pdata->arcache = XGBE_DMA_OS_ARCACHE;
- pdata->awcache = XGBE_DMA_OS_AWCACHE;
+ pdata->arcr = XGBE_DMA_OS_ARCR;
+ pdata->awcr = XGBE_DMA_OS_AWCR;
/* Set the maximum channels and queues */
reg = XP_IOREAD(pdata, XP_PROP_1);