diff options
| author | Ley Foon Tan <lftan@altera.com> | 2015-04-10 11:10:08 +0800 |
|---|---|---|
| committer | Ley Foon Tan <lftan@altera.com> | 2015-04-10 11:10:08 +0800 |
| commit | 4a89c3088ff61aa24754e9cd6dc665cc719f7efe (patch) | |
| tree | d280b9ad4a94a3aeec310e5764760df685c6ffca /arch/nios2/mm | |
| parent | e3e29f990cc77c5b23280c77275812a3f010cc41 (diff) | |
nios2: fix cache coherency issue when debug with gdb
Remove the end address checking for flushda function. We need to flush
each address line for flushda instruction, from start to end address.
This is because flushda instruction only flush the cache if tag and line
fields are matched.
Change to use ldwio instruction (bypass cache) to load the instruction
that causing trap. Our interest is the actual instruction that executed
by the processor, this should be uncached.
Note, EA address might be an userspace cached address.
Signed-off-by: Ley Foon Tan <lftan@altera.com>
Diffstat (limited to 'arch/nios2/mm')
| -rw-r--r-- | arch/nios2/mm/cacheflush.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/nios2/mm/cacheflush.c b/arch/nios2/mm/cacheflush.c index 2ae482b42669..796642932e2e 100644 --- a/arch/nios2/mm/cacheflush.c +++ b/arch/nios2/mm/cacheflush.c @@ -23,9 +23,6 @@ static void __flush_dcache(unsigned long start, unsigned long end) end += (cpuinfo.dcache_line_size - 1); end &= ~(cpuinfo.dcache_line_size - 1); - if (end > start + cpuinfo.dcache_size) - end = start + cpuinfo.dcache_size; - for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) { __asm__ __volatile__ (" flushda 0(%0)\n" : /* Outputs */ |