diff options
| author | Liu Yibin <jiulong@linux.alibaba.com> | 2020-04-21 15:56:28 +0800 |
|---|---|---|
| committer | Guo Ren <guoren@linux.alibaba.com> | 2020-05-13 17:55:05 +0800 |
| commit | 165f2d2858013253042809df082b8df7e34e86d7 (patch) | |
| tree | aeccca734fe97d89105a3674fc30d7355e6581fe /arch/csky/abiv2 | |
| parent | c2e59d1f4df8783856a4e6a05a7d4a76d7cf7082 (diff) | |
csky: Fixup msa highest 3 bits mask
Just as comment mentioned, the msa format:
cr<30/31, 15> MSA register format:
31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BA Reserved SH WA B SO SEC C D V
So we should shift 29 bits not 28 bits for mask
Signed-off-by: Liu Yibin <jiulong@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/abiv2')
| -rw-r--r-- | arch/csky/abiv2/inc/abi/entry.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/csky/abiv2/inc/abi/entry.h b/arch/csky/abiv2/inc/abi/entry.h index a99aff555a0a..ab63c41abcca 100644 --- a/arch/csky/abiv2/inc/abi/entry.h +++ b/arch/csky/abiv2/inc/abi/entry.h @@ -285,8 +285,8 @@ */ mfcr r6, cr<30, 15> /* Get MSA0 */ 2: - lsri r6, 28 - lsli r6, 28 + lsri r6, 29 + lsli r6, 29 addi r6, 0x1ce mtcr r6, cr<30, 15> /* Set MSA0 */ |