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authorVeerabhadrarao Badiganti <vbadigan@codeaurora.org>2020-03-11 22:44:21 +0530
committerBjorn Andersson <bjorn.andersson@linaro.org>2020-03-11 22:43:43 -0700
commit557a2aba5b832f80814b8821164108cacc5b0dca (patch)
treec9c0e0c38a6e0846290e98f1ff56a53c029d965f
parent5bcdf1009f1bf49f05812c5c33e948edd8845fe1 (diff)
arm64: dts: qcom: qcs404: Enable CQE support for eMMC
Enabling CQE support for eMMC by supplying the correct reg name and flag which indicates CQE support. Also remove the redundant _mem suffix for reg names. Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/1583946863-24308-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-rw-r--r--arch/arm64/boot/dts/qcom/qcs404-evb.dtsi1
-rw-r--r--arch/arm64/boot/dts/qcom/qcs404.dtsi2
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 522d3ef72df5..afe69e8f3114 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -200,6 +200,7 @@
&sdcc1 {
status = "ok";
+ supports-cqe;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 1eea06435779..f149a538c1cc 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -687,7 +687,7 @@
sdcc1: sdcc@7804000 {
compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
- reg-names = "hc_mem", "cmdq_mem";
+ reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;