diff options
| author | Joachim Eastwood <manabian@gmail.com> | 2016-05-01 22:58:22 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-05-03 15:22:20 -0400 |
| commit | 537372472415b7b75856561d23891a0bf3477ea4 (patch) | |
| tree | fe46d8fc7bc0248473ca9bb2ed27f7e0a7802cd1 | |
| parent | 70cb136f7730830aa1134925a941e3ad96e3a846 (diff) | |
stmmac: dwmac-socfpga: call phy_resume() only in resume callback
Calling phy_resume() should only be need during driver resume to
workaround a hardware errata.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Tested-by: Marek Vasut <marex@denx.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 50 |
1 files changed, 19 insertions, 31 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c index ba0b7934cc95..ba49d8c14958 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -198,41 +198,11 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac) static int socfpga_dwmac_init(struct platform_device *pdev, void *priv) { struct socfpga_dwmac *dwmac = priv; - struct net_device *ndev = platform_get_drvdata(pdev); - struct stmmac_priv *stpriv = NULL; - int ret = 0; - - if (!ndev) - return -EINVAL; - - stpriv = netdev_priv(ndev); - if (!stpriv) - return -EINVAL; /* Setup the phy mode in the system manager registers according to * devicetree configuration */ - ret = socfpga_dwmac_setup(dwmac); - - /* Before the enet controller is suspended, the phy is suspended. - * This causes the phy clock to be gated. The enet controller is - * resumed before the phy, so the clock is still gated "off" when - * the enet controller is resumed. This code makes sure the phy - * is "resumed" before reinitializing the enet controller since - * the enet controller depends on an active phy clock to complete - * a DMA reset. A DMA reset will "time out" if executed - * with no phy clock input on the Synopsys enet controller. - * Verified through Synopsys Case #8000711656. - * - * Note that the phy clock is also gated when the phy is isolated. - * Phy "suspend" and "isolate" controls are located in phy basic - * control register 0, and can be modified by the phy driver - * framework. - */ - if (stpriv->phydev) - phy_resume(stpriv->phydev); - - return ret; + return socfpga_dwmac_setup(dwmac); } static int socfpga_dwmac_probe(struct platform_device *pdev) @@ -290,6 +260,24 @@ static int socfpga_dwmac_resume(struct device *dev) socfpga_dwmac_init(pdev, priv->plat->bsp_priv); + /* Before the enet controller is suspended, the phy is suspended. + * This causes the phy clock to be gated. The enet controller is + * resumed before the phy, so the clock is still gated "off" when + * the enet controller is resumed. This code makes sure the phy + * is "resumed" before reinitializing the enet controller since + * the enet controller depends on an active phy clock to complete + * a DMA reset. A DMA reset will "time out" if executed + * with no phy clock input on the Synopsys enet controller. + * Verified through Synopsys Case #8000711656. + * + * Note that the phy clock is also gated when the phy is isolated. + * Phy "suspend" and "isolate" controls are located in phy basic + * control register 0, and can be modified by the phy driver + * framework. + */ + if (priv->phydev) + phy_resume(priv->phydev); + return stmmac_resume(dev); } #endif /* CONFIG_PM_SLEEP */ |