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authorJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>2019-11-25 15:25:07 +0100
committerBjorn Andersson <bjorn.andersson@linaro.org>2020-01-04 23:56:42 -0800
commit40b3d9404384d0012f23f80a1e3d8c699cadc5e6 (patch)
treeb7824cb9bf43ff33e96787d49af44d01ba3b2eaf
parent118764988c8e62ffb6e7086db3531ffee2bd5f2d (diff)
arm64: dts: qcom: qcs404: Add HFPLL node
The high frequency pll functionality is required to enable CPU frequency scaling operation. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191125142511.681149-3-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-rw-r--r--arch/arm64/boot/dts/qcom/qcs404.dtsi9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index c9e8e629045b..b5dff2aa1ab4 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -904,6 +904,15 @@
#mbox-cells = <1>;
};
+ apcs_hfpll: clock-controller@b016000 {
+ compatible = "qcom,hfpll";
+ reg = <0x0b016000 0x30>;
+ #clock-cells = <0>;
+ clock-output-names = "apcs_hfpll";
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
+
watchdog@b017000 {
compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
reg = <0x0b017000 0x1000>;